JPS63251846A - Storage device control system - Google Patents

Abstract

PURPOSE:To improve the throughput by securing the priority logic among the request signals received from each requesting device, the write instruction discriminating signals, a busy signal of the preceding cycle, a reading action discriminating signal and a 1-bit error detecting signal respectively and deciding whether the acceptance should be sent back to each requesting device or not. CONSTITUTION:A priority circuit 11 of a memory M secures the priority logic among requesting signals 17 and 18 received from the requesting devices A and B, the write instruction discriminating signals 19 and 20, a bush signal 36 of the preceding cycle produced in the memory M, a reading action discriminating signal 35, and a 1-bit error detecting signal 42 respectively. Then the circuit 11 decides whether or not the acceptance should be sent back to the devices A and B. Thus it is possible to shorten the cycle time by the priority logic as long as no conflict is caused between the read and write data. As a result, the overall system throughput is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a storage device control system, and in particular, the present invention relates to a storage device control system, and in particular, request control between each requesting device and a storage device connected via a common bus. This invention relates to operation cycle control when read data is on a common line.

[Conventional technology]

Conventionally, in systems where each requesting device such as an arithmetic processing unit, an input/output processing unit, etc. and a storage device are connected by a common bus, and write data and read data are shared on a common line, read data and write data may conflict with each other. The write operation after the read operation when a 1-bit error occurs is a critical cycle, and the cycle time of the read operation is determined by this.

[Problem that the invention seeks to solve]

In the conventional operation unit cycle busy control described above, 1
The cycle time of the read operation is determined by the write operation after the read operation when a bit error occurs. Therefore, in the case of a write operation after a read operation in which no one-bit error occurs, there is a drawback that the cycle time cannot be shortened even though there is no conflict between read data and write data.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a storage device that can shorten the cycle time when there is no conflict between read data and write data in a write operation after a read operation in which no one-bit error occurs. The purpose is to provide a control system.

[Means for solving problems]

In the storage device control system of the present invention, each requesting device such as an arithmetic processing unit, an input/output processing device, etc. and the storage device are connected by a common bus, and write data and read data are transmitted through a common line.
In a system that transfers corrected data with a delay of one clock cycle after the occurrence of a 1-bit error, (1) each request device is provided with a request control circuit that simultaneously transfers a request request signal and a write command identification signal to the storage device, (1) The storage device includes a main control circuit that generates a busy signal and a read operation identification signal for the previous cycle, an error detection circuit that generates a 1-bit error detection signal for the previous cycle, a busy signal, each write instruction identification signal, The device includes a priority circuit which inputs a read operation identification signal, a 1-bit error detection signal, and each request request signal, and returns an accept to the requesting device according to the priority of these signals.

Therefore, in the priority circuit in the storage device, the request request signal and write instruction identification signal transferred from each requesting device, the busy signal and read operation identification signal of the previous cycle generated in the storage device, and the Priority logic is used with the bit error detection signal to control whether or not to return an accept to each requesting device. Therefore, after a 1-bit error occurs in a read operation, in the case of a write operation after a read operation without a 1-bit error, if there is no conflict between the read data and the write data, the cycle time can be shortened using priority logic. Can be done.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage device control system according to the present invention, and FIG. 2 is a timing diagram for explaining the operation of FIG. 1. In FIG. 2, the dotted line indicates the case where there was no 1-bit error in the previous successive cycle.

In FIG. 1, when requesting device A or B makes a request to storage device M, request control circuit 1 or 2 of requesting device A or B always sends the request request signal 19 or 20 as well. At the same time as 17 or 18, the data is transferred to the priority circuit 11 of the storage device M. When the priority circuit 11 of the storage device tM receives the request request signal 17 or 18 and the write instruction identification signal 19 or 20, it outputs these signals, the busy signal 36 of the previous cycle, and the read operation identification signal 35 of the previous cycle. The priority logic is determined by the 1-bit error detection signal 42 from the error detection circuit 41, and the requesting device Δ or B hair accept signal 21 or 22 is returned.

The priority logic in this case is as follows. That is, RQl is the request request signal of requesting device A, R
Q2 is the request request signal of the requesting device B, WTI is the write command identification signal of the requesting device A, WT2 is the write command identification signal of the requesting device B, MRD is the read operation identification signal of the storage device M, and SER is the storage device M 1-bit error detection signal, M
BSY is the busy signal of storage device M, and RQ
, and RQ, let RQ2 < RQ,
Then, the return of the accept signal 21 to the requesting device A is as follows.

RQ, * ((SBR+MRD) * WTI)
* The return of the MBSY requester/requester child request signal 22 is as follows.

This will be explained below with reference to FIG.

For example, when the request request signal 17 requesting a read operation is transferred from the requesting device A to the storage device M, the priority circuit 11 of the storage device M requests the request according to the logic described above because the busy signal 36 is logic “0”. An accept signal 21 is sent back to device A.

In addition, the priority circuit 11 generates an operation start signal 34.
is sent to the main control circuit 12 and a read operation is executed. When this read operation is executed, the busy signal 36 becomes logic "1" for one clock cycle (abbreviated as IT). Further, a read operation identification signal 35 is sent from the main control circuit 12 to the priority circuit 11.

Next, the request request signal 18 is sent from the request device B 2T after the previous request request signal 17 when the busy signal 36 becomes logic "0". If the main operation request of the request request signal 18 is a read operation, the storage device M returns an accept signal 22 to the requesting device RB since the write command identification signal 20 is logic "0". However, when the main operation request of the request request signal 18 is a write operation, the write command identification signal 20 is set to logic "1" as shown in the figure.
Since the read operation identification signal 35 is logic "1", the storage device M does not return the accept signal 22 to the requesting device B. Therefore, the request request signal 18 is sent to the storage device M from the requesting device B after IT again. At this point, the read operation identification signal 35 is at logic "0'". Therefore, if a 1-bit error is not detected by the error detection circuit 41 based on the error control signal 43 in the previous read operation cycle, the 1-bit error detection signal 42 is "0", so the accept signal 22 is sent to the requesting device. It is sent back to B. Furthermore, if a 1-bit error is detected in the previous read operation cycle, the storage device M does not return the accept signal 22 to the requesting device B because the 1-bit error detection signal 42 is logic "1".

Therefore, the request requesting device 18 is sent from the post-IT requesting device B to the storage device M again and again. At this point, the read operation identification signal 35 and the 1-bit error detection signal 42
is logic "0", the accept signal 22 is returned to the requesting device B. Here, the write command identification signal 20 is logic "1", and the 1-bit error detection signal 42 is logic "1".
'' means that a 1-bit error occurred in the previous read operation cycle, the cycle 2T or 3T later is a write operation, and the read correction data 40 and write data 28 are in conflict. do.

In FIG. 1, the command/write masks 23 and 24 in the requesting devices A and B are sent from the bus driver 3.4 as the command/write mask 31 to the bus receiver 13 in the memory bag RM, and the command/write mask 37 is sent to the bus receiver 13 in the memory bag RM. The signal is supplied to the main control circuit 12 as a signal. Further, addresses 25 and 26 are sent as address 32 to path receiver 14 in storage device M via bus driver 5.6 and used as address 38. Write data 27, 28 and read data 4
0 is sent by the bus driver 7.8.16 as common data 33 and received by the path receiver 9.10.15 as write data 39 or read data 29.30 in the requesting device ASB or in the storage device M. It has become.

As can be seen from the above explanation, each requesting device Δ, B and the storage device M are connected by a common bus, the write data and the read data are on a common line, and one bit error occurs in the read operation cycle in the storage device M. In a system that transfers corrected data with a delay of one clock cycle after the occurrence of
The priority circuit 11 of the storage device M receives the request request signal 1 transferred from each requesting device A and B in this case.
7.18, the write command identification signal 19.20, the busy signal 36 of the previous cycle generated in the storage device M, the read operation identification signal 35, and the 1-bit error detection signal 42 are used to determine the priority logic, and an acceptance is determined. Each requesting device controls whether or not to send back to the ASB. As a result, conventionally, when a 1-bit error occurs in a read operation, the cycle time of the subsequent read operation is entirely determined by the write operation after the read operation related to the occurrence of this 1-bit error. In the invention, by using the above-described priority logic, the cycle time of the next read operation after the write operation after the read operation related to the occurrence of a 1-bit error is determined so that there is no conflict between the read data and the write data. In subsequent read operations after write operations, unless a 1-bit error is newly detected in the previous read operation cycle, the cycle time is further changed and returned to the original cycle time, thereby reducing the cycle time. Therefore, after a 1-bit error occurs in a read operation, 1
In the case of a write operation after a read operation that does not cause a bit error, if there is no conflict between read data and write data, cycle time can be shortened using priority logic, improving overall system throughput. can be achieved.

The present invention is not limited to the present embodiments, and various applications and modifications can be made without departing from the gist of the present invention.

〔Effect of the invention〕

As described above, if the present invention is used, the priority circuit uses the request request signal and write command identification signal transferred from each requesting device, and the request signal and write command identification signal generated within the storage device.
Priority logic is used between the previous cycle's busy signal, read operation identification signal, and 1-bit error detection signal to control whether or not to send an accept back to each requesting device, so 1-bit errors occur in read operations. In the case of a write operation after a read operation in which a 1-bit error does not occur, if there is no conflict between read data and write data, the cycle time can be shortened by using priority logic, which improves the overall system efficiency. This has effects such as being able to improve throughput.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing diagram for explaining the operation of FIG. 1. 1.2...Request control circuit, 11...
...Priority circuit, 12...Main control circuit, 17.18...Request request signal, 19.2
0...Write command identification signal, 21.22...
...Accept signal, 27.28.39...Write data, 29.30.40...Read data,
33... Common data, 35... Read operation identification signal, 36... Busy signal, 41... Error detection circuit, 42... 1-bit error detection signal. Applicant: NEC Corporation

Claims (1)

[Claims] Each requesting device such as an arithmetic processing unit, an input/output processing unit, etc. and a storage device are connected by a common bus, and write data and read data are shared on a common line, and after a 1-bit error occurs, corrected data is transmitted with a delay of 1 clock cycle. In the transfer system, each of the requesting devices includes a request control circuit that simultaneously transfers a request request signal and a write instruction identification signal to the storage device, and the storage device receives a busy signal and a read operation identification signal of the previous cycle. a main control circuit that generates a signal, an error detection circuit that generates a 1-bit error detection signal of the previous cycle, the busy signal, each write instruction identification signal, the read operation identification signal, and the 1-bit error detection signal. and a priority circuit which receives the request request signals and returns an accept to the requesting device according to the priority of these signals.