JPS6126104B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a main memory access method from each processor in a multiprocessor system including multiple CPUs (central processing units) and multiple IOPs (input/output processors). It is something.

Prior Art Multiprocessor systems are classified into several types based on the differences in the structure of the bus, which is a transfer route for address information and data between processor main memory devices (References: For example, PHILIP H
ENSLOW edition “Multiprocessors and Parallel
One typical type uses a single bus between all processors and main memory; another typical type uses an independent bus between each processor and main memory. There are multi-bus structures that occupy a middle position between the above two extremes.
A type is known in which the bus between the main storage devices and the bus between the IOP and the main storage device are separated.

In systems such as this, where the CPU system and IOP system buses are independent, main memory access control is usually common to all processors, and the access control phase (request exchange, address, data phase, etc.) is designed to be in a common phase. has been done. As a result, the access control phase is determined in accordance with the furthest processor, so dead time occurs in the access control phase of the processor closest to the main memory. That is, a system consisting of only nearby processors and only a main memory device allows high-speed main memory access, whereas a system in which many processors are connected to a bus has the problem that the access time of the nearby processors increases.

purpose of invention The present invention solves the above problems.

General Description of the Invention The present invention is based on a multiprocessor system having a common bus between a group of processors and a main memory, and having at least two series of such processor groups and the common bus. shall be. for example
An example of this is a multiprocessor configuration that separates a bus dedicated to the CPU and a bus dedicated to the IOP. In such a system, the main memory device includes an input means (a selection circuit 2 described later) for selectively inputting information on each bus.
1 and register 22 correspond to this. ), and a main memory access request processing circuit that is provided for each bus and that receives main memory access requests from each processor and performs reception processing for each (acceptance circuits 40 and 41 shown in the embodiment described later correspond to this). ), and each main memory access request processing circuit transfers access requests from processors connected to the corresponding bus to information specific to that bus so that information can be input from each bus to the input means in a common phase. Access requests to the bus are controlled at timings according to the delay. The gist of the present invention is a memory control method. For example, when separating the CPU-dedicated bus and the IOP-dedicated bus as described above, a two-level main memory access request processing circuit is provided.

As described above, as an effect of the present invention, the main memory access time of a group of processors having a short bus length is increased.

Note that when implementing the present invention, the following points should be taken into consideration.

(a) The control of the main memory access request processing circuit is simplified when timing control is performed using a common phase for all buses for information exchange between the common bus and the main memory device.

(b) Handling contention of main memory access requests that occur between processors. For example, each main memory access request processing circuit is designed to have a different start timing phase for accepting the access request, and while one processing circuit is accepting and processing the access request, other processing circuits are inhibited from accepting access requests. It has the function to Furthermore, a priority is set between the reception start timing phases, that is, between the main memory access request processing circuits, and reception of pending requests is controlled in accordance with this priority. For example, between the CPU-related reception circuit and the IOP-related reception circuit, the latter is given a high priority, and when a request from the CPU and a request from the IOP are pending at the same time, the reception circuit related to the IOP prioritizes requests from the IOP and
Suppresses acceptance for the related acceptance circuit.

(c) As a modification of item (a) above, since the main memory access request circuit performs a Hamming check when reading information from the main memory and places it on the common bus, Hamming correction is performed for at least one series of the common bus. The timing can be controlled so that the previous information is loaded earlier, and in other cases, the timing can be controlled using a common phase for all buses according to the principle in section (a).

Embodiment of the Invention An embodiment of the present invention will be described below. FIG. 1 is a diagram showing a bus structure between processors and main memory devices, and FIG. 2 is a diagram showing a control system regarding requests from the processor to the main memory device. In Figures 1 and 2, 1, 2, 3, 4 are IOPs, 5, 6 are CPUs,
100 is a main storage device (hereinafter simply referred to as memory)
shows. 10 is a bus that connects the IOP and memory, and 11 is a bus that connects the CPU and memory. Both buses have a structure divided into addresses, data (shared for read and write data), and control information (partial write flag, etc.). Signal lines 31, 32, 3
3 and 34 are memory access request signal lines from IOP1, 2, 3, and 4, respectively, and 35 and 36 are respectively
This is the same request signal line from CPUs 5 and 6. The bus information from the processor to the memory 100 is determined by the selection circuit 21, which selects either bus 10 or 11 from the reception circuit 4.
Register 22 selected by instructions from 0 and 41
will be incorporated into. On the other hand, data read from the memory is transferred from the data register 23 to the bus 10 or 11.
be carried on.

40 is a control circuit for accepting memory access requests from the IOP, and 41 is a control circuit for accepting memory access requests from the CPU. 51, 52, 53, 54,
55 and 56 are processors 1, 2, 3, and
This is an acceptance signal in response to an access request from 4, 5, and 6, and this is reflected on flip-flops (hereinafter abbreviated as FF) 61, 62, 63, 64, 65, and 66.

Next, a detailed explanation of the operation will be given.

First, a read request from the CPU will be explained. In FIG. 2, an access request from the CPU 5 is sent to the memory 100 via the signal line 35 and enters the reception circuit 41. If it is accepted here, the acceptance FF 65 is set to "1" by the acceptance signal line 55. This situation is shown in the time chart of FIG. One machine cycle consists of 4 clocks T ₀ , T ₁ ,
Consists of T ₂ and T ₃ . The output signal of the FF 65 is sent to the CPU 5, and the CPU 5 uses this signal to load the memory address and control information onto the bus 11.

FIG. 3 shows the phase of this bus as seen from the memory 100 side. The information on this bus is selected by the selection circuit 21 and taken into the register 22 by the clock T1. The data read in the memory 100 is taken into the data register 23 at T3 and immediately transferred to the bus 11.
It is put on the data line and sent to CPU5.
The CPU 5 takes in this data and the access ends. The above series of processing is a known technique, and detailed explanation of the circuit will be omitted.

Next, processing of a write access request by the CPU will be explained. A write request from the CPU 5 is sent to the memory 100 via the signal line 35, and when it is accepted, the FF
65 is set to "1" and the same output is sent to the CPU 5, which is exactly the same as the read request including the phase. Upon receiving this signal, the CPU 5 sends the write address, write data, and control information onto the bus 11 to the memory 100. memory 100
takes this into register 22 using the T1 clock,
Perform memory write operation. The phase of this series of controls is the same as the read access process. However, unlike reading, the read data is not sent to the CPU.

Memory access requests from the CPU 6 are also made in the same way as the CPU 5.

When memory access requests occur simultaneously in CPU5 and CPU6, the reception circuit 41 always
Accepts CPU5 with priority. Further, when a memory access request from the CPU 5 or 6 comes to the memory 100, if the memory 100 is busy processing the advance access request, the acceptance circuit 41 accepts this access request after the advance memory access is completed.

Next, the IOP memory read request will be explained. Read access request from IOP1 is signal line 3
1 is sent to the acceptance circuit 40, and when accepted there, FF61 is set to ``1'' on the signal line 51. Although not shown, the output signal of the FF 61 is sent to the IOP 1, and the IOP 1 receives the signal and puts the address and control information on the bus 10. This situation is shown in FIG. By the way, CPU 5 or 6 is implemented.
is placed near the memory 100, and the IOP is placed far away. Therefore, the memory access request signal line and its acceptance report signal line are longer in the IOP than in the CPU, and the bus 10 is longer than the bus 11. Therefore, as shown in FIG. 4, the phase relationship of processing the memory read request from IOP1 is
The time required for processing a read request is longer than the phase of communication with the memory. That is, the access request for IOP1 is sent by clock T1, but the access request from reception circuit 4
Accepts the signal accepted with 0 and sets it to FF61 as “1”
The only value that can be set is _T0 . The output of this FF61 is immediately sent to IOP1, and IOP1 performs control to transfer address and control information to bus 10, but it takes time for this to reach memory 100 because the bus is long, and the phase shown in Figure 4 is shown in Figure 4. The memory 100 takes this into the register 22 at the same clock T1 as the CPU access. The subsequent operation within the memory 100 is the same as the read access request processing by the CPU, and the read data is clocked by the clock T.
3, it is set in the data register 23. This data is immediately put on bus 10 and sent to IOP1. IOP1 takes this into IOP1 when it arrives. In this way, the IOP read access request processing is different from the case where the acceptance control is the CPU, and the time is extended due to the difference in physical distance, but after the address is read into the memory 100, it is exactly the same as the CPU. Processing occurs within memory 100. The sending phase of read data is also the same as that of the CPU access. The phase of taking in read data into IOP1 is delayed by the longer bus length than in the case of the CPU.

Next, memory write request processing from IOP1 will be explained. A write access request is sent from IOP1 to memory 100, this is accepted by acceptance circuit 40, and the output of this acceptance FF61 is sent to IOP1.
1, IOP1 accepts it and sends it to bus 10.
Place the address, write data, and control information on the .
The contents of this bus 10 are loaded into register 22 at clock T1. The phase relationship of this series of processing is the same as in FIG. 4, which shows the processing of a read access request of IOP1. The memory 100 performs a memory write operation based on the information taken into the register 22, but this memory internal processing is performed in the same phase and in the same manner as the CPU's write request processing.

Memory read and write request processing from IOP2, 3, and 4 is the same as for IOP1.

When a plurality of access requests occur simultaneously among IOPs 1, 2, 3, and 4, the reception circuit 40 prioritizes IOPs 1, 2, 3, and 4 in this order. For example, if both IOPs 1 and 2 issue memory access requests (regardless of the type of read or write) at the same time, the memory acceptance circuit 40 will:
First, accept the request for IOP1, process it, and then
The access request No. 2 is made to wait until the access processing of IOP1 is completed. Furthermore, if an advance access request has already entered the memory 100 and is being processed when an access request from an IOP occurs, acceptance of this new IOP access request is delayed until the end of processing of the advance access request.

Next, a case where memory access requests occur simultaneously between the IOP and the CPU will be explained with reference to FIG. Now consider a case where IOP3 and CPU5 simultaneously issue memory read requests. At this time, reception circuit 4
If it is 0, there is no advance access request and there are no access requests from other IOPs, the read request for IOP3 is immediately accepted and the acceptance FF 63 is set to "1". The output signal of this FF63 is immediately sent to the IOP3. The IOP 3 accepts this, carries the address and control information on the bus 10, and sends it to the memory 100. The memory 100 takes this into the register 22 and performs read access processing. FIG. 5 shows these phase relationships. The read data is set in the data register 23 by the clock T3, transferred to the bus 10, and sent to the IOP3.
The memory 100 has now finished processing the read access request from the IOP 3, and as shown in FIG. 5, the receiving circuit 41 accepts the read access request from the CPU 5, which has been kept waiting, and this access processing is started. When an IOP access request and a CPU access request come to memory 100 at the same time like this,
The acceptance circuit 40 accepts the IOP access request and begins its processing, but at the same time, the signal line 50 inhibits the acceptance control circuit 41 from accepting the CPU memory access request. Next, processing of this IOP access request begins, and if a memory access request from another IOP comes while the CPU access request is waiting, it will be processed in advance.
When the IOP access request processing is completed, the subsequent
IOP memory access requests are accepted first,
CPU memory access requests are made to wait until they are completed. In this process, the same control is performed for memory access requests between any IOP and any CPU, regardless of the type of memory access request, read or write.

In the above embodiment, one machine cycle consists of four phases, but the same applies to a case where one machine cycle consists of n phases. Further, the memory read time in the memory 100 is an example in which it takes 2 1/2 machine cycles, but this depends on the performance of the memory 100.

Next, in the above embodiment, for both CPU and IOP memory read requests, the read data is sent to both the CPU and IOP memory buses in the same phase, but the data before Hamming correction and the data after correction are selected and transferred to the bus. It is also possible to provide a means for putting the read data on the bus, and then, when a 1-bit error is detected, after the read data is sent out on the bus, the corrected data is put on the bus again and sent again. 6th
The figure shows the relationship between the Hamming correction circuit and the bus. In the figure, 200 is a data register that holds the data read from the memory but before Hamming correction; 201;
1 shows a Hamming correction circuit, which performs Hamming check and correction processing when a 1-bit error occurs. 202
is a data register in which data after being subjected to Hamming correction processing is set. For both CPU and IOP memory read requests, the read data enters the data register 200 and then enters the Hamming correction circuit 201, and if it is a 1-bit error, correction processing is performed, and if it is normal, it is set in the data register 202 as it is.

In response to a memory read request from the CPU, the contents of the register 200 before Hamming correction are first selected by the selector 203 in FIG. 6, and the data is loaded onto the CPU bus 11. In parallel with this, the Hamming correction circuit 20
A humming check is performed at step 1, and if normal, no new data is loaded onto the CPU bus 11, as shown in FIG. If there is a Hamming 1-bit error, the 8th
As shown in the figure, the data on which error bits have been corrected is transferred from the register 202 via the selector 203 to the bus 11 and sent to the CPU.

An IOP memory read request is processed in the same way, and data is transferred from the selector 204 to the IOP bus 10.

In addition, in response to a CPU read request, the data before Hamming correction is sent, and when correction is made, the corrected data is sent to the bus again, but in response to an IOP memory read request, data is always sent only from the corrected register. It is also possible to use a system that facilitates control by sending the data to the bus.

In this example, the number of IOPs is 4 and the number of CPUs is 2.
However, any number may be used. Also, the bus is IOP
Although there are two, one for the system and one for the CPU, three or more may be provided. Furthermore, it is clear that the present invention can be applied even if the processors are not clearly grouped into the IOP system and the CPU system, but a bus is provided for the grouped processors as necessary.

It is also clear that the gist of the present invention does not change even if the bus is not divided into address lines, data lines, and control lines, and addresses and data are transferred on one bus at different times.

The present invention can also be applied to a control system in which the memory contents are divided into a plurality of banks and the reception is made fine-grained.

In addition, when accepting memory access requests, instead of always giving priority to CPU 5 over CPU 6 as mentioned in the example, you can also choose a replacement CPU when there are simultaneous requests, such as giving priority to the CPU opposite to the previous reception. good.

Effects of the Invention As described above, separate buses are established between one group of processor systems and another group of processor systems, for example, the IOP system and the CPU system, and the IOP system's memory reception circuit and
The CPU system memory reception circuit is provided separately, and the operating phases of these two reception circuits are different, so that the two-level reception of IOP system and CPU system reception is performed in terms of phase, so the CPU memory access processing is independent of the IOP's bus length, and the CPU
This has the effect of speeding up memory access.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the bus structure between the processor main memory devices in an embodiment of the present invention, FIG. 2 is a diagram showing the control system regarding requests from the processor to the main memory device, and FIG. 3 is a diagram showing the CPU read access. Request processing time chart, Figure 4 is IOP
Time chart for processing read access requests,
Figure 5 is a time chart of simultaneous occurrence of both CPU read and IOP read requests, Figure 6 is a diagram showing the relationship between the Hamming correction circuit and the bus, and Figure 7 is a diagram showing the relationship between the Hamming correction circuit and the bus. FIG. 8 is a time chart showing that data is not loaded on the bus, and FIG. 8 is a time chart showing a case where new data is loaded on the bus due to an abnormal humming check result. 1~4...IOP1~4, 5~6...CPU5~
6, 10...IOP bus, 11...CPU bus, 22
...Register, 23...Data register, 40...
...Reception circuit, 41...Reception circuit.

Claims (1)

[Scope of Claims] 1. In a multiprocessor system in which a first processor and a main memory are connected by a first bus, and a second processor and the main memory are connected by a second bus, The main memory device includes input means for selectively inputting information on each bus, and a service provided corresponding to the bus to receive main memory access requests from processors connected to the buses and perform reception processing for each. Each service circuit includes information unique to the bus, and each service circuit performs reception processing in response to an access request from a processor connected to the corresponding bus, so that information can be input from each bus to the input means in a common phase. A memory control method characterized in that control is performed by different timings according to transmission delay. 2. The first and second buses are buses that commonly connect other processors in addition to the first and first processors, and the service circuit inputs access requests from the processors connected to the corresponding buses. 2. The memory control system according to claim 1, wherein the memory control system is a circuit that performs reception processing. 3. The service circuit is controlled by a timing cycle having a different reception start time for each of the access requests, and a reception priority order for the access requests is provided between the service circuits. 1
Memory control method described in section. 4. The service circuit controls information transfer between each of the processors and the main memory using a common timing cycle for all buses in accordance with the memory cycle of the main memory. The memory control method described in scope 1. 5. When reading information from the main memory, the service circuit sets the timing so that information before Hamming correction is loaded on at least one of the buses, and information after Hamming correction is loaded on the buses of other series. 2. The memory control system according to claim 1, wherein information transfer from each of said processors to said main memory is controlled using a timing cycle common to all buses.