JP2713204B2 - Information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system including a data transfer device for connecting a system bus and an input / output bus which are separately installed.

[0002]

2. Description of the Related Art Conventionally, in this type of technology, only one kind of data line is connected between a system-side data transfer device connected to a system bus and an input-output data transfer device connected to an input / output bus. It is not provided and only one type of transfer is allowed at a time. Therefore, for example, when data is transferred from a system to a certain input / output control device, direct memory access transfer (hereinafter, referred to as “memory transfer”) between any one of the input / output control devices and a storage device without passing through a processing device. , "DMA transfer") must be confirmed and arbitrated.

The transfer between the input / output side and the system side is roughly classified into an input / output transaction (hereinafter, referred to as "IO transaction") and a direct memory access transaction (hereinafter, referred to as "DMA transaction"). Here, an IO transaction refers to setting an initial value of a transfer address or the like in a certain register of an input / output control device or reading a value of a certain register in accordance with an input / output command from a processing device, or a DMA transfer to the input / output control device. This refers to a series of processes for instructing activation of transfer. The DMA transaction refers to a series of processes related to DMA transfer in which data is directly transferred between the input / output control device and the storage device without using a processing device. Generally DM
The A transaction takes a long time because it deals with a large amount of data, and the IO transaction takes less time than the DMA transaction. And D
Since the MA transfer is performed as a unit until the transfer is completed, another transfer cannot be interrupted. Therefore, once D
Once the MA transfer has started, the other transfers are DMA
You have to wait for the transfer to finish.

Referring to FIG. 10, when an IO transaction is issued from the system-side data transfer device 100, an IO_BUSY signal (negative logic) indicating input / output busy is issued.
Is asserted, and the IO transaction reaches the I / O-side data transfer device 200 with a delay of two cycles. In addition,
Here, it is assumed that transfer between the system-side data transfer device 100 and the input / output-side data transfer device 200 requires two cycles. Also, the system-side data transfer device 1
DMA_00 representing the direct memory access request on the input / output side at the same time when the IO transaction is issued at 00.
When the REQ signal (negative logic) is asserted and a DMA transaction is requested from the input / output data transfer device 200, this request reaches the system data transfer device 100 with a delay of two cycles. On the other hand, the system-side data transfer device 100 waits for the end of the IO transaction, and
The A_ACK signal (negative logic) is asserted to inform the I / O-side data transfer device 200 that the DMA transfer will be accepted. The DMA_ACK signal arrives at the input / output data transfer device 200 with a delay of two cycles, and one cycle later, the input / output data transfer device 200 starts a DMA transaction.

[0007] Immediately after the IO transaction, the next IO is executed in the system-side data transfer device 100.
If you try to issue a transaction,
Cannot be issued because it is used for MA transfer. After all DM
After waiting for the last data of transaction A to arrive at system-side data transfer device 100, the next IO
You will start a transaction.

[0006]

In the above-mentioned prior art,
Since the IO transaction and the DMA transaction use the same path, the performance of the information processing system as a whole deteriorates due to the overhead of arbitrating each other and waiting for the IO transaction due to the long-time occupation of the DMA transfer path. The problem arises.

In particular, when the system bus side and the input / output side are installed at a certain distance from each other, a plurality of cycles may be required for the transfer between the data transfer devices. Arbitration for each transfer has a significant effect on performance. For example, as shown in FIG. 10, in the case where a DMA transaction is interposed even if a request to continuously issue an IO transaction is made, in addition to the time required for the DMA transaction, the time between the two data transfer devices is increased. The time required for migration is wasted. Also, the number of paths between the two data transfer devices cannot be increased without limitation from the viewpoint of mounting.

An object of the present invention is to eliminate the need for arbitration between an IO transaction and a DMA transaction in transfer between data transfer devices, and to eliminate the overhead caused by this arbitration.

Another object of the present invention is to eliminate unnecessary wait time between an IO transaction and a DMA transaction to improve transfer efficiency.

It is another object of the present invention to improve the transfer efficiency so as not to increase the number of paths between the two data transfer devices as much as possible.

[0011]

In order to solve the above-mentioned problems, an information processing system according to the present invention comprises a data transfer device on a system bus for connecting a processing device or a storage device, and an input / output device for connecting an input / output control device. A data transfer device on the bus side, and the processing device between the input / output control device and the storage device between the data transfer device on the system bus side and the data transfer device on the input / output bus side. Direct memory access, which is a series of processes that perform transfer without intervention
A transfer path for a transaction, and a transfer path for an input / output transaction which is a series of processing between the processing device and the input / output control device other than the direct memory access transaction. .

Further, another information processing system of the present invention comprises:
A data transfer device on the system bus connecting the processing device and the storage device; and a data transfer device on the input / output bus connecting the input / output control device, wherein the data transfer device on the system bus includes the input / output control device. The system bus includes a direct memory access transaction, which is a series of processes for transferring data between the device and the storage device without passing through the processing device, and an input / output transaction other than the direct memory access transaction. A first I / O transaction transfer unit for transferring the I / O transaction, and a first direct transfer unit for transferring the direct memory access transaction.
Input / output interface means for separating data from the input / output bus into the direct memory access transaction and the input / output transaction And second input / output transaction transfer means for transferring the input / output transaction; and second direct memory access transaction transfer means for transferring the direct memory access transaction. A transfer path for an input / output transaction provided between the input / output transaction transfer means and the second input / output transaction transfer means, the first direct memory access transaction transfer means and the second direct Direct memory provided between the memory access transactions transfer means,
And a transfer path for an access transaction.

In another information processing system according to the present invention, the first input / output transaction transfer means includes:
A first division unit that divides the data relating to the input / output transaction when outputting the data to a transfer path for the input / output transaction; Second dividing means for dividing the data when the data is output to a transfer path, and first assembling means for restoring the data divided by the second dividing means. And the second input / output transaction transfer means includes second assembling means for restoring the data divided by the first dividing means.

Further, in another information processing system according to the present invention, the first direct memory access transaction transfer means transfers data relating to the direct memory access transaction to the direct memory access transaction. Division means for dividing when outputting to a transfer path for
The second direct memory access transaction transfer means transfers reply data to the direct
Fourth dividing means for dividing when outputting to a transfer path for a memory access transaction, and further, the first direct memory access transaction transferring means is divided into the fourth dividing means. Third assembling means for restoring data, and the second direct memory access transaction transfer means further includes fourth assembling means for restoring the data divided by the third dividing means. Contains.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the data transfer apparatus of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, an information processing system according to an embodiment of the present invention includes a processing device 40 for processing data.
0 and a plurality of storage devices 500 for storing data, respectively.
0, an input / output bus 600 for connecting a plurality of input / output control devices 700,
An input / output data transfer device 200 connected to the input / output bus 600 is included. The input / output control device 700 includes:
Further, an input / output device (not shown) is provided under the control unit.

An IO transaction transfer line 2 for transferring an IO transaction is provided between the system-side data transfer device 100 and the input / output-side data transfer device 200.
0 and DM for transferring DMA transactions
They are connected by an A transaction transfer line 30. That is, a path for transferring an IO transaction and a path for transferring a DMA transaction are physically separate paths.

Referring to FIG. 2, a system-side data transfer device 100 includes a system interface circuit 110 which is an interface with a system bus 300, an IO transaction transfer circuit 120 which is responsible for transferring IO transactions, and a DMA transaction transfer. And a DMA transaction transfer circuit 130 in charge. The system interface circuit 110 separates a transfer from the system bus 300 into an IO transaction and a DMA transaction, or transfers a transaction from the IO transaction transfer circuit 120 or the DMA transaction transfer circuit 130 to the system bus 300. The IO transaction transfer circuit 120 receives an IO transaction from the system interface circuit 110, and receives the IO transaction from the input / output data transfer device 2.
Transfer this to 00. Similarly, the DMA transaction transfer circuit 130 also operates in the system interface circuit 1
10, the DMA transaction is received and transferred to the input / output side data transfer device 200.

The input / output data transfer device 200 includes a system interface circuit 210 as an interface with the input / output bus 600, an IO transaction transfer circuit 220 for transferring IO transactions, and a DMA.
And a DMA transaction transfer circuit 230 which is in charge of transferring the transaction. These input / output interface circuit 210, IO transaction transfer circuit 220 and DMA transaction transfer circuit 2
30 has the same function as that of the system-side data transfer device 100.

Referring to FIG. 3, in the information processing system according to the first embodiment of the present invention, the IO transaction transfer circuit 120 in the system-side data transfer device 100
An IO transaction transmission buffer 121 for temporarily holding an IO transaction from the system interface circuit 110; an IO transaction transfer control circuit 123 for performing read control on the IO transaction transmission buffer 121;
A reply data receiving buffer 124 for temporarily holding reply data from 00 and a buffer monitoring circuit 126 for monitoring that the reply data receiving buffer 124 is about to overflow.

On the other hand, an IO transaction transfer circuit 220 in the input / output data transfer device 200 is provided with an IO transaction reception buffer 221 for temporarily holding an IO transaction from the system data transfer device 100.
And a buffer monitoring circuit 223 that monitors that the IO transaction reception buffer 221 is about to overflow.
And a reply data transmission buffer 2 for temporarily holding reply data from the input / output interface circuit 210.
And a reply data transfer control circuit 226 for performing read control on the reply data transmission buffer 224.
And

The buffer monitoring circuit 223 monitors the remaining amount of the IO transaction reception buffer 221 and, when detecting that it is about to overflow, notifies the IO transaction transfer control circuit 123 of the fact. This allows I
Reading from the O transaction transmission buffer 121 is temporarily suspended. Similarly, the buffer monitoring circuit 126
Monitors the reply data receiving buffer 124 and, when detecting that it is about to overflow, notifies the reply data transfer control circuit 226 of the fact. As a result, reading from the reply data transmission buffer 224 is temporarily interrupted.

When an IO transaction involving reply data is transferred from the system-side data transfer device 100 to the input / output-side data transfer device 200, the subsequent IO transaction waits in the system-side data transfer device 100. On 20,
No conflicts occur between transfers in different directions.

Referring to FIG. 4, the DMA transaction transfer circuit 130 in the system-side data transfer device 100
The relationship between the IO transaction transfer circuit 120 in the system side data transfer device 100 and the IO transaction in the input / output side data transfer device 200 in FIG.
This is the same as the relationship of the transaction transfer circuit 220.
However, since a large amount of data is handled in the DMA transaction, the buffers 131, 134, 231 and 2
Reference numeral 34 denotes buffers 121, 124, 221 and 2 in FIG.
A larger capacity than 24 should be prepared.

Next, the operation of the information processing system according to the first embodiment of the present invention will be described.

Referring to FIG. 5, in the first cycle, an IO transaction is executed by the system-side data transfer device 10.
Starting from 0, IO_ represents IO_BUSY at the same time.
The BUSY signal (negative logic) is asserted and continues to be asserted until the third cycle. This IO transaction is delayed by two cycles, that is, during the three cycles from the third cycle to the fifth cycle, the I / O-side data transfer device 200
To reach.

In the I / O-side data transfer device 200, a DMA transaction is started in the first cycle, and transfer is continued for six cycles up to the sixth cycle. This DMA transaction arrives at the system-side data transfer device 100 with a delay of two cycles, that is, six cycles from the third cycle to the eighth cycle.

As can be seen from this example, the IO transaction and the DMA transaction are executed while overlapping in time. In addition, since transfer path arbitration is not performed, unnecessary waiting between transactions that has occurred in FIG. 10 does not occur here.

As described above, according to the information processing system of the first embodiment of the present invention, the IO transaction transfer line 20 and the DMA transaction are connected between the system side data transfer device 100 and the input / output side data transfer device 200. By providing the transfer line 30 independently, the transfer by the IO transaction and the transfer by the DMA transaction can be performed at the same time, and the arbitration between the IO transaction and the DMA transaction becomes unnecessary.

Next, a description will be given of a second embodiment of the information processing system according to the present invention.

Referring to FIG. 6, the information processing system according to the second embodiment of the present invention differs from the first embodiment in that an IO transaction division circuit 122 is provided at the output of an IO transaction transmission buffer 121, Reply data assembling circuit 125 at output of buffer 124
And an IO transaction assembling circuit 222 at the output of the IO transaction receiving buffer 221, and a reply data dividing circuit 225 at the output of the reply data transmitting buffer 224. The IO transaction division circuit 122 divides the data held in the IO transaction transmission buffer 121 into a plurality of smaller data. Further, the IO transaction assembling circuit 222 assembles the divided data held in the IO transaction reception buffer 221 into data of the original size. Reply data division circuit 225
The reply data assembling circuit 125 operates in a similar manner.

Referring to FIG. 8, data before division held in the IO transaction transmission buffer 121 includes a 32-bit width address and a 32-bit width data,
It includes a 1-bit type field that specifies write processing or read processing and a 3-bit size field that indicates the size of data. The reply data transmission buffer 131 holds the 36-bit width as one word,
The data is read out to the data division circuit 312 by using this as a unit.

On the other hand, referring to FIG. 9, at the output of the IO transaction dividing circuit 122, the address and the data are each divided into 16 bits. This is IO
This is because the bit width of the transaction transfer line 20 is set to 16 bits, and the divided 16-bit words are transferred in order from the upper word. The first transmitted word contains a 1-bit type field and 3
In addition to the bit size field, the upper 12 bits of the address are included. This is because the upper part of the address is necessary to determine the destination of the transfer.

Here, I from the system bus 300 side
Although the O transaction has been described, reply data from the input / output bus side is similarly processed by the reply data dividing circuit 225 and the reply data assembling circuit 125.

As described above, according to the information processing system of the second embodiment of the present invention, the IO transaction transfer circuit 120 is provided with the IO transaction division circuit 122 and the reply data assembling circuit 125, and the IO transaction transfer circuit 220 By providing the IO transaction assembling circuit 222 and the reply data dividing circuit 225 therein, the path width of the IO transaction transfer line 20 can be reduced.

Next, a description will be given of a third embodiment of the information processing system according to the present invention.

Referring to FIG. 7, the information processing system according to the third embodiment of the present invention is different from the first embodiment in that a reply data dividing circuit 132 is provided at the output of a reply data transmission buffer 131 and a DMA transaction reception circuit is provided. DMA transaction assembling circuit 13 is provided at the output of buffer 134
5, the data assembling circuit 232 at the output of the reply data receiving buffer 231 and the DMA transaction dividing circuit 235 at the output of the DMA transaction transmitting buffer 234. These division circuits and assembly circuits have the same functions as those of the IO transaction transfer circuits 120 and 220 of the second embodiment in FIG. That is, the reply data dividing circuit 132
The data held in the reply data transmission buffer 131 is divided into a plurality of data having a smaller size. The data assembling circuit 232 assembles the divided data held in the reply data receiving buffer 231 into data of the original size. DMA transaction division circuit 235 and DMA transaction assembly circuit 135
Works similarly.

The manner of dividing the DMA data is also shown in FIGS.
Is the same as the case of the IO transaction described above.

As described above, according to the information processing system according to the third embodiment of the present invention, the reply data division circuit 132 and the DMA transaction assembling circuit 135 are provided in the DMA
Data assembling circuit 2 in transaction transfer circuit 230
By providing the DMA transaction transfer circuit 30 and the DMA transaction dividing circuit 235, the path width of the DMA transaction transfer line 30 can be reduced.

[0040]

As is apparent from the above description, according to the present invention, the transfer path between the data transfer device on the system side and the data transfer device on the input / output side is set to be the same as that for the IO transaction.
By operating independently for the MA transaction, arbitration between the IO transaction and the DMA transaction becomes unnecessary, and
The transfer by the O transaction and the transfer by the DMA transaction can be performed simultaneously. In addition, by dividing data at the time of transfer, the transfer path width can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one configuration of an information processing system of the present invention.

FIG. 2 is a block diagram showing one configuration of a data transfer device according to the present invention.

FIG. 3 is a block diagram showing an IO transaction transfer circuit according to the first embodiment of the present invention.

FIG. 4 shows DM in the first and second embodiments of the present invention.
FIG. 3 is a block diagram illustrating an A transaction transfer circuit.

FIG. 5 is a diagram showing a time chart in the first embodiment of the data transfer device of the present invention.

FIG. 6 shows IOs according to the second and third embodiments of the present invention.
FIG. 3 is a block diagram illustrating a transaction transfer circuit.

FIG. 7 is a block diagram showing a DMA transaction transfer circuit according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a format of transfer contents according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a format of transfer contents in the second and third embodiments of the present invention.

FIG. 10 is a diagram showing a time chart in a conventional data transfer device.

[Explanation of symbols]

 Reference Signs List 20 IO transaction transfer line 30 DMA transaction transfer line 100 System side data transfer device 110 System interface circuit 120 IO transaction transfer circuit 121 IO transaction transmission buffer 122 IO transaction division circuit 123 IO transaction transfer control circuit 124 Reply data reception buffer 125 Reply data assembly Circuit 126 Buffer monitoring circuit 130 DMA transaction transfer circuit 131 Reply data transmission buffer 132 Reply data division circuit 133 Reply data transfer control circuit 134 DMA transaction reception buffer 135 DMA transaction assembling circuit 136 Buffer monitoring circuit 200 Input / output side data transfer device 210 Input / output Interface circuit 220 IO transaction transfer circuit 221 IO transaction reception buffer 222 IO transaction assembly circuit 223 buffer monitoring circuit 224 reply data transmission buffer 225 reply data division circuit 226 reply data transfer control circuit 230 DMA transaction transfer circuit 231 reply data reception buffer 232 reply data assembly circuit 233 Buffer monitoring circuit 234 DMA transaction transmission buffer 235 DMA transaction division circuit 236 DMA transaction transfer control circuit 300 System bus 400 Processing device 500 Storage device 600 Input / output bus 700 Input / output control device

Claims (3)

(57) [Claims] 1. An information processing system comprising: a data transfer device on a system bus for connecting a processing device or a storage device; and a data transfer device on an input / output bus for connecting an input / output control device. The data transfer device includes a direct memory access transaction, which is a series of processes for transferring data between the input / output control device and the storage device without passing through the processing device, and a process other than the direct memory access transaction. System interface means for dividing the data from the system bus into an I / O transaction, first I / O transaction transfer means for transferring the I / O transaction, and first I / O transaction transfer means for transferring the direct memory access transaction Direct memory access transaction And an input / output interface unit for dividing the data from the input / output bus into the direct memory access transaction and the input / output transaction. A second input / output transaction transfer unit for transferring a write / output transaction, and a second direct memory access transaction transfer unit for transferring the direct memory access transaction, wherein the first input / output transaction Transfer means and said second
A transfer path for an input / output transaction provided between the input / output transaction transfer means and the first direct memory access transaction transfer means and the second direct memory access transaction transfer means And a transfer path for a direct memory access transaction provided between the information processing system. 2. The first input / output transaction transfer unit includes a first division unit that divides data relating to the input / output transaction when outputting the data to a transfer path for the input / output transaction. Second input / output transaction transfer means for splitting the reply data when outputting the reply data to a transfer path for the input / output transaction, further comprising:
A first method for restoring the data divided by the second dividing means;
Assembling means, and the second input / output transaction transfer means further comprises:
A second method for restoring the data divided by the first dividing means;
The information processing system according to claim 1, characterized in that it comprises a and assembly means. 3. The direct memory access transaction transfer means, when outputting data relating to the direct memory access transaction to a transfer path for the direct memory access transaction. The second direct memory access transaction transfer means, wherein the second direct memory access transaction transfer means
A fourth dividing unit that divides the data when outputting to a transfer path for a memory access transaction; and the first direct memory access transaction transferring unit is divided into the fourth dividing unit. Third assembling means for restoring data; and the second direct memory access transaction transfer means further comprising fourth assembling means for restoring the data divided by the third dividing means. the information processing system according to claim 1, comprising.