JPH02171949A - Dma transfer system - Google Patents

Abstract

PURPOSE:To increase a data transfer speed by simultaneously applying lower address data to both memories in the case of data transfer between the memories using the lower address data in common and directly transferring the data through a data bus. CONSTITUTION:The transferring memory 1 is directly connected to the transferred memory 2 through a data bus 3 and an address bus 4. Low-order address data A0 to A12 out of an address signal (e) from a DMA controller (DMC) 5 are simultaneously applied to both the memories 1, 2 through the address bus 4 and data (f) from the memory 1 are directly transferred to the memory 2 through the data bus 3. Since the data can be directly transferred between both the memories without passing them through a temporary register or the like, data transfer between the memories having the low-order address data in common can be rapidly executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system for directly transferring data between memories that share lower address data.

[Conventional technology]

If it is difficult to transfer data between memories using DMA, a register called a temporary register is provided in the middle, data is accumulated from the transfer source memory in this register, and then data is stored from the register to the transfer destination memory. ing.

[Problem to be solved by the invention]

However, since data is transferred via intermediate registers, the time required to transfer data through the registers is approximately twice as long as the time required to directly transfer data between memories, resulting in a reduction in data transfer response speed. It is occurring.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is constructed by the following means.

In other words, in data transfer between memories that share lower address data in common, the source memory and the destination memory are directly connected via a data bus and address bus, and the DMA acknowledge signal of the DMA controller is sent to the destination memory. and I/O/O write signals are given as chip select signals and write signals, and the transfer source memory is
It decodes the upper address data of the MA controller and gives it as a chip select signal, gives a memory read signal, and gives the lower address data to both memories simultaneously via the data bus, and simultaneously transfers the data via the data bus. We intend to do so.

[Effect]

Therefore, the transfer source memory is in the read state and the transfer destination memory is in the write state, and the lower addresses of both memories are simultaneously designated as the same address, and data transfer via the data bus causes the lower data of both memories to be the same. This is done directly between addresses.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram, FIG. 2 is a timing chart showing the signals of each part in FIG. 1, and FIG. 3 is a diagram showing the address setting status of the memory. and the transfer destination memory 2 are directly connected via a data bus 3 and an address bus 4, while a DMA controller (hereinafter referred to as DMC) 5 and a selector (hereinafter referred to as 5EL)
6.7 and a decoder (hereinafter referred to as OGC) 8 are provided, and 5EL6 and 7 are provided with a bus hold acknowledge signal (hereinafter referred to as HLDAK) (a) from a central processing unit (hereinafter referred to as CPU) not shown in the figure. It is believed that the system will respond and perform a switching operation.

In addition, the addresses of memories 1 and 2 are set at υ as shown in FIG.
The addresses of memory 2 are determined as r8000HJ to [9FFFHJ, and the lower address data AO-A12 of both memories 1.2 is common.

At this point, when HLDAK(a) from the CPU is given, DMC5 starts operating and 5F2L6.
7 responds and provides the DMA acknowledge signal (hereinafter referred to as DMAAK) sent by the DMC 5 as a chip select signal for the memory 2, and also provides the 1/O write signal (hereinafter referred to as Ilo/WR) (d) as a write signal. as memory 2
On the other hand, a memory read signal (hereinafter referred to as MRD) (C) from DMC5 is given to memory 1, and
Upper address data A13 to A15 in the address signal (e) sent by the MC5 are decoded by the DEC8,
Since it is given as a chip select signal for memory 1,
As a result, memory 1 becomes a read state and memory 2 becomes a write state.

In addition, among the address signal (e) from the DMC 5, the lower address data AO to A12 are simultaneously given to the memories 1 and 2 via the address bus 4, so the address signal (e
) is, for example, r /O0OHJ, then data (f) from address r /O0OHJ of memory 1 is directly transferred to address r9000HJ of memory 2 via data bus 3 .

Note that while HLDAK (a) is given, DMC5 receives DMAAK (b), MRD (c), rlo
-WR(a) is generated sequentially and disappears in the opposite order, and data (f) is transmitted for a slightly longer period than Ilo・wR(d), thereby ensuring reliable data. transfer is performed.

After HLDAK(a) disappears, 5EL6.7 becomes DEC8
In order to select the output of and the memory write signal MWR from the CPU and apply them to the memory 2, if the CPU specifies the address r9000HJ, the transferred data can be read from the memory 2.

〔Effect of the invention〕

From the above explanation, it is clear that according to the present invention, DM
A controller DMA acknowledge signal and I/O
/O write signal puts the transfer destination memory in writing state, and D
MA controller upper address data and memory
The read signal puts the transfer source memory in the read state,
In this method, lower address data is given to both memories at the same time, and the data is transferred directly via the data bus.In particular, there is no intervention such as a temporary register, and the data is transferred directly between the two memories. Since the data transfer speed is high, a remarkable effect can be obtained in data transfer between common memories of lower address data.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention; FIG. 1 is a block diagram, FIG. 2 is a timing chart showing signals of each part in FIG. 1, and FIG. 3 is a diagram showing a memory address setting situation. 1.2-・118 memory, 3...-data bus, 4@
--Address bus, 5 --DMA controller,
6, 7...-selector, 8, Il... decoder, (b
)...DMA acknowledge signal, (c)...memory read signal, (d)...I/O write signal,
(e) Address signal, (f) eφφ data.

Claims (1)

[Claims] In data transfer between memories that share lower address data in common, the source memory and the destination memory are directly connected via a data bus and address bus, and the DMA acknowledge signal and the DMA controller's DMA acknowledge signal are sent to the destination memory. An I/O write signal is given as a chip select signal and a write signal, and the transfer source memory receives the D
Decoding the upper address data of the MA controller and giving it as a chip select signal as well as giving a memory read signal, and simultaneously giving the lower address data to both of the memories via the data bus, and transferring the data via the data bus. DM characterized by directly conducting
A transfer method.