JPH01207847A - Inter-memory data transfer system - Google Patents

Abstract

PURPOSE:To attain an inter-memory data transfer with only the use of one DMAC by providing in either memory an address variable type matching circuit to function as an input and output register from the DMAC side. CONSTITUTION:When the data of a memory 1 are transferred to a memory 2, the control right of the respective buses of an address read/write control is passed by a DMAC 4, an empty bus is utilized and the data transfer is executed by an address signal and a control signal which the DMAC 4 generates. A write address to the memory 2 is changed and simultaneously a shake band processing to exchange a request signal TxRQ and a strobe signal TxAK with the DMAC 4 is executed. Further, the read/write control of the memory 2 is executed by converting a signal from the DMAC 4.

Description

[Detailed Description of the Invention] [Table of Contents Overview Industrial Application Fields Prior Art (Fig. 5) Means for Solving the Problems to be Solved by the Invention (Fig. 1) Effect (Fig. 1) ) Embodiment (Figures 2 to 4) Effects of the invention [Summary] Direct memory access controller (Direct
Memory Access Controller
Regarding the inter-memory data transfer method that transfers data between memories using a DMAC (hereinafter referred to as DMAC), by adding a matching circuit to the memory, it is possible to transfer data between memories just by using one DMAC. For this purpose, one of the memories is configured to include a variable address matching circuit that functions as an input/output register from the DMAC side.

[Industrial Field of Application] The present invention relates to an inter-memory data transfer method that uses DMAC to transfer data between memories.

In recent years, there has been a technology called direct memory access (DMA) that directly transfers data between memories via a CPU (central processor unit) or MPU (microprocessor unit). When transferring data between memories via the CPU, this technology requires a two-step process of first reading the data into the CPU and then writing that data to the transfer destination memory, so it is particularly difficult to transfer large amounts of data. This technology solves the inconvenience that when attempting to transfer all data at once, it takes a long time to transfer, and the CPU becomes busy for the transfer process.

And in order to implement such DMA, the address,
Control of each bus for read/write control is handed over to the CPU, and data is transferred using the vacant buses in response to address signals and control commands generated by the DMAC.

[Prior Art] FIG. 5 is a block diagram conceptually showing a conventional inter-memory data transfer method.
is a memory (RAM), and 33.34 is a DMAC 135 is an intermediate register, for example, from memory 31 to memory 32.
When data is transferred to the memory 32, the data from the memory 31 is first input to the DMAC 33, and then the data is input from this DMAC 33 to another DMAC 34 via the intermediate register 35, and then further transferred to the memory 32.

[Problems to be Solved by the Invention] However, in such a conventional memory-to-memory data transfer method, two actions are required for memory transfer, and two
Since two DMAs are required, there are problems in that the scale becomes large and the data transfer performance is low.

Therefore, there is a request to transfer data between memories using one DMAC, but since the basic processing between registers and memory cannot change the memory address of one side, Data transfer between them is not possible.

The present invention has been made in view of these problems, and includes the addition of a memory register matching circuit [thereby, one DM
The purpose of this invention is to provide an inter-memory data transfer method that enables data transfer between memories simply by using AC.

[Means to solve the problem] FIG. 1 is a block diagram showing the basic configuration of the present invention.

In Figure 1, 1 and 2 are memories, 3 is an MPU, and 4 is a D
MACl3 is a matching circuit, 6 is a clock pulse generator, and memory 1. MPU3. DMAC4 and matching circuit 5 are interconnected via address bus AD, data bus DATA, and control bus CNT. moreover,
A shakehand processing line exists between the DMAC 4 and the matching circuit 5. Note that the clock pulse generator 6 is connected to the control bus CNT, and
MPU3 clock φ1. φ2 is supplied.

Further, the MPU 3 and the DMAC 4 are connected via a signal line for exchanging signals for permission to use the bus, and the matching circuit 5 and the memory 2 are connected to an address line, a data line, and a read/write control line. connected via.

By the way, the matching circuit 5 is configured as a variable address type circuit that functions as an input/output register from the DMAC 4 side. Therefore, this matching circuit 5 writes address A to the memory 2. A request signal T x R is sent between the address change unit 7 that changes ~Ax and the DMAC 4.
It is comprised of a shake hunt processing unit 8 that exchanges Q and a strobe signal TxAK corresponding thereto, and a read/write control unit 9 that converts signals from the DMAC 4 and performs read/write control of the memory 2. .

Note that this matching circuit 5 transfers data D. - A data transmitting/receiving section 10 that receives Dx and sends it to the memory 2 side is also provided.

[Function] With such a configuration, when data in memory 1 is transferred to memory 2 using DMAC 4, for example, DMAC
4, the MPU 3 is given control of each bus for address and read/write 1, and data is transferred using the address and control signals generated by the DMAC 4 using the vacant lot. The matching circuit 5 changes the write address to the memory 2, performs shakehand processing to exchange the request signal TxRQ and the corresponding strobe signal TxAK with the DMAC 4, and further converts the signal from the DMAC 4. Performs read/write control of memory 2. This allows the DMAC 4 to view memory 2 as an input/output register while changing the address, and as a result, it becomes possible to transfer data between memories in the same way as data transfer between normal input/output register memo 9. .

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of the matching circuit 5 which is the main part of the present invention. A matching circuit 5 is added to the memory 2 and the DMAC
From the 4th side, it is configured as a variable address type circuit that functions as an input/output register. This matching circuit 5 includes an address changing section 7. Data driver/receiver 1
0. It is configured to include a control section 11.

Here, the address changing unit 7 changes the write address to the memory 2, and the address changing unit 7 changes the write address to the memory 2. Transfer start address register 13. Address decoder 14.
An address generator 15 is provided, and this address change unit 7 receives MPU bus addresses A0 to Ax by its address receiver 12 and transfers these address information to a start address register 13 and an address decoder 1.
Furthermore, information from the transfer start address register 13 receiving the signal from the data driver/receiver 10 and decoded address information from the address decoder 14 are sent to the address generator 15. Then, this address generator 15 generates a memory address A Mo - A M x and a memory select C5M based on the information from the transfer start address register 13 and the address decoder 14.

=8- The data driver/receiver 10 transfers data D o-
It performs data buffer processing to receive Dx and send it to the memory 2 side as DMo-DMx, but also sends data information to the transfer start address register 13.

The control unit 11 sends a request signal Tx to the DMAC 4.
It has the functions of both a shake hand processing section that exchanges RQ and a corresponding strobe signal TxAK, and a read/write control section that converts signals from the DMAC 4 and performs read/write control of the memory 2.

To explain the case where data is transferred from memory 1 to memory 2 using the above-described configuration, first, the following preprocessing is performed in MPU 3. That is, (1) DM with MPU3
The transfer memory start address and number of bytes are set in AC4.

(2) The MPU 3 writes the start address to the matching circuit 5 from Sera1.

(3) Instruct DMAC4 to start.

After the pretreatment is completed, the next treatment is performed.

(4) The DMAC 4 receives a transfer request (TxR) from the matching circuit 5.
In Q), the MPU 3 is notified of the start of transfer. As a result, D
MAC4 gains bus control.

(5) DMAC4 issues an address and a control signal,
At the same time as reading data from the memory 1, a strobe (TxAK) is sent to the matching circuit 5 to notify the matching circuit 5 of data transfer.

(6) Matching circuit 5 writes data to memory 3 side.

Then, if data is to be transferred from memory 1 to memory 2 continuously, the process from item (4) above is repeated.

In this way, the DMAC 4 allows memory 2 to be viewed as an input/output register while also changing the address, making it possible to transfer data between memories in the same way as normal data transfer between input/output registers and memories. It is.

In addition, the hardware scale required for inter-memory data transfer by the DMAC 4 can be reduced, and memory transfer can be performed in one cycle, which greatly contributes to improving data transfer performance.

A specific example of the configuration of the matching circuit 5 can be realized by the configuration shown in FIG. This matching circuit 5 first separates the memory 2 and the MPU bus, and furthermore, in order to open the data bus when the memory 2 is selected, the bus driver/receiver 1
6, 17.18.

The bus driver/receiver 16 receives address information A at the timing shown in FIG. 4(e). - It receives Ax and sends it to the address register/address decoder 19 and memory address decoder 20, and the bus driver/receiver 17 receives data information. -After receiving Dx, this is the 4th
It is sent to the memory 2 side as D M o - D M x and also sent to the upper address register 21 at the timing shown in FIG.

The bus driver/receiver 18 has a tarlock φ2 [see FIG. 4(,)] and a strobe signal TxAK [see FIG. 4(d)].
)], the read/write control signal R/W [see Figure 4 (e) = 11- for the output timing of this signal], and outputs the request signal TXRQ [see Figure 4 (c)]. It is something. Here, the bus driver/receiver 18 has four clocks φ2 [Fig.
) reference], it is sent to the ]-/8 frequency divider 22. The 1/8 frequency divider 22 divides the clock by 178 [see FIG. 4(b)], and further divides the clock into a delay circuit 23.
After a short delay, the bus driver/receiver 18
The request signal TxRQ (see FIG. 4(c)) is outputted in accordance with the timing specified by the DMAC.

This makes it visible to the DMAC 4 as an input/output register.

In this way, the bus driver/receiver 18 is configured as shown in FIG.
When a request signal TxRQ as shown in c) is output, a strobe signal TxAK is returned from the DMAC 4 at a timing as shown in FIG. 4(d).

Also, at the timing shown in Fig. 4(e), read/write 1 to
When the control signal R/W is input to the bus driver/receiver 18, this signal is inverted by the inverter 24 and output to the memory 2 side. This is DMAC4
The read/write control signal R/W from the memory 2 connected to this matching circuit 5 is a signal sent to the normal memory side.
Since it requires the opposite operation to that of a normal memory, it is inverted by the inverter 24. The output timing of the read/write control signal R/W, which is inverted by the inverter 24, is as shown in FIG. 4(f).

Note that the read/write control signal R/W is also output to the upper address register 21 as a control signal, and the upper address register 21
outputs the upper address to the memory address decoder 20.

Then, the memory address decoder 20 decodes the address information from the bus driver/receiver 16 and the upper address register 21 for memory, and outputs AM, -
A Mx [This signal timing is as shown in FIG. 4(f)] is output to the memory 2 side, and a signal for chip select 1- of the memory 2 is output.

The chip select signal from the memory address decoder 20 is outputted to the memory 2 via the gate circuit 25 as a chip select word C3M. At this time, the strobe signal TxAK from the bus driver/receiver 18 is also input to the gate circuit 25. The output timing of this chip select signal C5H is shown in FIG. 4(g).

Note that the signal from the address register/address decoder 19 and the signal for chip selection from the memory address decoder 20 are input to a gate circuit 26, and the output from this gate circuit 26 is a control signal to the bus driver/receiver 17. used as.

In this way, address, data, DMAC/MPU
By adding the necessary processing to the control signal of the DM
While making it look like an input/output register from AC4,
Moreover, the address can be made variable, and data transfer between the memories 1 and 2 is possible by using just one DMAC 4 here and there.

Note that the present invention can be applied even when the types of MPU, DMAC, and memory are different. In this case, although the signal timing and the number of signal lines change, the basic processing method remains the same.

[Effects of the Invention] As detailed above, according to the memory-to-memory data transfer method of the present invention, in the memory-to-memory data transfer method in which data is transferred between memories using DMAC, one of the memories is With a simple configuration in which a variable address matching circuit that functions as an input/output register is provided from the DMAC side, there is an advantage that data transfer between memories is possible by using only one DMAC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram of a matching circuit showing an embodiment of the present invention, FIG. 3 is a specific configuration diagram of the matching circuit, and FIG. Timing chart 1 for the matching circuit in the figure. FIG. 5 is a block diagram showing a conventional example. In the figure, 1.2 is a memory, 3 is an MPU, 4 is a DMACl, 3 is a matching circuit, 6 is a clock pulse generator, 7 is an address change unit, 8 is a shake hand processing unit, 9 is a read/write control unit, and 10 is a Data transmission/reception unit, 1 is a control unit, 12 is an address receiver, 13 is a transfer start address register, 14 is an address decoder, 15 is an address generator, 16 to 18 are bus drivers/receivers, 19 is an address register/address decoder, 20 21 is a memory address decoder, 21 is an upper address register, 22 is a 1/8 frequency divider, 23 is a delay circuit, 24 is an inverter, and 25 and 26 are gate circuits.

Claims (2)

[Claims] (1) In an inter-memory data transfer method in which data is transferred between memories (1, 2) using a direct memory access controller (4), the direct memory access is performed on one of the memories (1, 2). An inter-memory data transfer system characterized in that a variable address matching circuit (5) functioning as an input/output register is provided from the controller (4) side. (2) The matching circuit (5) transmits a request signal and a corresponding strobe signal between the address change unit (7) that changes the write address to the one memory and the direct memory access controller (4). and a read/write control section (9) that converts signals from the direct memory access controller (4) to control read/write of the one memory. 2. The inter-memory data transfer system according to claim 1, wherein the inter-memory data transfer system is configured as follows.