JPS62241045A - Storage device - Google Patents

Abstract

PURPOSE:To double the width of data to be transferred and to increase the data transmitting speed by setting the data width of both a memory part and a read data register at a value twice as large the data width of an address bus and a data bus. CONSTITUTION:The data width of a memory part 10 is set at 32 bits when the data widths of memory parts 10A and 10B are set at 16 bits. In the same way, the data width of a read data register 30 is also set at 32 bits. Thus the data of 32-bit width is extracted out of the part 10 and transferred via the register 30 when a single read request is delivered. In this case, the a read data register 30B is connected to an address bus 5 with a read data register 30A connected to a data bus 6 respectively. Thus both buses 5 and 6 are used in common with each other in a read mode of the part 10. As a result, the width of the data to be transferred is redoubled and the data transmitting speed is increased.

Description

[Detailed description of the invention] [Industrial application field] This invention relates to storage devices, and more particularly.

It relates to a storage device whose address bus can also be used as a data bus.

[Conventional technology]

FIG. 3 is a block diagram showing a schematic configuration of a conventional storage device. In FIG. 3, C is a dynamic RAM group (memory unit) for storing required data, and is connected to What is there?

Address register (Jl) temporarily stores the memory address for data read/write; Read data register (Jl, Jl) temporarily stores the read data.
and a write data register (4111) that temporarily stores the data to be written, and an address register (Jl is connected to the corresponding address bus (y), and a read data register (31 and write data register The address bus (sl) and the data bus (61) are connected to a data bus (6). It is integrated into a memory path (not shown) that includes a control signal line for transmitting control signals.

Next, I will explain the operation.For example, the memory section (
Assume that a data read request for C is issued via a predetermined control signal line within the memory bus. At this time, the target address of the memory section (c) is set in the address register (c) via the address bus (S), and the contents stored at the address thus set are stored in the memory section (c). The data is read from the data register (3), set in the read data register (3), and then transmitted to the processor section (not shown) via the data bus (6).In such a case,
When the memory section (c), address register (c), read data register (3), write data register (ri1), address bus (j#) and data bus (61) are all 1, for example, /6 bit wide, As mentioned above, the data output to the data bus (6) is 76 bits wide.

[Problem that the invention seeks to solve]

Since conventional storage devices are configured as described above, the width of data successively output from the memory section (C) is fixed at 1, for example, 76 bits.

This invention solves the problem that the data 1 positive that is successively output in 7 read requests is limited to the above-mentioned /6 bits, and the data transmission speed decreases. By making the data width of the memory section and read data register twice the data width of the address bus and data bus, the data width of the data transferred in seven read requests can be reduced. The objective is to obtain a storage device with K that doubles and increases its data transmission speed.

[Means for solving problems]

A storage device according to the present invention includes a memory section, an address register connected to an address bus in which an address for accessing the memory section is set, and a data bus for reading and writing data to the memory section. It consists of a read data register and a write data register connected to each other, the data width of the memory section and the read data register is set to be twice the data width of the address bus and the data bus, and half S of the read data register is set to the address bus. bus, and its remaining half is connected to the data bus.

[For production]

According to the present invention, when data is successively output from a required address in the memory section and transmitted to the processor section, both the address bus and the data bus are shared for this purpose.

〔Example〕

? FIG. 1K is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention. In this Figure 1,
The memory section (10) is configured such that a #l memory section (10A') and a 4# co-memory section (10B') having a storage capacity of the same data width are arranged in parallel with each other. , and the read data register (3Q) is
#/read data registers (J) with the same data width
Ok) and #corret data registers (3oB) are arranged in parallel with each other. Then, write data register (IIl) and memory section (lO) #/
The memory sections (10A) are connected to each other by signal lines (//A)K.

# Top 9 parts (toB) are connected to each other by the signal line (//B), and the reference/memory part (IOA)
and #-/read data register (, 717A) are mutually connected, and #copy top 9 part (/DB') and 4# collet data register (JOB) are mutually connected.

Furthermore, the reference/read data register (JOk) and the data bus (61) are connected to each other by a signal line (3/A), and the #corret data register (JOB) and address bus (s) are connected to each other by a signal line (, 3/B).In addition, in this FIG.
Items with the same reference numerals as those in the book in the figure represent the same or equivalent actions. Now, refer to the memory section (IO
Assuming that the data widths of the A) and #-memory sections (ioB) are both /6 bits, the data width of the memory section (1
The data width of 0) becomes 3.2 bits, and similarly, the data width of read data register (3o) also becomes 32 bits. According to the above-mentioned embodiment, since seven read requests have been issued, three
2-bit wide data is taken out and set in the read data register (JO), and is transmitted to the processor section, etc. This point will be explained below with reference to the second cause. Figure 1 is a timing diagram for explaining the operation when a read request like the one described above is issued. be. Now, when a required 17-degree request (REQ) is issued from the processor section, etc., the target address of the memory section (/θ) is sent to the address register (rADR set in 1) via the address bus (!1). Next, a busy memory access is performed (AccESs), and the data (DATO) in #/memory section (/θA) K in the memory section (10) is
) is set in the #/read data register (3oA), and the data (DAT/
) is set in the '#URID data register (30B). and.

As a response rmsp) to the read request.

The former data (DATO) is transmitted via the data bus (6t).

Also, the latter data (DAT/') is transferred to the address bus (5
) as 32-bit wide data overall.

It is transmitted to the processor section, etc. As can be seen from the timing diagram in Figure 1, requests and responses to them occur at different times, and information of different nature, such as addresses and data for memory sections, is mixed. No inconvenience will occur.

In the above embodiment, the data width of the memory section is 3λ bits, but the data width is not limited to this, for example, the data width may be 6 dabits, and the data width of the address bus or data bus may be used. By appropriately selecting the method of assigning addresses to the memory section, the same effects as those of the above embodiments can be achieved. [Effects of the Invention] As explained above, the storage device according to the present invention an address register connected to an address bus in which an address for accessing the memory part is set; and a read data register and write data connected to a data bus for reading and writing data to the memory part. The data width of the memory section and read data register is twice the data width of the address bus and data bus.

Half of the read data register is connected to the address bus, and the remaining half is connected to the data bus, so that when data is read out from the memory section, both the address bus and the data bus are connected. Since the bus is shared for data transmission, both the address bus and data bus are used when transmitting data from the memory section to the processor, etc., and the data transmission speed increases accordingly. This effect can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention, and FIG. 2 is a timing diagram for explaining how the embodiment operates. FIG. 3 is a block diagram showing a schematic configuration of a conventional storage device. (1), (10) are memory parts, (10A), (10B
) is #ia'# co-memory part, (ri is address register, +31. (30) is read data register% (JOA'), (
30B) tie/, l read data register, (ulF
i write data register, (, r) Fi address bus,
(A) is the data bus %C11A)I(//B)l(3
1A) and (37B) are signal lines. In each figure, the same reference numerals indicate the same or corresponding parts. Leather 1 Figure 10A, 10B: 11, 12 Met'J Sop
2: 7 address L register 30: Read data register 30A, 30B: wl, w2'J-FT"-ELM register 51'4: Write data L!" register 5: 7 address register 6 : Data space Figure 2 7 Domestic space (5) Ward's name = text (6) ro [come ts 7 question ro = self ko 5 I =] Figure 3 1 ゛ Memo wholesale 2: 7V L?” Star 3: Read ↑゛-Ta L Lister 4: Write eater register 5゛ 7V

Claims (1)

[Claims] a memory section, an address register connected to an address bus in which an address for accessing the memory section is set, and a read data register and write connected to a data bus for reading and writing data to the memory section. a data register, wherein the data width of the memory section and the read data register is twice the data width of the address bus and the data bus, and half of the read data register is connected to the address bus; Further, the remaining half of the storage device is connected to the data bus, and both the address bus and the data bus are shared for data transmission when reading data from the memory section.