JPS6121542A - Data transfer device - Google Patents

Abstract

PURPOSE:To realize highly efficient data transfer by adopting the constitution that the 1st and 2nd memories and the two memories are accessed independently at the same time. CONSTITUTION:An address switch 9 is changed over to the position of a hard disc 11 by a command from a CPU7 and a DMA command is given to a DMA controller 8. The content from a hard disc 11 is written on the 1st memory 12 according to the command. In this case, the 2nd memory 13 is in the system connected to a data bus 14 and an address bus 15 and it is accessed freely from the system. When the transfer to the 1st memory 12 is finished, the CPU7 changes over an address switch 9 and a data switch 10, the 2nd memory 13 is arranged on the hard disc 11 and the 1st memory 12 is arranged on the system and while the data is transferred from the 1st memory 12 to the system, the content of the hard disc 11 is transferred to the 2nd memory 13. The transfer time is overlapped by repeating it to attain highly efficient data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a data transfer device used in a storage device of a computer or the like.

Conventional configuration and its problems FIG. 1 shows a conventional configuration. FIG. 2 shows a timing chart.

The conventional device shown in FIG.
Instead of switching to the hard disk 3 side, direct memory access (hereinafter abbreviated as DM, A) control, DM to row 24
Give instructions A. For example, in the case of reading from the hard disk 3, the contents from the hard disk 3 are written to the storage element 5 according to this instruction. When the writing is completed, the completion information is transmitted from the DMA controller 4 to the CPU 1, the CPU 1 switches the address switch 2 to the address bus 6 side, and the contents of the memory element 5 are transferred to other memories etc. via the data bus 7. be transferred.

However, when the memory element 6 is used in a time-division manner in this way, the system connected to the address bus 6 and the data bus 7 (
(not shown) side occurs, and also on the hard disk 3 side, when the storage element 5 is located on the system side, a time loss occurs, and the transfer efficiency is greatly reduced.

OBJECTS OF THE INVENTION The object of the present invention is to eliminate these time losses and realize highly efficient data transfer.

Structure of the Invention The present invention enables highly efficient data transfer by providing a first and second memory and having a structure in which the two memories can be accessed independently at the same time.

In the seventh embodiment, a CPU is connected to a control signal line to send control signals to a DMA controller 8, an address switch 9, and a data switch 10. Further, the DMA controller 8 and the address switch 9 are connected by an address data line,
Address data is sent from the DMA controller roller 8 to the address switch 9. Furthermore, the DMA controller 8 and -
- and the hard disk devices 11 are connected by address data lines.

The address switch 9 and the first and second memo IJ 12 , 13 are arranged so that the address switch 9 sends independent address data to the first storage element (hereinafter abbreviated as memory) and to the second memory 13, respectively. Independent address data lines are connected to each.

The data switch 10 is connected to a hard disk drive 11 and first and second memories 12 and 13 by data lines so as to be able to send and receive data, and is further connected to a data bus 14 by a data line.

The address bus) 5 is connected to an address switch 9 and an address data line.

Next, the operation of the present invention will be explained with reference to FIGS. 3 and 4. First, in response to an instruction from the CPU 7, the address switch 9
The bar switches to the disk 11 side and issues a DMA instruction to the DMA controller 8. For example, when reading data from the hard disk 11, the contents from the hard disk 11 are written to the first memory 12 according to this instruction.

At this time, the second memory 13 is located on the system (not shown) side connected to the data bus 14.degree. address bus 16, and can be freely accessed from the system side. When the transfer to the first memory 12 is completed, the CPU 7 switches the address switch 9. Switch the data switch 1゜, hard disk 11
Second memory 13 on the side, first memory 12 on the system side
is arranged, and while data is being transferred from the first memory 12 to the system side, the contents of the hard disk 11 are being transferred to the second memory 13. By repeating these steps, the transfer time is over-ramped and data is transferred with high efficiency. The same thing can also be said about writing data from the system side to the hard disk 11 via the first and second memories.

Effects of the Invention As described above, by having two memories, the efficiency of data transfer is greatly improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional example, Fig. 2 is a timing chart based on Fig. 1, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a timing chart based on Fig. 3. be. 7...Central processing unit, 8...Direct memory access controller, 9...Address switch, 10
...Data switch, 11...Hard disk,
12...First memory element, 13...Second memory element, 14...Delta bus, 15. Address bus.

Claims (1)

[Claims] The two storage elements are connected to the storage device via an address switcher and an address controller that separately switch the addresses of the respective storage elements, and the first and second storage elements are connected to the storage device. A data transfer device characterized in that a storage element is connected to a data bus via a data switch.