JPS62262170A - Data transfer system - Google Patents

Abstract

PURPOSE:To transfer data between memories in two processors with a simplified means, by providing a shared memory, and means which performs the read and the write of a specific value at the specific address of the shared memory, at each processor. CONSTITUTION:A memory 3 is provided in a microprocessor 1, and a memory 6 is provided in a micro processor 2. A shared memory 9 is switched and connected to the processor 1, or the processor 2 through bus switching circuits 10, and 10'. The processors 1 and 2 are equipped with functions to perform the read and the write of the specific value at the specific address of the memory 9, and it is decided to which processor, 1 or 2, the memory 9 is connected, by the operation of the function. The circuits 10 and 10' are switched by a switch control circuit 14, and the data in the memories 3 and 6 are transferred alternately by using a simplified circuit through the memory 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer system, and more specifically to a system in which data can be transferred between memories by switching buses.

[Conventional technology]

In recent years, devices using microprocessors have become increasingly diverse.

When using the currently mainly used 8-bit microprocessor as a device that performs various types of processing while communicating at high speed, its processing speed cannot be said to be fast enough. High-speed systems are supported by using high-level microprocessors or multiple 8-bit microprocessors to distribute processing functions.

As described above, there are methods to increase speed, but when using multiple microprocessors to perform processing operations as in the latter method, in order to make each microprocessor operate effectively, it is necessary to Transfer of microprocessor memory data is required. Conventionally, a DMA (direct memory access) method has been used as a data transfer method for this purpose.

[Problem that the invention seeks to solve]

However, if such data transfer between memories is performed using the conventional DMA method, a control circuit for DMA transfer (transfer using direct memory access control) must be used; The configuration is not easy.

That is, in the case of the DMA method, since data is transferred directly between memories without going through a microprocessor, the address signal generation circuit of the transfer memory and the start address of this address signal generation circuit.

It requires a circuit to control the address length (transfer data length), which has the disadvantage of being complicated and expensive.

The purpose of the present invention is to eliminate these drawbacks of the conventional method,
It is an object of the present invention to provide a data transfer method that allows data transfer between memories of respective processors with a simple configuration.

[Means for solving problems]

The data transfer method of the present invention includes a first processor, a second processor, a shared memory used by these processors, and a bus for this shared memory selectively transferred to the first processor side and the second processor side. The present invention is characterized in that it has a switching connection means for switching connection to the memory, and a means for writing and reading a specific value to and from a specific address of the shared memory in each of the first and second processors.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a case where two microprocessors are used and memory data of each microprocessor is transferred.

In the figure, 1 is a main microprocessor, 2 is a sub-microprocessor, and the main microprocessor 1 side has a memory 3. I10 control circuit (110C0NT)
4. It has ROM5, and similarly, the sub-microprocessor 2 side also has memory 6 and I10 control circuit (110C0NT).
, ROM8.

9 is a shared memory used to transfer data between the memories 3 and 6 of each microprocessor 1.2; 10.10
' is the data bus 11 of the shared memory 9. address bus 12
14 is a bus switching control circuit for controlling these bus switching circuits 10 and 10'', and the bus switching circuit 10 is connected to the main micro The bus switching circuit 10' is inserted between the data bus 11, address bus 12, and control line 13 on the processor 1 side, and the bus switching circuit 10' is inserted between the data bus 11, address bus 12, and control line 13 of the two sub-microprocessors. inserted in between.

The bus switching control circuit 14 includes a flip-flop (F, F,) 15 controlled by the I10 control circuit 4, 6 on the side of each microprocessor 1.2;
The bus switching circuit 10 is also provided with a driving section 16 that drives the bus switching circuits 10 and 10' using the output of the flop 15.

Thus, in this example there is a shared memory 9 and a bus switching circuit 10.10 between the two microprocessor systems.
' and a bus switching control circuit 14 are provided, and these bus switching circuits 10, 10' and the bus switching control circuit 14 control the data bus 11 and address bus 1 of the shared memory 9.
2 and the control line 13 to the sub microprocessor 2.
The bus is switched such that the connection is switched to the main microprocessor 1 side under control from the main microprocessor 1, or the bus is switched to the sub microprocessor 2 side under control from the main microprocessor 1.

Further, the main microprocessor 1 and the sub-microprocessor 2 each have a function of writing and reading a specific value to a specific address of the shared memory 9. In other words, by writing a specific value to a specific address among the addresses allocated to the shared memory 9 and reading the contents of the same address, it is determined whether the written value can be read correctly.
Currently, it is possible to determine which side the shared memory 9 is connected to. For example, if the shared memory 9 is switched to the sub-microprocessor 2 side, the sub-microprocessor 2 side , since the written value can be read correctly, the state that the shared memory 9 is connected to the sub-microprocessor 2 side is detected, and in this state, the shared memory 9 and the shared memory 6 of the sub-microprocessor 2 are connected. All you have to do is transfer data between the memory 9 and the main microprocessor 10F.
The same applies when connected to I.

In this way, the main microprocessor 1 and the sub-microprocessor 1
Each microprocessor 2 writes a specific value to a specific address in the shared memory 9, and reads the value.For example, such a method includes writing a specific value in the ROM 5.8 on each side. It can be constructed by incorporating a program that periodically performs such writing and reading operations and determines whether or not reading can be performed correctly.

Next, we will discuss the data transfer operation according to this method, taking as an example the case where the sub-microprocessor 2 transfers the data in the memory 6 on the sub-microprocessor 2 side to the memo I73 of the main microprocessor 1. explain.

When the sub-microprocessor 2 transfers data in the memory 6 on the sub-microprocessor 2 side to the memory 3 of the main microprocessor 1, the sub-microprocessor 2 transfers data from the memory 6 on the sub-microprocessor 2 side to the memory 3 of the main microprocessor 1. , by periodically writing a specific value to a specific address and reading the contents of the same address, when the written value can be read correctly, the shared memory 9
Detects the state of connection to the sub-microprocessor 2 side, transfers the data in the memo I76 of the sub-microprocessor 2 to the shared memory 9, and makes it possible to transfer the data to the memory 3 of the main microprocessor 1. . After that, sub-microprocessor 2's ! 10 control circuit 7 controls flip-flop 15 of bus switching control circuit 14 to switch the bus of shared memory 9 to the main microprocessor 1 side.

Similarly to the sub-microprocessor 2, in the main microprocessor 1, the shared memory 9 is connected to the main microprocessor 1 by being able to correctly read the written value to a specific address in the shared memory 9. main microprocessor 1
transfers the data in the shared memory 9 to the memory 3 of the main microprocessor 1 using an inter-memory transfer instruction.

When the transfer of the memory area is completed, the main microprocessor 1 controls the flip-flop 15 of the bus switching control circuit 14 from the I10 control circuit 4 of the main microprocessor 1, and switches the bus of the shared memory 9 to the sub-microprocessor. Switch to processor 2 side.

In this way, when data is transferred from the sub-microprocessor 2 side to the main microprocessor 1 side, the data bus 11. The line 13 that controls the address bus 12 and the read/write of the shared memory 9 is sub-wired.
The connection is switched to the main microprocessor 1 side under the control of the microprocessor 2, and the connection is switched to the sub microprocessor 2 side under the control of the main microprocessor 1.

In this way, the bus of the shared memory 9 is switched to the sub-microprocessor 2 side, the shared memory 9 is returned to the control of the sub-microprocessor 2, and the next transfer is started.

〔Effect of the invention〕

As described above, according to the present invention, data can be transferred by switching buses, and a data transfer system with a simple configuration can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Main microprocessor 2...
Sub-microprocessor 3.6...Memory 4.7...I10 control circuit 5.8...ROM 9...Shared memory 10.10゛...Bus switching circuit 11... Data bus 12... Address bus 13... Control line 14... Bus switching control circuit 15... Flip-flop 16... Drive unit

Claims (2)

[Claims] (1) Switching for selectively connecting the first processor, the second processor, the shared memory used by these processors, and the bus of this shared memory to the first processor side and the second processor side. A data transfer system comprising: a connection means; and a means for writing and reading specific values to and from specific addresses of a shared memory in the first and second processors, respectively. (2) In the data transfer method according to claim 1, the switch-connected bus is a data bus, an address bus, and a line for controlling writing and reading of a shared memory,
The switching connection means switches and connects these data buses, address buses, and lines for controlling write and read operations to the first processor side under control from the second processor, and
A data transfer method characterized by switching connection to a second processor under control from a first processor.