JPH04263333A - Memory duplication system - Google Patents

Abstract

PURPOSE:To shorten the processing restarting time after the switch of systems for a duplex device containing a duplex memory by taking over the contents of the memory without copying the memory after the switch of systems. CONSTITUTION:The address lines, the data lines, and the control lines which are set between a memory control part 5 and a memory 3 and between a memory control part 6 and a memory 4 respectively are connected to each other via the confounding buffers 1 and 2. When the memory 3 is identical with an ACT, both buffers 1 and 2 transmit the signals to the memory 4 from the memory 3. Then the control operation of the part 6 is inhibited to the memory 4. Therefore the data are simultaneously written into an ACT system memory 3 and an SBY system memory 4. When the memory 4 is identical with an ACT, the buffers 1 and 2 transmit the signals to the memory 3 from the memory 3. Then the control operation of the part 5 is inhibited to the memory 5. As a result, the secured between the ATC and SBY system coincidence of contents is always secured between the ATC and SBY system memories.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory duplication system for a duplex configuration device.

0002

2. Description of the Related Art In the conventional memory duplication system, as shown in FIG. It has a memory control section 9, an A-system memory 3, a B-system central processing unit 8, a B-system memory control section 10, and a B-system memory 4.

Next, the operation of the conventional system will be explained using FIG. Normally, the A-system central processing unit 7 accesses the A-system memory 3 via the A-system bus 11. Similarly, the B-system central processing unit 8 accesses the B-system memory 4 via the B-system bus 12.

[0004] Now, assuming that system A is ACT, when system A's central processing unit 7 becomes a failure and system B becomes ACT due to ACT/SBY switching logic (not shown), central processing unit 8 of system B becomes ACT. A to carry out processing in system B
It is necessary to copy the contents of the system memory 3 to the B system memory 4. Therefore, the B-system central processing unit 8 uses the A-system memory 3.
Then, a memory read is performed and a copy operation of writing to the B system memory 4 is performed. As a result, the B-system central processing unit 8 processes the contents of the A-system memory 3.

[0005]

In the conventional memory duplication system, since memory copying is performed in order to take over processing, there is a problem in that it takes time to restart processing after system switching.

[0006]

[Means for Solving the Problems] The memory duplication system of the present invention provides address lines, data lines, and control lines between memories of each system and a memory control unit that controls writing/reading of this memory in duplexed memories. is provided with a confounding means for confounding between both systems, ACT/SB for the memory
controlling the signal transmission direction of the confounding means and the execution of a control operation for the memory by the memory control unit by the Y signal;
The structure is such that when writing to the ACT type memory, writing is also performed to the SBY type memory at the same time.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. First, a system consisting of the central processing unit 7, the memory control unit 5, the memory 3, the confounding buffer 1, and the buffer control unit 13 is referred to as system A, and the central processing unit 8, the memory control unit 6,
A system constituted by the memory 4, the confounding buffer 2, and the buffer control section 14 is referred to as a B system. The A-system central processing unit 7 and the A-system memory control unit 5 are connected via the A-system bus 11,
The B-system central processing unit 8 and the B-system memory control unit 6 are connected via the B-system bus 12. Next, connect the address line, data line, and control line connecting the memory control unit 5 and memory 3 of system A to the buffer 1 for confounding with system B, and connect the memory control unit 6 of system B and memory 4. The address lines, data lines, and control lines are connected to the interlacing buffer 2 with the A system, and the interlacing buffer 1 and the interlacing buffer 2 are connected. The buffer control units 13 and 14 are ACT/S (not shown).
The ACT signal from the BY control section is input to control the signal transmission direction of the confounding buffers 1 and 2.

Next, a memory write operation when the A system is ACT will be explained.

[0010] When the A system is ACT, the buffer control unit 13
instructs the confounding buffer 1 to change the signal transmission direction from the A system to the B system. On the other hand, the B-system buffer control unit 14 receives the SBY signal, and the confounding buffer 2
The signal transmission direction is directed from the A system to the B system. When the A-system central processing unit 7 writes data to the memory 3, the memory control unit 5 outputs an address, data, and a write signal to the memory 3. This signal is also output to the B-system memory 4 via the confounding buffer 1 and the confounding buffer 2. Therefore, writing was performed to the A-system memory 3 and the B-system memory 4 at the same time. At this time, the B-system memory control unit 6, which is SBY,
A BY signal is being input, and signal output to the memory 4 is stopped.

Next, a memory read operation will be explained.

The signal transmission direction of the confounding buffers 1 and 2 has already been changed from the A system to the B system. When the A-system central processing unit 7 reads data from the memory 3, the memory control unit 5
outputs an address and a read signal to the memory 3. This signal is also output to the B-system memory 4 via the confounding buffers 1 and 2. Therefore, read operations are performed simultaneously on the A-system memory 3 and the B-system memory 4. but,
At this time, the data output by the memory 4 is stored in the confounding buffer 2.
is directed toward B system, so it is not output to A system. Therefore, the data output from the A-system memory 3 is read into the central processing unit 7.

When the B system is ACT, the confounding buffer 1
, 2 are reversed, and the operation for the B-system memory 4 is the same as described above.

[0014]

[Effects of the Invention] As explained above, the present invention intertwines address lines, data lines, and control lines for memory in both systems via a confounding buffer, and writes to SBY memory at the same time when writing to ACT memory. This has the effect of making memory copy unnecessary after system switching and shortening the time until processing restarts.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a memory duplication system according to the prior art.

[Explanation of symbols]

1, 2 Confounding buffers 3, 4 Memories 5, 6, 9, 10 Memory control units 7, 8
Central processing unit 11, 12 Bus 13, 14 Buffer control unit

Claims (1)

[Claims] 1. In a duplex memory, a confounding means is provided for confounding address lines, data lines, and control lines between the memory of each system and a memory control unit that controls writing and reading of this memory between both systems, A for the memory
The signal transmission direction of the confounding means and the execution of the control operation for the memory by the memory control unit are controlled by the CT/SBY signal, and when the ACT system writes to the memory, the SBY
A memory duplication system characterized in that writing is simultaneously performed on the memory of the system.