JPS59135684A - Data bypass system between buffer memories - Google Patents

Abstract

PURPOSE:To reduce the transfer time by providing a means bypassing data from a write data bus of a storage device to a read data bus and transferring data directly between buffer memories via the bypass means as required. CONSTITUTION:If a data required for a central processing unit 1 does not exist in a buffer memory 3, since the central processing unit 1 accesses a storage device 16 and reads the required data, a read request is transmitted. When the data requested by the central processing unit 1 exists in the buffer memory 6 of the central processing unit 2, the move-out of data is instructed to the central processing device 2 and the mode is in the stand-by state until the move-out of the central processing unit 2 is accessed. When the move-out is accessed from the central processing unit 2, a control circuit 8 stores the data transmitted from the buffer memory 6 via a write data bus 18 to a register 13 via a selection circuit 11, switches the selecting circuit 10 and transmits the data to a buffer memory 3 at the same time via a read data bus 20.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a central processing unit equipped with a buffer memory, and a storage device (main storage device) to which a plurality of central processing units can be connected The present invention relates to a swap-type multiprocessor system equipped with an intermediate buffer storage device (intermediate buffer storage device provided in a multiprocessor system), and particularly relates to a data bypass method between buffer memories that reduces data transfer time between processors in the multiprocessor system.

(b) Conventional technology and problems A central processing unit with a conventional buffer memory.

In a swap-type multiprocessor system equipped with a storage device to which a plurality of central processing units can be connected, there is a loop I for transferring data between the storage device and the buffer memory of the central processing unit. Since there is no data bypass route within the device, if it becomes necessary to directly transfer data between central processing units, there is no means to transfer data between the buffer memories of the central processing units, and the data is temporarily stored in the memory. After writing data to the device, the only way is to read it and transfer it. Therefore, there is a drawback that additional time is required for the write and read sequences in the storage device.

(C) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks by reducing the amount of data required in each central processing unit or the central processing unit.

If the data exists in the buffer memory of another central processing unit, the data is bypassed to the requesting central processing unit in parallel with writing the data moved out from the other central processing unit to the storage device; The object of the present invention is to provide a data bypass method between buffer memories that makes it possible to shorten transfer time.

(d) Structure of the Invention The structure of the present invention is a swap-type multiprocessor system that includes a central processing unit equipped with a backup memory and a storage device to which a plurality of the central processing units can be connected. A means for bypassing data from a write data bus to a read data bus is provided, and when data transfer is required between the buffer memories, data is transferred directly between the backup memories via the bypass means. This is what I did.

(e) Examples of the invention The figure is a block diagram of a circuit showing one embodiment of the present invention.

The central processing unit 1 has a buffer memory 3.

A tag 4 storing address information, validity, etc. of the buffer memory 3 is built-in, and the central processing unit 2 has a tag 5 storing address information, validity, etc. of the buffer memory 6 and the third pamphlet notebook 6. Built-in. The storage device 16 has a tag 7 to which the contents of the tag 4 are copied, and a tag 9 to which the contents of the tag 5 are copied. Here, the operation will be explained focusing on the central processing unit 1.

The data required by the central processing unit 1 is stored in the buffer memory 3.
When there is no such data, the central processing unit 1 accesses the storage device 16 to read the necessary data.

Sends out the read rifnis I. The control circuit 8 of the storage device 16 refers to the tag 9, checks whether the data requested by the central processing unit 1 exists in the buffer memory 6 of the central processing unit 2, and if the data exists, transfers the data to the central processing unit 2. to move out.

It is in a waiting state until it receives a move-out access from the central processing unit 2. When there is a move-out access from the central processing unit 2, the control circuit 8 selects the data sent from the backup memory 6 via the write data bus 18 to the selection circuit 1.
1, the data is stored in the register 13, and the 9 selection circuit 10 is switched to simultaneously send the data to the backup memory 3 via the read data bus 20. With the data written to the buffer memory 3, the read operation of the central processing unit 1 is completed.

The data stored in the register 13 is then written to the memory 14 when the central processing unit 1 accesses the storage device 16 to read data.

If the requested data does not exist in the buffer memory 6,
Data is read from the memory 14 into the register 15 and sent to the buffer memory 3 via the 1 selection circuit 10.

The operation centered on the central processing unit 2 is the same as above, but the referenced tag is 7, and the data moved from the backup memory 3 is transferred via the write data bus 19 and through the selection circuits 11 and 12. and read data bus 17
The data is transferred to the buffer memory 6 through the process.

(f) Detailed Description of the Invention As described in detail, the present invention is applicable to a case where data required by a relative central processing unit of each central processing unit exists in the backup memory of another central processing unit.

In parallel with writing the data moved out from the other central processing unit to the storage device, the data can be bypassed to a requesting central processing unit to shorten the transfer time. The effect is great.

[Brief explanation of the drawing]

The figure is a block diagram of a circuit showing one embodiment of the present invention. 1.2 is a central processing unit 53, 6 is a buffer memory; 4.
．． 5, 7.9 is a tag, 8 is a control circuit, 10°11.12
is a selection circuit, and 13.15 is a register. 14 is a memory, and 16 is a storage device.

Claims (1)

[Scope of Claim] A swap-type multiprocessor system comprising a central processing unit equipped with a buffer memory and a device A to which a plurality of central processing units can be connected. In the case where means for bypassing data from a write data bus to a read data bus of the storage device is provided, and data transfer between the sofa memories is required. A data bypass method between buffer memories, characterized in that data is directly transferred between buffer memories via the bypassing means.