JPS6243737A - Interrupt control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention has a built-in buffer memory of relatively small capacity that can be accessed at learning speed, and stores information in main memory at a constant zero.
) This invention relates to increasing the speed of interrupt processing in a processing device, which aims to speed up processing by once transferring each size to a batza memory and accessing the buffer memory (hereinafter referred to as a cache method).

[Background of the invention]

Conventional devices use a cache method as described in Japanese Patent Application Laid-open No. 59-176848, and the new/old PSW (program status word) is stored in the main memory according to the execution status of the program in the same way as general programs and data. Even with the above technology, when an interrupt occurs, the area containing the new PSW in the main memory is stored in the buffer memory and the corresponding new PSW is transferred to and from the buffer memory.
It has the disadvantage that it requires a long transfer time to load into the SW register.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to eliminate the above-mentioned drawbacks, an object of the present invention is to provide an interrupt control method that eliminates the need for a processing procedure for storing an area containing a new PSW in main memory in a buffer memory when an interrupt occurs.

[Summary of the invention]

The reason why the method shown in the prior art has been adopted is that the high-speed memory element used in the buffer memory has a relatively small capacity and is expensive, and the main focus has been on reducing the cost of the device. However, 7. The speed and large capacity of memory elements,
Price reductions have been rapidly realized in recent years with advances in semiconductor technology. Under these circumstances, in the present invention, in order to achieve the above object, the t
By fixedly accommodating the hP SW area in a buffer memory separate from a general buffer memory, a faster interrupt control method is realized.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of an information processing device, in which 1 is a processor, 2 is a backup memory in which general program data is stored, and 5 is a storage area for storing old PSW area (system area) according to the present invention. 4 indicates a backup memory, 4 indicates a main memory, and 5 indicates a current PSW register.

In the case of the cache method, access between the buffer memory 2.3 and the main memory 4 is normally realized by an address conversion mechanism (not shown), but in the present invention, the backup memory 2.3 is realized by an address conversion mechanism (not shown). Does B exist in the same address space as seen from the processor 1?The backup memory 2 is a copy of the main memory 4, and its address area is incorporated in the address conversion mechanism, whereas the buffer memory 5 is a fixedly allocated address area, and there is no mechanism to refer to main memory. Note that the buffer memories 2 and 3 are similarly constructed of high-speed memory elements.

In Fig. 1, the new/old 1) SWσ) area is always stored in the buffer memory 3 and can be accessed directly from the processor at high speed, so when an interrupt cause occurs,
The Ipsw corresponding to the cause of the interrupt is stored in the buffer memory 3.
is directly loaded into the current PSW register 5, and the process is performed.

According to this embodiment, there is no need for the processing procedure of storing the area of the main memory containing the new PSW in the backup memory in conjunction with interrupt processing, making it possible to increase the number of interrupt processing operations and reduce the number of control hardware. becomes.

〔Effect of the invention〕

According to the present invention, there is no need for a process to store the main memory area containing the new PSW in the backup memory in conjunction with interrupt processing, thereby speeding up interrupt processing and
This has the effect of reducing the amount of control hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing apparatus showing an embodiment of the present invention. 1...Processor, 4...Main memory,

Claims (1)

[Claims] 1. In an information processing device that writes information to a buffer memory in units of a fixed size area on the main memory and accesses the buffer memory for processing, an area of a new PSW corresponding to each interrupt of the processor is created. An interrupt control method characterized in that an interrupt is fixedly stored in a buffer memory different from the buffer memory.