JPH07319720A - System switching method for processor - Google Patents

Abstract

PURPOSE:To shorten the system switching time for a duplex processor. CONSTITUTION:A duplex processor consists of a 1st CPU, a 1st memory, a 1st memory controller, a 1st processor containing a 1st arbiter which controls at least a controller connected to a bus, a 2nd CPU, a 2nd memory, a 2nd memory controller, and a 2nd processor containing a 2nd arbiter which controls at least a controller. In such a constitution, the 1st and 2nd memory controllers always keep the same contents between the 1st and 2nd memories and stops (S2) and starts (S4) the 1st and 2nd arbiters respectively. Thus the system is switched to the 2nd processor from the 1st processor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic exchange system having dual processors, and more particularly to a system switching system for processors.

[0002]

2. Description of the Related Art An operation example of a conventional processor switching system will be described with reference to the drawings. FIG. 2 is a block diagram of a duplex processor system to which a conventional processor switching system is applied.

As shown in FIG. 2, the active processor 10 comprises a CPU 11, an arbiter 12, a memory 13 and a memory controller 14, and a standby spare processor 20 comprises a CPU 21, an arbiter 22, a memory 23 and a memory controller. ., 3n (n is a natural number) connected to a bus 30 including n controllers (hereinafter referred to as agents) 31, 32, ... Has become. The arbiter 12 of the active processor and the arbiter 22 of the standby spare processor are both agents 31, 3 on the bus 30.
2, ... 3n is controlled. The memory controller 14 of the active processor controls the memory 13 of the active processor, and the memory controller 24 of the standby spare processor controls the memory 23 of the standby spare processor.

Conventionally, when switching the processor system, each agent 31, 3 connected to the bus 30 is switched.
Execute the stop command for 2, 3 ... 3n. If there is data in each agent 31, 32, ..., 3n, the data is swept out to the bus 30, and after confirming that all the agents have stopped using the bus, the active processor The contents of the memory 13 are copied to the memory 23 of the standby spare processor. After that, each agent 31, 32, ...
It was necessary to start the system and switch the processor system from the active processor 10 to the standby spare processor 20.

[0005]

However, in such a conventional system switching system of a processor, since the system is switched after copying the contents of the memory after stopping the agent, the system switching is completed. There was a problem that it took time.

In view of the above points, an object of the present invention is to shorten the system switching time of the duplex processor.

[0007]

A system switching system of a processor according to the present invention includes a first CPU, a first memory, and a first CPU.
A memory controller and a first arbiter for controlling at least one controller connected to the bus, a second CPU, a second memory, and a second memory controller. And a second processor having a second arbiter for controlling the at least one control device, wherein the first and second memory controllers store the contents of the first memory and the first memory controller. The contents stored in the second memory are always equalized, and the first arbiter is stopped and the second arbiter is activated to switch the system from the first processor to the second processor.

In the system switching system of the processor of the present invention, when the first and second memory controllers make a write request to the first memory, the second memory controller writes the data to the first memory and the second memory at the same time. When the same content is written in the first memory and a read request is issued to the first memory, the stored content of the first memory is compared with the stored content of the second memory, and the first address at the read address is compared. When the storage content of the first memory is different from the storage content of the second memory, the storage content of the first memory is stored by writing the storage content of the first memory to the second memory at the same time. The contents and the contents stored in the second memory can always be made equal.

Further, in the processor system switching method of the present invention, the at least one control device may include a data buffer having a capacity capable of waiting for a time required for system switching of the redundant processor.

[0010]

[Action]

(1) Since the system is switched from the first processor to the second processor by stopping the first arbiter and activating the second arbiter, the procedure required for system switching is reduced, and the system of the redundant processor is The switching time can be shortened.

(2) When the first and second memory controllers make a write request to the first memory,
When writing to the first memory and writing the same content to the second memory at the same time, and when there is a read request to the first memory, the stored content of the first memory is compared with the stored content of the second memory. If the stored contents of the first memory and the stored contents of the second memory at the read address are different, the stored contents of the first memory are read out and written into the second memory at the same time. Since the storage contents of the first memory and the storage contents of the second memory are always made equal, there is no need to copy the storage contents from the first memory to the second memory when switching the system, and the system switching time of the redundant processor can be reduced. It can be shortened.

(3) Since at least one control device is provided with a data buffer having a capacity capable of waiting for the time required for switching the system of the redundant processor, it is not necessary to sweep out the data to the bus when switching the system,
It is possible to shorten the system switching time of the redundant processor.

[0013]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an operation flowchart of one embodiment of the present invention, and shows the switching operation of the processor system in the block diagram of FIG.

The details of the configuration of FIG. 2 are as described in the prior art, except that each agent 3 is different.
.., 3n are each provided with a data buffer (not shown) that allows waiting for the time required for switching the system from the active processor 10 to the standby spare processor 20.

The difference between the operation of FIG. 2 and the prior art is that the memory controller 14 of the active processor and the memory controller 24 of the standby spare processor constantly monitor the memory access. At the time of write access to the memory 13 of the active processor, the memory controller 14 of the active processor also causes a write access to the memory 23 of the standby spare processor, and the same address is the same in the memory 13 of the active processor and the memory 23 of the standby spare processor. The data content of is written. Further, at the time of read access to the memory 13 of the active processor,
If the contents stored in the memory 13 of the active processor and the contents stored in the memory 23 of the standby spare processor are different, it is determined that the contents of the memory 13 of the active processor are correct, the contents of the memory 13 of the active processor are read, and the standby spare processor is read. To the memory 23. With such a function, the contents of the memory 13 of the active processor and the memory 23 of the standby spare processor are always the same.

The operation of FIG. 1 will be described based on the configuration of FIG. When a failure occurs in the active processor 10 (S
In 1), the arbiter 12 of the active processor is stopped to switch the system to the standby spare processor 20 (S).
Along with 2), the CPU 11 of the active processor outputs a system switching signal to the CPU 21 of the standby standby processor,
System switching is notified (S3). At this time, the bus 30
Since the arbiter is temporarily gone, it is no longer used. When the standby standby processor 20 receives the system switching signal from the active processor 10, the standby standby processor 20 can be executed immediately by starting the arbiter 22 (S4), and the system switching from the active processor 10 to the standby standby processor 20 is completed. (S5).

A plurality of agents 31, 32, ...
3n is a standby spare processor 2 from the active processor 10.
By buffering the information for the system switching time to 0 in the data buffer, the active processor 1
The system can be smoothly switched from 0 to the standby spare processor 20.

[0018]

As described above, the present invention has the effects described below.

(1) By switching the system from the first processor to the second processor by stopping the first arbiter and activating the second arbiter, the procedure required for system switching is reduced, and duplication is realized. This has the effect of shortening the switching time of the processor system.

(2) When the first and second memory controllers make a write request to the first memory,
When writing to the first memory and writing the same content to the second memory at the same time, and when there is a read request to the first memory, the stored content of the first memory is compared with the stored content of the second memory. If the stored contents of the first memory and the stored contents of the second memory at the read address are different, the stored contents of the first memory are read out and written into the second memory at the same time. By always equalizing the storage content of the second memory with the storage content of the second memory, there is no need to copy the storage content from the first memory to the second memory when the system is switched, and the system switching time of the duplex processor is eliminated. It has the effect that can be shortened.

(3) Since at least one control device has a data buffer having a capacity capable of waiting for the time required for switching the system of the redundant processor, it is not necessary to sweep out the data to the bus when switching the system. The advantage is that the switching time of the redundant processor system can be shortened.

[Brief description of drawings]

FIG. 1 is an operation flowchart of an embodiment of the present invention.

FIG. 2 is a block diagram of a duplex processor system to which a conventional processor switching system is applied.

[Explanation of Codes] 10 Working Processor 11 CPU of Working Processor 12 Arbiter of Working Processor 13 Memory of Working Processor 14 Memory Controller of Working Processor 20 Standby Spare Processor 21 CPU of Standby Spare Processor 22 Arbiter of Standby Spare Processor 23 of Standby Spare Processor Memory 24 Memory controller for standby spare processor 30 Bus 31, 32, ..., 3n n agents

Claims (3)

[Claims] 1. A first CPU, a first memory, and a first memory.
A memory controller and a first arbiter for controlling at least one controller connected to the bus, a second CPU, a second memory, and a second memory controller. A second processor comprising a second processor having a second arbiter for controlling the at least one control device, wherein the first and second memory controllers have storage contents of the first memory and the second memory controller. The storage contents of the memory are always equalized, and the system is switched from the first processor to the second processor by stopping the first arbiter and activating the second arbiter. The system switching method of the processor. 2. The first and second memory controllers, when a write request is made to the first memory, write the same content to the second memory at the same time as writing to the first memory, When there is a read request to the first memory, the stored contents of the first memory and the stored contents of the second memory are compared, and the stored contents of the first memory at the read address and the second contents are compared. When the storage content of the first memory is different from the storage content of the first memory, the storage content of the first memory is read out and written to the second memory at the same time. The system switching system according to claim 1, wherein the contents are always the same. 3. The processor system switching system according to claim 1, wherein said at least one control device comprises a data buffer having a capacity capable of waiting for a time required for system switching of said duplex processor.