JPH0619634A - Disk controller provided with duplex memory - Google Patents

Abstract

PURPOSE:To improve the utilizing efficiency of a memory and also to improve the writing processing efficiency of data in a disk controller. CONSTITUTION:A control means 30 for comparing the respective residual capacity of a nonvolatile memory 27 and a volatile memory 28 and instructing the staging of the data to the memory having larger residual capacity is provided on a cash control means 29. When it is decided that the data for which read is requested by a host device 25 are erroneous, the data read from a disk device 3 are transferred to the host device 25 and the staging is performed to either the nonvolatile memory 27 or the volatile memory 28 instructed by the cash control means 29, and then, when it is decided that the data for which write is requested by the host device 25 are a hit, the data for which the write is requested are written in the pertinent rewrite area of the memory stored with the hit staged data and only the write data are written in the other memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk controller having a non-volatile memory and a volatile memory. The present invention relates to a disk control device having a dual memory that enhances data write processing efficiency.

Some disk control devices have a cache mechanism, and when the data requested to be read by the host device exists in the cache memory, it is read from the cache memory and transferred. Therefore, it is possible to perform high-speed processing because no mechanical operation of the disk device is involved.

Further, when writing data, if the data existing in the cache memory is rewritten, the data is written in the cache memory to terminate the data transfer with the host device, and then the cache is available when there is a margin of operation. Writing from the memory to the disk device. Therefore, in this case as well, high speed processing can be performed since no mechanical operation of the disk device is involved.

By the way, if the memory for storing the data before writing to the disk device is volatile, the data disappears when the power is cut off, and therefore the current is supplied from a backup power supply such as a battery to operate. A non-volatile memory is used.

However, since this non-volatile memory is expensive, it has a smaller capacity than the volatile memory normally used.
Therefore, only the write data is written in this non-volatile memory, and the data staged from the disk device is written in the volatile memory. At the same time, the write data is also written in the corresponding data area of the staged data stored in this volatile memory by a method called “hawking write”.

As described above, although the capacity of the non-volatile memory is small, it is necessary that the use efficiency of the memory and the data write processing efficiency are not lowered for this reason.

[0007]

2. Description of the Related Art FIG. 5 is a block diagram for explaining an example of a conventional technique, and FIG. 6 is a detailed block diagram for each strong unit.

In FIG. 5, the disk controller 2 is composed of a plurality of functional units, and a channel adapter 4 is provided.
6A, the processor 13 reads the program stored in the control memory 14 to operate, and receives the start I / O command from the channel 1 via the interface circuit 12 and the channel 1 and data is also transferred to and from the other functional units via the common bus 11 by controlling the common bus control circuit 15.

The device adapter 5 has a structure as shown in FIG. 6 (A), and the processor 13 operates by reading a program stored in the control memory 14, and the interface circuit 12
Command is sent to the disk device 3 to transfer data to and from the disk device 3, and the common bus control circuit 15 is controlled to transfer data to and from another functional unit via the common bus 11. I do.

The cache control circuit 6 has a structure as shown in FIG. 6B, and the processor 17 operates by reading the program stored in the control memory 16 to control the common bus control circuit 18 to make another operation. The address sent by the functional unit is R
The data is stored in the AM 19, and whether or not there is data to be written or read in the volatile memory 8 is checked by this address. If it exists, it is determined to be a hit, and if it does not exist, it is determined to be a miss, and the channel adapter 4 or Notify the device adapter 5.

The resource manager 9 has a structure as shown in FIG. 6C, and the processor 21 operates by reading the program stored in the control memory 20 to control the common bus control circuit 22 to operate the common bus 11. All the start I / O commands from the channel 1 are received and stored in the RAM 23 via the centralized management of the start I / O commands.
The data transfer process is instructed to the channel adapter 4 and the device adapter 5 for each start I / O instruction.

Further, the control information for each received start I / O command, the control information for each channel path, and the disk device 3
Control information is stored in the RAM 23, and other functional units are RA
It is possible to access the RAM 23 via the M access control circuit 24 and read the above information, and centrally manage this information.

The volatile memory 8 is a memory whose stored contents disappear when the power supply of the device is stopped, and the non-volatile memory 7 is supplied with current from a backup power supply 10 such as a rechargeable battery even when the power supply of the device is stopped. The stored contents are retained.

When the channel 1 sends a start I / O command to the channel adapter 4 and gives an instruction to write data to the disk device 3, for example, the channel adapter 4 requests the resource manager 9 to use the common bus 11.
When permitted, the cylinder address, head address and record address are stored in the RAM 23 of the resource manager 9.

The cache control circuit 6 checks whether or not the data designated by the head address and the record address read from the RAM 23 of the resource manager 9 is stored in the volatile memory 8 and, if stored, a hit is detected by the channel adapter 4. And the address is sent to the non-volatile memory 7 and the volatile memory 8.

Therefore, the channel adapter 4 sends the data sent by the channel 1 to the non-volatile memory 7 and the volatile memory 8. Therefore, only the write data is written in the non-volatile memory 7, and the write data is written in the volatile memory 8 in the designated record of the data staged from the designated track.

When the cache control circuit 6 notifies the miss, the channel adapter 4 connects with the device adapter 5 according to the instruction of the resource manager 9 and accesses the disk device 3.

That is, the device adapter 5 is instructed by the resource manager 9 to execute the RAM of the resource manager 9.
When the cylinder address, the head address and the record address stored in 23 are read and the disk device 3 is controlled to position the head in the specified cylinder, the channel adapter 1 is attached to the specified head of the disk device 3.
The data to be sent by the device is sent, and the data is sequentially written from the designated record.

When instructed to read data from channel 1, the channel adapter 4 reads data from the volatile memory 8 and transfers it to channel 1 when the cache control circuit 6 notifies a hit.

When the cache control circuit 6 is notified of a miss, the channel adapter 4 causes the resource manager 9
, The data read from the disk device 3 is transferred to the channel 1.

At this time, the cache control circuit 6 performs a staging process for writing the data sent from the device adapter 5 to the volatile memory 8 because the data instructed to be read is missed.

FIG. 7 is a diagram for explaining how to use the memory. FIG. 7A shows the data storage contents of the non-volatile memory 7, and FIG. 7B shows the storage contents of the volatile memory 8.

As described above, the capacity of the volatile memory 8 is larger than the capacity of the non-volatile memory 7, and the volatile memory 8 is
Stores staged data (1) to (4). That is, the data (1) to (4) are read and stored from the designated record of the track of the disk device 3 designated to be read to the data of the last record of this track.

Assuming that the data instructed to be written by the channel 1 corresponds to the portion indicated by the data (1), the cache control circuit 6 notifies the hit. Therefore, as described above, the nonvolatile memory 7 is used. And the write data is written in the volatile memory 8, respectively.

Next, assuming that the data instructed to be written from the channel 1 corresponds to the portion indicated by the data (2), the cache control circuit 6 notifies the hit, and as described above, the nonvolatile control is performed. The write data is written in the nonvolatile memory 7 and the volatile memory 8, respectively.

Further, assuming that the data instructed to be written from the channel 1 corresponds to the portion indicated by the data (3), the cache control circuit 6 notifies the hit, and as described above, the nonvolatile memory is used. The write data is written in the nonvolatile memory 7 and the volatile memory 8, respectively.

[0027]

FIG. 8 is a diagram for explaining the problems of the prior art. As shown in the figure, it is assumed that the volatile memory 8 has staged data for 9 tracks, for example, and the data indicated by A to H is written as write data.
As shown in the figure, only write data, as shown by A to H,
It is written.

Since the capacity of the non-volatile memory 7 is small, a write back process is executed when the data H has been written and the capacity is exhausted. That is, in order to allow a sufficient capacity, the device adapter 5 writes the data H to one or more records of the corresponding track of the disk device 3 and writes the data G according to the instruction of the resource manager 9 as shown in the figure. Data G that has been written to the non-volatile memory 7 by writing to one or more records of the corresponding track of the disk device 3.
And a process of erasing H are executed.

By doing so, when the next write data J is hit, the write data J can be written in the non-volatile memory 7. However, since the channel adapter 4 cannot access the non-volatile memory 7 during this write back process, the write command from the channel 1 is kept waiting. Therefore, there is a problem that the data writing processing efficiency of the disk control device 2 is reduced.

To solve this problem, the capacities of the non-volatile memory 7 and the volatile memory 8 may be made equal, but there is a problem that this is not a good method for efficiently using the memories.

In view of the above problems, the present invention uses a volatile memory having a smaller capacity than the conventional volatile memory 8 and a non-volatile memory having the same capacity as the volatile memory having the smaller capacity, By using both memories evenly, it is possible to improve the write processing efficiency by eliminating the waiting of the write command and to improve the memory usage efficiency.

[0032]

FIG. 1 is a block diagram for explaining the principle of the present invention. The disk control device 26 includes a nonvolatile memory 27 that operates by being supplied with a current from the backup power source 10, a volatile memory 28 having the same storage capacity as the nonvolatile memory 27, and the nonvolatile memory 2
7 or a volatile memory 28, cache control means 29 for determining a hit when staging data including data to be written or read is present in one of the memories, and a miss when there is no such data The data transfer between the disk 25 and the disk device 3 is controlled.

The cache control means 29 is provided with a control means 30 for comparing the remaining capacities of the non-volatile memory 27 and the volatile memory 28 and instructing the memory having the larger remaining capacity for data staging. ing.

When it is determined that the data requested to be read by the host device 25 is a miss, the data read from the disk device 3 is transferred to the host device 25, and at the same time, the non-volatile data instructed by the cache control means 29. After staging to one of the memory 27 and the volatile memory 28, if it is determined that the data requested to be written by the host device 25 is a hit, the staging in which the data requested to be written is hit. The written data is written in the rewriting corresponding area of the memory in which the written data is stored, and only the write data is written in the other memory.

[0035]

By configuring as described above, the capacity of the volatile memory 28 can be made smaller than before, and the non-volatile memory 27 and the volatile memory 28 are used evenly, so that the memory usage efficiency is improved. It can be done.

Further, the non-volatile memory 27 and the volatile memory 2
Since the capacities of both memories 8 and 8 are equal and used evenly, the write-back processing due to the small capacity of the non-volatile memory is not performed. Therefore, it is possible to prevent the data write processing efficiency from decreasing.

[0037]

2 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a diagram for explaining the operation of FIG.

In FIG. 2A, the same reference numerals as those in FIG. 5 indicate the same functions. 2B is a detailed block diagram of the cache control circuit 31. In FIG. 2A, the disk controller 26 is composed of a plurality of functional units, the channel adapter 4, the device adapter 5, and the resource manager 9 are the same as above, and the cache control circuit 31 is 2 (B), the processor 17 operates by reading the program stored in the control memory 32, controls the common bus control circuit 18, and stores in the RAM 19 addresses sent by other functional units. Then, by this address, it is checked whether or not there is data to be written or read in the non-volatile memory 27 or the volatile memory 28, and if it exists, it is judged as a hit, and if it does not exist, it is judged as a miss, and the channel adapter is judged. 4 or the device adapter 5 is notified.

Then, the processor 17 uses the register A33.
Calculates and stores the remaining capacity of the non-volatile memory 27,
The remaining capacity of the volatile memory 28 is calculated and stored in the register B34.

When the remaining capacity stored in the register A33 is a and the remaining capacity stored in the register B34 is b, the device adapter 5 sends the data from the disk device 3 when it is determined that a data read instruction is missed. When the data is read out and transferred to the channel adapter 4, this data is staged.
When> b, the non-volatile memory 27 is instructed to be staged, and when a <b, the volatile memory 28 is instructed to be staged.

When it is determined that there is a hit at the time of a data write command, the write data is written in the corresponding portion of the hit staged data in the nonvolatile memory 27 or the volatile memory 28 in which the staged data is stored. In addition to the write instruction, the write instruction is written to the nonvolatile memory 27 or the volatile memory 28 in which the hit staged data is not stored.

The volatile memory 28 is a memory whose contents are lost when the power supply of the device is stopped, and the non-volatile memory 27 is powered from the backup power supply 10 such as a rechargeable battery even when the power supply of the device is stopped. Is supplied to hold the stored contents.

When the channel 1 instructs the channel adapter 4 to read the data, the cache control circuit 31 reads the data specified by the head address and the record address from the RAM 23 of the resource manager 9 into the non-volatile memory 27 as described above. Alternatively, it is checked whether the memory is stored in any one of the volatile memories 28, and if not stored, the error is notified to the channel adapter 4.

Therefore, when the channel adapter 4 is connected to the device adapter 5 to control the disk device 3 to read the designated data, the data is transferred to the channel 1.
At this time, since the cache control circuit 31 has notified the miss, the cache control circuit 31 determines the memory to be staged under the above conditions,
The device adapter 5 is instructed to read the data from the designated record to the last record of the designated track, and the address is sent to either one of the nonvolatile memory 27 and the volatile memory 28, and the device adapter 5 is read. The data to be sent by 5 is staged in one designated memory.

When the channel 1 instructs the channel adapter 4 to write the data, the cache control circuit 31 outputs the data designated by the head address and the record address read from the RAM 23 of the resource manager 9 to the non-volatile memory 27 as described above. Alternatively, it is checked whether the memory is stored in any one of the volatile memories 28, and if so, the channel adapter 4 is notified of the hit.

Therefore, the channel adapter 4 is not coupled to the device adapter 5 and transfers data to the non-volatile memory 27 and the volatile memory 28, and the cache control circuit 31 stores the address determined under the above conditions in the non-volatile memory. 27
To the volatile memory 28.

Therefore, the data sent by the channel adapter 4 is written in the non-volatile memory 27 and the volatile memory 28, respectively, as shown in FIG. That is, the volatile memory 28
When the data indicated by A of the staged data hits, the write data is A in the non-volatile memory 27.
Is written in the area shown in FIG.
It is also written in the part indicated by.

Similarly, when the data of the portion indicated by B of the staged data in the volatile memory 28 hits,
The write data is written in the area B of the nonvolatile memory 27 and also in the portion B of the volatile memory 28.

Similarly, when the data of the portions C to G of the staged data in the volatile memory 28 hit, the write data is written in the areas C to G of the non-volatile memory 27, respectively. , Are also written in the portions indicated by C to G of the volatile memory 28, respectively.

Further, when the data in the portion indicated by H of the non-volatile memory 27 is hit, the write data is written in the area indicated by H in the volatile memory 28, and by the H in the non-volatile memory 27. It is also written in the part shown.

Similarly, when the data in the portion indicated by J of the staged data in the non-volatile memory 27 hits, the write data is written in the area indicated by J in the volatile memory 28 and at the same time, in the non-volatile memory 27. It is also written in the part indicated by J.

Similarly, when the data of portions K to N and P of the staged data in the non-volatile memory 27 respectively hit, the write data is the K of the volatile memory 28.
To N and P, respectively, and at the same time, to the portions indicated by K to N and P of the non-volatile memory 27.

The addresses of the areas A to G of the non-volatile memory 27 and the areas H, J to N and P of the volatile memory 28 are determined by the cache control circuit 31 from the remaining capacity of each memory. Since the data storage area is searched and determined, it is written at a random position.

FIG. 4 is a flow chart for explaining the operation of FIG. The channel adapter 4 monitors the instruction reception in step (1). When the instruction is received, the read instruction is checked in step (2), and if it is a read instruction, it is checked in step (3) whether there is a hit.

When notified of a miss from the cache control circuit 31, the channel adapter 4 transfers the data read from the disk device 3 to the channel 1 via the device adapter 5 in step (4).

At this time, the cache control circuit 31 checks in step (5) whether a> b. That is, the nonvolatile memory 27
If the remaining capacity of the non-volatile memory 27 is larger than the remaining capacity of the volatile memory 28, the non-volatile memory 27 is instructed to be staged in the non-volatile memory 27 in step (6), and the non-volatile memory 27 is instructed in step (5).
If the remaining capacity of the volatile memory 28 is smaller than the remaining capacity of the volatile memory 28, it is instructed to stage the volatile memory 28 in step (7).

The channel adapter 4 checks in step (8) whether the data transfer is completed, and if it is completed, the step (1) is executed.
If the data transfer is not completed, the process returns to step (4).

When the channel adapter 4 is notified of the hit in step (3), it reads the data from the memory in which the data specified in step (14) exists and transfers it to channel 1, and the data is read in step (9). When the transfer is completed, the process returns to step (1). If the data transfer is not completed, the process returns to step (14).

If the command received in step (2) is a write command, the channel adapter 4 moves to the process of step (10) and checks if there is a hit. Cache control circuit 31
When the hit is notified by the channel adapter 4, the write data is written in the corresponding portion of the memory in which the staging data exists and the write data is written in the other memory according to the address sent by the cache control circuit 31 in step (11). Write only.

Then, in step (13), it is checked whether or not the data writing is completed. If it is completed, the process returns to step (1), and if not completed, the process returns to step (10). In addition, step (1
When the error is notified in 0), the data is written to the disk device 3 via the device adapter 5 in step (12), and the process proceeds to step (13).

[0061]

As described above, according to the present invention, since the non-volatile memory and the volatile memory can be used evenly, the efficiency of use of the memory is improved, and the write-back processing is not required, so that the write processing efficiency is improved. Can be improved.

Since the write data is stored in the non-volatile memory and the volatile memory, even if the power supply of the apparatus is stopped, it is guaranteed by the data in the non-volatile memory and one memory becomes an obstacle. Can also write data back to the disk device from the other memory.

When the non-volatile memory becomes a failure,
Data can be written back from the volatile memory to the disk device, and the data read operation can be continued thereafter. When a failure of the volatile memory occurs, one track of data is stored in the non-volatile memory so that the data can be written. And the read operation can be continued.

When 1/4 of the staged data is written on the non-volatile memory, the capacity of the volatile memory can be set to 4/5 as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a diagram for explaining the operation of FIG.

FIG. 4 is a flowchart illustrating the operation of FIG.

FIG. 5 is a block diagram illustrating an example of conventional technology.

FIG. 6 is a detailed block diagram of each functional unit.

FIG. 7 is a diagram illustrating a memory usage method.

FIG. 8 is a diagram for explaining the problems of the conventional technology.

[Explanation of symbols]

 1 channel 2, 26 disk controller 3 disk device 4 channel adapter 5 device adapter 6, 31 cache control circuit 7, 27 non-volatile memory 8, 28 volatile memory 9 resource manager 10 backup power supply 11 common bus 12 interface circuit 13, 17 , 21 Processors 14, 16, 20, 32 Control memory 15, 18, 22 Common bus control circuit 19, 23 RAM 24 RAM access control circuit 25 Upper device 29 Cache control means 30 Control means 33 Register A 34 Register B

Claims (1)

[Claims] 1. A non-volatile memory (27) which operates by being supplied with a current from a backup power supply (10), and the non-volatile memory.
A volatile memory (28) having the same storage capacity as (27) and staged data including data to be written or read to either one of the nonvolatile memory (27) or the volatile memory (28) A disk control device (26) for controlling data transfer between the host device (25) and the disk device (3), which comprises a cache control means (29) for judging a hit when it exists and a miss when it does not exist ), The cache control means (29) includes the nonvolatile memory (2
7) and the remaining capacity of the volatile memory (28) are compared with each other, a control means (30) for instructing staging of data is provided in the memory with the larger remaining capacity, and the host device (25) requests reading. If the data is determined to be a miss, the data read from the disk device (3) is transferred to the host device (25), and the nonvolatile memory (27) or the cache control means (29) instructs After staging in any one of the volatile memory (28), if it is determined that the data requested to be written by the host device (25) is a hit, the data requested to be written is
A disk controller equipped with a duplicated memory, which writes to a rewriting corresponding area of a memory in which hit staging data is stored, and writes only write data to the other memory.