JPH08166905A - Cache memory control method - Google Patents

Abstract

PURPOSE: To reflect the change of a content in a main storage device on cache memories without affecting the processing of a processor by switching access priority to the cache memories between CPU and the system bus if need. CONSTITUTION: Usually, CPU possesses access priority on either the cache memory 21 or 22, and the system bus 5 possesses access priority on the other memory. Access priority is switched in accordance with a request from CPU. When CPU possesses access priority on the cache memory 21, for example, a bus from CPU is logically connected to an access control circuit 211 in the cache memory 21 by a selection means 41 based on a selection control signal 43 from a selection control circuit, and the system bus 5 is logically connected to the access control circuit 221 of the cache memory 22 by a selection means 42.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control method, and more particularly to a cache memory control method for controlling a cache memory provided in an information processing device or the like.

[0002]

2. Description of the Related Art An information processing apparatus having a conventional cache memory has a structure as shown in FIG. 4 (for example, Japanese Patent Laid-Open No. 3-225540). In the figure, 82 is a cache memory for temporarily storing the contents of the main memory 85 divided into blocks, and 81 is for writing / reading to / from the main memory 85 via the data buffer 88 and the system bus 83. At the same time, a processor that performs writing / reading to / from the cache memory 82 at high speed, and 84 is a DMA independent of the processor 81.
The main memory 8 via the system bus 83 by the transfer operation
5 is a DMA control device for writing / reading to / from the memory.

Reference numeral 86 is a comparison register for comparing the block number of the invalidated block with the write address to the main memory 85 output to the system bus 83, and for outputting the invalidation processing request signal 91 in accordance with the match. A control unit 87 outputs the bus release request signal 92 and the gate signal 93 in response to the invalidation processing request signal 91, and invalidates the contents of the cache memory 82 in block units by the cache memory control signal 94.

Normally, the cache memory 82 stores a copy of the contents of a predetermined block of the main memory device 85. When a read request is issued from the processor 81 to the main memory device 85, the contents corresponding to the request are stored. When stored in the cache memory 82, a faster memory access is realized by reading from the cache memory 82 that stores the same contents as the main storage device 85.

Therefore, the contents of the main memory 85 and the cache memory 82 must always be kept the same, and the DMA controller 84 or the like writes the contents in the main memory 85 independently of the processor 81. However, if the same portion as the portion where the write operation is performed is stored in the cache memory 82, that content is invalidated. It is necessary to refuse the reading from the processor 81 until the contents are updated.

The invalidation process for the cache memory 82 will be described below. First, when the DMA transfer operation issued from the DMA controller 84 to the system bus 83 is a write operation to the main memory device 85, the block number of the block stored in the cache memory 82 and the main memory device. The write address to 85 is compared in the comparison register 86. Here, when the two match, the invalidation request signal 91 is output from the comparison register 86 to the control unit 87.

In response to this, the bus release request signal 92 is output from the control section 87 to the processor 81, the gate signal 93 is output to the data buffer 88, and the system bus 83 is released from the processor 81.
The operation of the processor 81 is temporarily stopped. At the same time, the control unit 87 outputs the cache memory control signal 94 to the cache memory 82, and the corresponding block in the cache memory 82 is invalidated.

After the invalidation is completed, the bus release signal 92 and the gate signal 93 are stopped, and the operation of the processor 81 is restarted. As a result, the content corresponding to the address written by the DMA controller 84 is invalidated in the cache memory 82, and when the processor 81 subsequently issues a read request to the block, The reading from the cache memory 82 is rejected, the new contents are read from the main storage device 85, and the new contents are written to the cache memory 82.

[0009]

Therefore, in such a cache memory control method in the conventional information processing apparatus, the invalidation process is performed on the cache memory 82 after the processor 81 is stopped. Therefore, there is a problem that the processing by the processor 81 is reduced. In particular, in recent years, the data transfer capacity of the system bus and external devices has dramatically increased due to the improvement of the processing capacity, and the frequency of occurrence of writing to the main storage device 85 on the system bus has become an enormous value. In the conventional method, the invalidation process occurs every time a write occurs, and the processor 81 stops, so that there is a problem that the processing drop of the processor 81 becomes remarkable.

Further, in a device that performs transaction processing, the main task is to process transactions that come in from outside, so according to the conventional method, related transactions are sequentially input to the main storage device 85. The cache contents used for the processing of the processor 81 are invalidated by the series of information described above, and the hit rate to the cache memory 82 is reduced, and the processing capacity of the entire device is reduced. The present invention is intended to solve such a problem, and to provide a cache memory control method capable of reflecting a change in the content of the main storage device in the cache memory without affecting the processing of the processor. Has an aim.

[0011]

In order to achieve such an object, a cache memory control method according to the present invention comprises:
First and second cache memories for temporarily storing the contents of the main storage device are provided in parallel between the CPU and the system bus, and an access request to the main storage device is issued by the CPU.
If the write request to the main memory occurs on the system bus, the system bus accesses the first cache memory having the access priority. Updating the contents stored in the second cache memory having priority,
The priority of access to both cache memories is switched between the CPU and the system bus as needed.

When a write request to the first cache memory is output from the CPU, the storage content of the first cache memory is updated based on the request and the storage content of the second cache memory is updated. Is to be updated. If the data requested by the read request from the CPU to the first cache memory is not stored in the first cache memory, the requested data is read from the main storage device and the first data is read.
And the requested data is stored in the second cache memory. Further, when the access priority to the cache memory is switched, the contents of the second cache memory are copied to the first cache memory.

Further, flags are provided for storing the presence / absence of updating of the contents stored in the first and second cache memories in predetermined units, respectively, and respond to a write request to the main storage device generated on the system bus. Then, when the second cache memory is updated, the corresponding flag is set to “updated”, and when the access priority to the cache memory is switched, the flag in the contents of the second cache memory is set. Only the information indicating that there is an update is copied to the first cache memory. Furthermore, the CPU accesses the cache memory by alternately performing address output and data input / output, and when the access priority to the cache memory is switched, the address for the second cache memory is given by the CPU. The contents of the second cache memory are read out and copied to the first cache memory by alternately performing predetermined address output and data input while output or data input / output is not executed. Is.

[0014]

Therefore, when an access request to the main storage device is made in the CPU, the first cache memory is accessed by the CPU, and when a write request to the main storage device is made on the system bus, The storage contents of the second cache memory are updated based on the request, and the access priority to both cache memories is switched between the CPU and the system bus as needed. Further, when the access priority to the cache memory is switched, the contents of the second cache memory are copied to the first cache memory.

[0015]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an information processing device using a cache memory control method according to an embodiment of the present invention. In FIG. 1, the contents 21 and 22 of a main memory 6 are temporarily stored in block units. Cache memory (first and second storage means), 1 is cache memory 21, 22
CPU that operates by accessing
Bus consisting of address and data from U1, 4
Reference numeral 1 is a selection unit that controls the logical connection state of the bus 11 to the cache memories 21 and 22, and 42 is a selection unit that controls the logical connection state of the system bus 5 to the cache memories 21 and 22.

A selection control means 40 controls the selection means 41, 42 by outputting a selection control signal 43 in response to the cache switching signal 12 from the CPU 1, and 3 is a C
When writing data from the PU 1 to the cache memory 21 or 22, the same data is copied to the other cache memory 22 or 21 and the cache memory 2
Copying means for copying data between the cache memories 21 and 22 at the time of switching between 1 and 22. Reference numeral 7 denotes a main bus via the system bus 5 by sending a write / read request independent of the CPU 1 onto the system bus 5. It is a peripheral device that accesses the storage device 6.

Further, FIG. 2 shows the cache memories 21 and 22.
FIG. 3 is a block diagram showing the details of the vicinity, and in the cache memories 21 and 22, 212 and 222 are data memories in which the same contents as the main storage device 6 are stored in block units and which are accessed at high speed from the CPU 1, and 213 and 223 are memories. Write flags that store in block units whether or not the contents stored therein are updated independently of the CPU 1, and access controls 211 and 221 that control access to the data memories 212 and 222 and write flags 213 and 223. Circuit.

In the copy means 3, 34 is a write control circuit that transfers the address and data to the write buffer 35 in response to a write request from the CPU 1 via the bus 11, and 33 is a data copy operation between the cache memories 21 and 22. A read control circuit for outputting a predetermined read request at times, 31, 32 are cache memories 21, 2.
2 access buses 37, 38 and read control circuit 33
A selector 36 for controlling a logical connection state with the write buffer 35 controls each selector 31, 32 according to a selection control signal 43 from a selection control means 40, and a read control circuit 3 by a data copy signal 39.
3 is a direction control circuit for outputting a copy instruction to the device 3.

Next, the operation of the present invention will be described with reference to FIG. Normally, the CPU 1 has the cache memories 21, 22.
, And the system bus 5 has the access priority to the other, and these access priorities are switched according to the request from the CPU 1. For example, when the CPU 1 has the access priority to the cache memory 21, the CP is determined based on the selection control signal 43 from the selection control circuit 40.
The bus 11 from U1 is logically connected to the access control circuit 211 of the cache memory 21 by the selection means 41, and the system bus 5 is logically connected to the access control circuit 221 of the cache memory 22 by the selection means 42.

As a result, the cache memory 21 is accessed in response to a memory access request, that is, a write / read request, to the main storage device 6 generated in the CPU 1. Now, when a read request is generated in the CPU 1, it is transferred to the access control circuit 211 via the bus 11 and the selection means 41, and when the request is hit, that is, the requested data is stored in the data memory 212. If so, desired data is read from the data memory 212 and transferred to the CPU 1 via the selection means 41 and the bus 11.

When a write request is generated in the CPU 1, it is transferred to the access control circuit 211 via the bus 11 and the selection means 41, and when the request hits, the data memory 212 is requested. Data is written. At the same time, a write request from the CPU 1 is detected by the write control circuit 34, and the address and data are transferred to the write buffer 35. Here, the direction control circuit 36 controls the selector 32 according to the selection control signal 43 to connect the write buffer 35 to the access control circuit 221.

As a result, the data memory 222 is accessed based on the address and the data stored in the write buffer 35 via the selector 32 and the access control circuit 221. Therefore, CPU1
In response to a write request from the cache memory 21, the same data as the data written in the data memory 212 of the cache memory 21 is written in the data memory 222 of the cache memory 22 via the copy means 3, so that the contents of the two are identical. Retained.

When the read request from the CPU 1 does not hit, that is, when the requested data is not stored in the data memory 212, a predetermined control means (not shown) in the cache memory 21. Due to
Desired data is transferred from the main storage device 6 to the data memory 212 via the system bus 5, the selection means 42 and the access control circuit 211. At the same time, the desired data is transferred from the selection means 42 to the data memory 222 via the access control circuit 221, and the identities of both are maintained.

Next, by a write request generated on the system bus 5 independently of the CPU 1 such as DMA transfer,
A case where the content of the main storage device 6 is changed will be described. When a write request to the main memory device 6 is sent from the peripheral device 7 to the system bus 5, the access control circuit for which the address and data of this request are given access priority to the system bus 5 via the selecting means 42. 221 is input. Here, if this request is hit, that is, if the requested data is stored in the data memory 222, the data memory 22 is based on this request.
The data in 2 is updated.

This is the same when the write request from the CPU 1 is not hit and the write request for the main memory device 6 is output from the cache memory 21 onto the system bus 5. The detected data from the cache memory 21 is transferred to the system bus 5, the selection means 42 and the access control circuit 2.
Data memory 22 of cache memory 22 via 21
Written to 2. Therefore, when a write request to the main memory device 6 occurs on the system bus 5,
The request is detected, and the changed contents are reflected in the cache memory 22 to which the system bus 5 has the access priority.

Next, the switching operation of the cache memories 21 and 22 will be described. The CPU 1 outputs the cache switching signal 12 to the selection control means 40 as needed. The switching of the cache memory is requested by the CPU 1 on the basis of the occurrence of the difference between the contents of the cache memories 21 and 22 as a criterion, and, for example, as described above, the main memory device transmitted to the system bus 5. When a write request for 6 hits in the cache memory 22, or the cache memory 22 accompanying this hit
It is implemented according to the end of data transfer to the.

In response to the cache switching signal 12, the selection control signal 43 is output from the selection control means 40, and CP
The bus 11 from U1 is logically connected to the access control circuit 221 of the cache memory 22 by the selection means 41, and the system bus 5 is logically connected to the access control circuit 211 of the cache memory 21 by the selection means 42. As a result, the CPU 1 has the access priority of the cache memory 22 and the system bus 5 has the access priority of the cache memory 21.

The selection control signal 43 is sent to the copy means 3
Is also input to the direction control circuit 36 of
6, the read control circuit 33 is connected to the access control circuit 221 of the cache memory 22 via the selector 32 and the access bus 38, and the write buffer 35 is connected.
Are connected to the access control circuit 211 of the cache memory 21 via the selector 31 and the access bus 37. Further, the read control circuit 3 is read from the direction control circuit 36.
The data copy signal 39 is output for the signal No. 3.

In response to this, a read request is output from the read control circuit 33 to the cache memory 22, and the contents of the data memory 222 are read for each block during the period when there is no access from the CPU 1.
It is transferred to the write buffer 35 via the write control circuit 34. Further, a write request is output from the write buffer 35 to the cache memory 21,
It is written in the data memory 212 via the selector 31, the access bus 37 and the access control circuit 211.

In this way, via the copying means 3,
The content of the cache memory 22 is the cache memory 21.
Then, the data is sequentially copied, and the identities of both cache memories 21 and 22 are maintained. When reading the data in the data memory 222, the write flag 223 indicating whether or not the data is updated is referred to, and only the write flag 223 indicating that the data is updated may be transferred to the cache memory 21. Of course, this makes it possible to omit unnecessary transfer data and shorten the transfer processing time. After transfer, the corresponding write flag 223 is set to no update.

As the CPU 1, a memory access type which outputs an address and data in two cycles is used, and pipeline control for reading data from the data memory 222 is executed during the unused period of the address bus and the data bus. It may be done. 3A and 3B are explanatory diagrams showing pipeline control. FIG. 3A is a schematic block diagram and FIG. 3B is a timing chart. In the figure, 1 is a CPU, 22 is a cache memory, 15 is an address bus, 16 is a data bus, 17 is a tag bus, and A1.
1, A12, A31 are addresses, D11, D12, D3
1 is data, and T11, T12, and T31 are tags.

The tag means the cache memory 21,
The table of contents information of the contents held in 22, for example,
The upper few bits of the address are assigned. By updating and holding this tag together with the data and referring to it in response to an access, a faster hit determination is performed. In the cycle C1 of FIG. 3B, the address A11 to be accessed is first output from the CPU 1 onto the address bus 15.

In the subsequent cycle C2, the address A11 from the CPU 1 is stopped and the data D11 and the tag T11 are output to the data bus 16 and the tag bus 17, respectively. The cache memory 22 holds the address A11 output in the cycle C1 and writes the data D11 and the tag T11 output in the cycle C2 to the storage location specified by the address A11.

Here, according to this two-cycle system, the data bus 16 and the tag bus 17 are included in the cycle C1.
Is not used, and the address bus 15 is not used in the cycle C2, the contents of the cache memory 22 can be read from the read control circuit 33 by utilizing this unused period. In the actual pipeline control, the address A31 for reading is output onto the data bus 16 in the cycle C2, and the data bus 16 and the tag bus 1 are output in the next cycle C3.
The data D31 and the tag T31 read in 7 are output.

By performing the pipeline control in this way, it becomes possible to read the data to be copied from the cache memory 22 by the read control circuit 33 in parallel with the access from the CPU 1 to the cache memory 22. It is possible to secure the identity of the contents of the cache memories 21 and 22 in a short time without stopping the access.

[0036]

As described above, the present invention provides a CPU
And a system bus, first and second cache memories for temporarily storing the contents of the main memory are provided in parallel, and when a write request to the main memory occurs on the system bus, Based on the request, the system bus updates the stored contents of the second cache memory having the access priority, and the access priority to both cache memories is switched between the CPU and the system bus as necessary. It is possible to reflect changes in the contents of the main storage device in the cache memory without stopping the operation of the CPU. Further, when the CPU outputs a write request to the first cache memory, the storage contents of the first and second cache memories are updated based on the request, so the write request from the CPU In contrast, the contents of both cache memories are kept the same, and the process of copying the contents of the first cache memory to the second cache memory at the time of switching the cache memories can be omitted, and the process for keeping the same after the switching can be omitted. Can be reduced.

If the data requested by the read request from the CPU to the first cache memory is not stored in the first cache memory, the requested data is read from the main storage device and the first data is read. Since the contents are stored in the second cache memory and the second cache memory, the contents of both cache memories are kept the same with respect to the data read from the main memory, and the contents of the first cache memory are preserved when the cache memories are switched. The process of copying to the second cache memory can be omitted, and the process for maintaining the identity after switching can be reduced. Also,
When the access priority to the cache memory is switched, the contents of the second cache memory are copied to the first cache memory. Compared to the case of copying from the main storage device to the first cache memory, it is possible to maintain the identity of both cache memories without occupying the system bus.

Further, a flag for storing whether or not the contents stored in the first and second cache memories are updated in a predetermined unit is provided to respond to a write request to the main storage device generated on the system bus. Then, when the second cache memory is updated, the corresponding flag is set to “updated”, and when the access priority to the cache memory is switched, the flag in the contents of the second cache memory is set. Since only the information indicating that there is an update is copied to the first cache memory, the amount of data to be copied between both cache memories is reduced, and the processing time for maintaining the sameness can be shortened. Furthermore, when the cache memory is accessed by the CPU alternately performing address output and data input / output, and when the access priority to the cache memory is switched, the address of the second cache memory by the CPU is changed. Since the contents of the second cache memory are read out and copied to the first cache memory by alternately performing predetermined address output and data input while output or data input / output is not executed. , It is possible to carry out the processing for maintaining the identity regardless of the access operation by the CPU, and it is possible to further shorten the processing time.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus using a cache memory control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a main part of FIG.

FIG. 3 is an explanatory diagram showing pipeline control.

FIG. 4 is a block diagram of an information processing apparatus using a conventional cache memory control method.

[Explanation of Codes] 1 ... CPU, 11 ... Bus, 12 ... Cache switching signal 21, 22 ... Cache memory, 3 ... Copying means,
40 ... Selection control means, 41, 42 ... Selection means, 43 ... Selection control signal, 5 ... System bus, 6 ... Main storage device, 7 ...
Peripherals.

Claims (6)

[Claims] 1. A cache memory for temporarily storing the contents of the main storage device is provided between a system bus to which the main storage device is connected and a CPU. By accessing this cache memory, the CPU can perform various operations. In an information processing device in which processing is performed, first and second cache memories that temporarily store the contents of the main storage device are provided in parallel between a CPU and a system bus, and an access request to the main storage device is issued. Occurs in the CPU, the CPU accesses the first cache memory having the access priority, and when a write request to the main memory occurs on the system bus, the system bus is based on the request. Updates the contents stored in the second cache memory that has access priority, and accesses both cache memories as necessary. Cache memory control method characterized in that the above rights to switch between CPU and system bus. 2. The cache memory control method according to claim 1, wherein when a write request to the first cache memory is output from the CPU, the storage content of the first cache memory is updated based on the request. In addition, the cache memory control method is characterized in that the storage content of the second cache memory is updated. 3. The cache memory control method according to claim 1, wherein when the data requested by the read request from the CPU to the first cache memory is not stored in the first cache memory, the main memory A cache memory control method comprising: reading the requested data from a device and storing the requested data in a first cache memory, and storing the requested data in a second cache memory. 4. The cache memory control method according to claim 1, wherein the contents of the second cache memory are copied to the first cache memory when the access priority to the cache memory is switched. And a cache memory control method. 5. The cache memory control method according to claim 4, further comprising a flag for storing whether or not the contents stored in the first and second cache memories are updated in a predetermined unit, respectively, on the system bus. When the second cache memory is updated in response to the write request to the main memory that occurs in step 1, the corresponding flag is set to update, and when the access priority to the cache memory is switched, A cache memory control method, wherein only the information indicating that the flag has been updated is copied to the first cache memory among the contents of the second cache memory. 6. The cache memory control method according to claim 4, wherein the CPU accesses the cache memory by alternately performing address output and data input / output, and the access priority to the cache memory is switched. In addition, the contents of the second cache memory are read by alternately performing a predetermined address output and data input while the address output or the data input / output by the CPU is not executed with respect to the second cache memory. , A cache memory control method, wherein copying is performed in a first cache memory.