JPS6022376B2 - Cache memory control device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a cache memory control device.

Generally, in an information processing device, in order to improve its processing speed, some of the information stored in the main memory is temporarily stored between the central processing unit (hereinafter referred to as CPU) and the main memory. , which replaces main memory and is faster than the CPU
It is equipped with a cache memory that exchanges information between the computer and the computer. The cache memory is divided into a plurality of sections called selectors, and each sector is further divided into blocks each consisting of a plurality of words. When the CPU specifies a memory address and requests necessary information from the cache memory IJ', the cache memory control circuit checks whether the data at the specified address currently exists validly in the cache memory. If it exists validly (hit), this data is sent to the CPU.
If it does not exist validly (in case of a cache miss), the block containing the data at the specified address is transferred from the main memory to the cache memory and stored (in this case). A cache storage address is an address that ignores the upper digits and is determined only by the lower digits necessary to specify the address in the cache.Therefore, if the contents of the lower digits are the same, until then it is stored at this address in the cache. The old data that had been stored is rewritten for this new data and created from the cache), and the data at the specified address is supplied to the CPU. In this way, from now on the same data (or data belonging to the same block as this data)
When a request is made by the CPU, preparations are made to respond to the request at high speed. As is clear from the above, in order to use the limited cache memory capacity as effectively as possible, it is necessary to make the cache hit probability as high as possible.

Furthermore, in the cache memory control circuit, since the cache memory is accessed only after determining a cache hit/no-miss hit, it is also necessary to shorten the time in the hit/miss hit determination circuit (improving throughput). For this purpose, the cache memory is divided into instruction-only cache memory and operand-only cache memory, and when a request from the CPU is for issuing an instruction, a request is sent to the instruction cache memory control circuit, and the cache memory is for issuing an instruction. A conventionally known method is to issue a request to the operand cache memory control circuit when the request is issued. On the other hand, in order to improve the processing speed of an information processing device, a pipeline processing method that performs advance control is known.

This method is as follows. Each instruction, for example, A
, P, C, 8 and W. In step A, the instruction is decoded and the address of the operand used in the instruction is calculated (the address of the operand that is indirectly specified or indexed is calculated). Step P converts the logical address into a real address (programs are generally written using logical addresses). In step C, an operand is proposed. If this instruction includes an operand to be retrieved from the memory address, issue a cache memory IJ' request using the real address obtained in step P, and retrieve the data (operand) to be combined as described above. ) is stored in the operand register of the arithmetic circuit. In step E, the operation specified by this instruction is performed using the operand. Then, in step W, the result thus obtained is stored in the location specified by this instruction (for example, a general-purpose register or memory address). In this case, if the specified storage location is a certain memory address, a storage request is issued to the cache memory control circuit, and if the data at the specified memory address is validly present in the cache. If so, the data is rewritten and updated. At the same time, it issues a storage request to the main memory and updates the contents of this memory address. On the other hand, the above A, P, C
, E, and W, separate hardware is provided for processing each step.

Instead of processing each instruction by completing all five steps of one instruction before proceeding to the processing of the next instruction, as shown in Figure 1, the steps are shifted one by one. By processing consecutive instructions in parallel, the idle time of each piece of hardware is eliminated and processing speed is improved. Now, in the above explanation, it is assumed that instruction 13 in FIG. 1 is an instruction that stores an operation result at a certain memory address, and instruction 15 is an instruction that reads an operand from a certain memory address. Then, step W of instruction 13 and step C of instruction 15 overlap in time, but the former is a process of accessing the cache and storing data in the cache, and the latter is a process of accessing the cache and storing data from the cache. Since it is a process of reading data, the two conflict and cannot be executed simultaneously in the same period.

Therefore, conventionally, when such a situation occurs, storage in the cache is generally performed with priority (that is, step W of instruction 13 is performed with priority), and after that is completed, reading from the cache is performed. . Therefore, when such a combination of instructions occurs, the flow of the pipeline is disturbed as shown in FIG. 2, resulting in a corresponding decrease in processing efficiency. On the other hand, in some cases, step W of an instruction that does not write to a memory address (for example, an instruction that writes a result to a general-purpose register) and an instruction that does not read from a memory address (for example, only the contents of a general-purpose register are used as an operand). There is also a possibility that step C of the command used) overlaps in the same period. During this period, the above memory access will not be performed at all,
This is the idle period of the corresponding hardware. For example, in FIG. 2, instructions step C and step W that do not perform memory access are shown in brackets, but instruction 1, step W, and step C of the instructions do not perform memory access. , this period becomes the idle period of the corresponding hardware. The following can be considered as a method for effectively utilizing this idle period to reduce the above-mentioned turbulence in the pipeline flow. In other words, if a first-in-first-out (FIFO) cache store address buffer circuit and a cache store data buffer circuit with appropriate depth are provided, and an instruction of the type described above that stores an operation result in a memory address appears. , the memory address and the corresponding stored data are temporarily stored in the cache store address buffer circuit and the cache store data buffer circuit, respectively, and the memory address and the corresponding stored data are temporarily stored in the cache store address buffer circuit and the cache store data buffer circuit, respectively. By using the idle time of the hardware that performs this to store data from the buffer circuit to a designated memory address, the above-mentioned disturbance in the pipeline flow can be reduced. However, in the pipeline system, as described above, the following problems occur because the operands of the subsequent instruction are prefetched before the preceding instruction is completed.

For example, suppose now that the preceding instruction is an instruction that stores the result of an operation at a memory address at a certain address X, and that the subsequent instruction that follows it is an instruction that uses the contents of the same address X as one of its operands. . In this case, it is necessary to read the operand from address X of the subsequent instruction after the storage of the operation result at address X by the preceding instruction is completed. Therefore, the above-mentioned method of storing temporary data using a buffer circuit and using the idle period to store it in a designated memory address cannot be used unconditionally by ignoring this fact. . In particular, as mentioned at the beginning, when the cache memory is used separately for instructions and operands in order to increase the cache hit rate, complex problems occur that cannot be solved by conventional devices. SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control device that eliminates such problems and exhibits the effects of inserting the buffer circuit. The control device of the present invention is a cache memory control device for an information processing device including a main storage device, a central processing unit, and a cache memory, and temporarily stores part of instruction information stored in the main storage device. However, instead of the main memory, there is an instruction cache memory that exchanges instruction information with the central processing unit, and a cache memory that temporarily stores part of the operand information stored in the main memory. an operand cache memory that exchanges operand information with the central processing unit in place of a storage device; and store address information and store data information in response to a store request from the central processing unit to the main storage device. a cache store buffer circuit that receives and temporarily stores the respective information, and generates a store request; and a cache store buffer circuit that receives and temporarily stores the instruction read request address information from the central processing unit and all address information temporarily stored in the cache store buffer circuit. an instruction address match detection circuit that generates instruction address match detection information when matching address information is detected; and an instruction address match detection circuit that generates instruction address match detection information when matching address information is detected; an operand address match detection circuit that compares all address information stored in the cache and generates operand address match detection information when matching address information is detected; and an operand address match detection circuit that generates operand address match detection information when matching address information is detected; Check whether the requested address exists in the memory, and if the requested address exists, read the instruction information of the requested address from the instruction cache memory; if the requested address does not exist, read the instruction information of the requested address from the main storage device. The instruction cache memory IJ' is controlled to be stored in the instruction cache memory, and in response to a store request from the cache store buffer circuit, the instruction cache memory IJ' checks whether or not the store address exists. Control is performed to store the store information from the store buffer circuit at the requested address of the instruction cache memory, and when the instruction address match detection information occurs, the store request from the cache store buffer circuit is processed with priority. an instruction cache memory control circuit that controls the operation of the operand cache memory; and in response to an operand offer request from the central processing unit, checks whether or not the requested address exists in the operand cache memory; The operand information of the requested address is read from the operand cache memory, and if there is no requested address, the operand information of the requested address is read from the main storage device and controlled to be stored in the operand cache memory, and the operand information from the cache store buffer circuit is controlled to be read. In response to a store request, it is checked whether or not the store address exists in the operand cache memory, and if the requested address exists, the store information from the store buffer circuit is stored at the requested address in the operand cache memory. and an operand cache memory control circuit that performs control so that a store request from the cache store buffer circuit is processed with priority when the operand address-atsushi detection information is generated.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram showing one embodiment of the present invention. Reference number 1 indicates a central processing unit (hereinafter referred to as CPU).

After calculating the operand address of a certain instruction, the CPU
outputs this operand address via operand address output line 2. The CPU also outputs control information via the line 2, and if this instruction is a type of instruction that stores the operation result in a certain memory address, the output operand address is stored in the operand address buffer circuit. 40 and instruction address buffer circuit 41 in parallel. Further, when the data of the calculation result to be stored in the memory addresses stored in the buffer circuits 40 and 41 is obtained, the CPU 1
outputs it along with control information via the store data output line 3, and the data is stored in the operand data buffer circuit 50 and the instruction data buffer circuit 51 in parallel. The buffer circuits 40, 41, 50 and 51 are first-in-first-out control (F1) all having the same depth.
In the buffer circuit "0", the circuits 40 and 41 and the circuits 50 and 51 have exactly the same configuration. The memory address and its corresponding data are:
Data stored in corresponding locations (same buffer address) of the buffer circuits 40, 41 and 50, 51 (i.e., data corresponding to a memory address stored in the circuit 40 is stored in a corresponding buffer address of the circuit 50,
Data corresponding to the (same) memory address stored in the circuit 41 is stored in the corresponding buffer address of the circuit 51. Exactly the same data is written to circuits 40 and 41 and circuits 50 and 51 at exactly the same time, but as will become clear later in the explanation, they are divided into separate buffer circuits in order to perform argumentation independently. ). Furthermore, all contents (the memory addresses) stored in said circuit 40 and circuit 41 are transmitted via address comparison lines 70 and 71 from respectively to address match detection circuit 60 for operands and address match for instructions. The signal is supplied to one input terminal of each of the detection circuits 61 . The other input of the operand match detection circuit 60 is supplied with a memory address when the CPUI issues a read request for reading an operand from a memory address, and thus a memory address is supplied to the operand address buffer circuit 40. If any of the stored memory addresses and the read request memory address match, the detection circuit 6 provides a match detection signal to the operand cache memory control circuit 20.

Further, the other input of the instruction match detection circuit 61 is supplied with the memory address of the instruction to be read when the CPUI issues a request to read the instruction from the memory address. If it matches any memory address stored in the instruction cache memory control circuit 21, the detection circuit 61 provides a match detection signal to the instruction cache memory control circuit 21. The circuits 20 and 2 when these coincidence detection signals are applied
The operation in step 1 will be described later, but first, the operation in the absence of these coincidence detection signals will be explained.
Now, the storage request information and its output from the address buffer circuits 40 and 41 are transmitted to the operand cache memory control circuit 20 and the instruction cache memory control circuit through the address buffer output lines 80 and 81, respectively. 21.

Thus, as mentioned above, when an instruction appears that stores the result of an operation at a memory address,
At the appropriate step of the instruction, the memory address is stored in the buffer circuits 40 and 41, and the data of the operation result is stored in the circuits 50 and 51, respectively, without delay, so that the memory address is stored without delay in the buffer circuits 40 and 41, and the data of the operation result is stored in the circuits 50 and 51, respectively. Disturbances in the pipeline flow caused by memory access conflicts can be avoided. When the contents are thus stored in the circuits 40, 41, 50 and 51, the circuits 40 and 41 supply storage request information to the respective control circuits 20 and 21 via the respective output lines 80 and 81. do. On the other hand, the circuit 20 outputs CP via the output line 2.
When a request to read an operand of a certain instruction is received from the UI, and there is no coincidence detection signal at that time, this read request is received with priority over the storage request from the circuit 40 (the buffer circuits 40 and 50 , Since the data to be stored is temporarily stored, it is possible to suspend storage requests and receive proposals with priority, thus avoiding the disruption of the pipeline flow as described above. be able to). When the read request is accepted in this way, the circuit 20 reads the data at the memory address supplied via the line 2 from the operand cache memory 30 and supplies it to the CPUI (at this time, the specified memory address is 30, the circuit 20 reads the block containing the data at the memory address from the main memory 4 and stores it in the cache memory 30, and at the same time, the circuit 20 reads the block containing the data at the specified memory address from the CPU 30. ). If there is no request for the table from the CPUI and there is a request for storage from the circuit 40, the circuit 20 accepts the storage request and stores the data specified by the address data read out via the line 80. At the memory address of the cache memory 30,
One piece of data stored in the circuit 5 corresponding to this address data is read out and stored. At this time,
If this memory address is not validly present in the cache memory 30, these data only need to be read from the buffer circuits 40 and 50. This is due to the following reasons. That is, although not particularly illustrated, a third address buffer circuit having the same depth as the address buffer circuits 40, 41 and the data buffer circuits 50, 51 and into which exactly the same contents are written, and third data. A buffer circuit is provided separately, and in addition to the data to be stored at the memory address, it is completely independent of the storage process in the cache memory (operand cache memory 30 and instruction cache memory 31) that is currently being explained. Storage processing in the main storage device 4 is performed separately.

That is, the data temporarily stored in the circuits 40, 41 and 50, 51 is originally data to be written to a designated memory address of the main storage device 4, and is stored in the third address buffer circuit and the third address buffer circuit described above. The data buffer circuit No. 3 is a buffer that temporarily stores the data in order to store the data in the main storage device 4 by utilizing the free time of access from the storage circuit to the main storage device 4. . In this way, a separate independent route is provided for storage in the main storage device 4, so
If there is no valid memory address to be stored in the cache memory 30, there is no need to perform any special processing on this address. Now, exactly the same type of processing as that for the operand cache memory 301 described above is performed for the instruction cache memory 31.

That is, when the instruction address buffer circuit 41 has data, it provides a storage request to the instruction cache memory control circuit 21 via the buffer output line 81. The circuit 21, on the other hand,
An instruction read request is received from the CPU via the instruction read request line 5. If this request is accepted and there is no match detection signal from the circuit 61, the circuit 21 reads out the contents of the memory address specified in the line 5 from the instruction cache memory 31 and sends it to the CP.
(At this time, if the data at the specified memory address does not exist effectively in the cache memo IJ31, it is read from the main storage device 4 and supplied to the UI. 30). When there is no instruction read request from the CPUI and there is a storage request from the circuit 41, the circuit 21 reads a memory address to be stored from the circuit 41, and if the memory address is stored in the instruction cache memory 31, If the data exists in the memory address effectively, the data at the memory address is rewritten by using the data read out from the instruction data buffer circuit 51. However, if the memory address to be stored does not exist effectively in the cache memory 31, only one piece of the corresponding data in the buffer circuits 41 and 51 is read and discarded. Now, the above is the operation when there is no coincidence detection signal from the address coincidence detection circuits 60 and 61, but when there is any coincidence detection signal, the operation is as follows.

Now, if there is an operand request from the CPU 1 as described above, and the memory address of the operand matches certain data (address) stored in the operand address buffer circuit 40, then the operand The operand match detection circuit 60 provides a match detection signal to the operand cache memory control circuit 2.

Upon receiving this, the circuit 20 receives the storage request from the circuit 40 with priority, and corresponds the address stored in the circuit 40 up to the address where the match occurred and the address stored in the circuit 50. sequentially (F
(IFO control) and stores the latter data in the memory address specified by the former. In this case, if a specified memory address does not exist validly in the cache memory 30, it is only necessary to read out the data corresponding to that memory address as described above. After processing the storage request up to the memory address where the match occurred, the circuit 20 accepts the read request from the CPUI. By controlling in this manner, when a preceding instruction updates a certain memory address in the operand cache memory 30 and a subsequent instruction uses data at that memory address as an operand, the operand is not prefetched or Regardless of operations such as temporary suspension of data to be stored, subsequent instructions always use the data updated by the preceding instruction as operands, so no malfunction occurs. The processing for the operand cache memory 30 described above is performed in exactly the same way for the instruction cache memory 31. That is, when the CPU makes an instruction read request via the instruction read request line 5, and the specified memory address from which this instruction is to be read matches any data stored in the instruction address buffer circuit 41. In this case, the instruction address coincidence detection circuit 61 provides a coincidence detection signal to the instruction cache memory control circuit 21.
Upon receiving this, the circuit 21 receives the storage request from the circuit 41 with priority, and corresponds the address stored in the circuit 41 up to the address where the match occurred and the address stored in the circuit 51. sequentially (F
(by IFO control), instruction cache memory 31
The latter data is stored in the memory address specified by the former. In this case, if a specified memory address does not exist validly in the cache memory 31, only the data corresponding to that memory address can be read as described above. After processing the storage request from the circuit 41 up to the memory address where the match occurred, the circuit 21 accepts an instruction issuing request from the CPUI. By controlling in this way,
Immediately after an instruction to update a memory address in the instruction cache memory 31, when the CPU reads data (instruction) at the memory address as an instruction,
Even though there is a process of storing the instruction in the cache memory 31), the instruction updated by the preceding instruction is always read out from the instruction cache memory 31 and supplied to the CPU, resulting in malfunction. It never happens. In the embodiment described above, the operand address buffer circuit 40 and the instruction address buffer circuit 41
Furthermore, the third address buffer circuit for the main memory device was made into a separate buffer circuit, but
It is also possible to combine these into one buffer circuit by using a buffer circuit capable of (ead) and by slightly changing the control method.

Further, the operand data buffer circuit 50, the instruction data buffer circuit 51, and the third data buffer circuit for the main memory device can also be combined into one buffer circuit in exactly the same manner. Further, in the above embodiment, when a match is detected by the match detection circuit 60 or 61, data up to the address corresponding to the address where the match was detected is given priority over other data and stored in the cache memory 30 in the FIFO.
Or, instead of this, it is also possible to control so that only the data at the address where a match occurs is written in the cache memo 31 with priority over others.

Controlling in this manner generally improves processing speed, although the configuration becomes more complex. As described above, by using the present invention, an information processing system having a CPU that is equipped with operand cache memory and instruction cache memory separately, increases the cache hit rate and throughput, and performs pipelined advance control. It is possible to provide a cache memory control device that improves time loss due to disturbances in the pipeline flow of the device and solves problems caused by preemption of operands or instructions by advance control.

This has the effect of improving the processing efficiency of the information processing device.

[Brief explanation of the drawing]

FIGS. 1 and 2 are diagrams for explaining pipeline processing, and FIG. 3 is a diagram showing an embodiment of the present invention. In FIG. 3, 1... central processing unit (CPU), 2... operand address output line, 3... store data output line, 4...
...Main storage device, 5...Instruction issue request line, 20...Operand cache memory control circuit, 21...Instruction cache memory, 30
... Operand cache memory, 31...
... Instruction cache memory, 40... Operand address buffer circuit, 41... Instruction address buffer circuit, 50... Operand data buffer circuit, 51... Instruction data buffer circuit,
60... Operand address match detection circuit,
61... Instruction address match detection circuit, 70.
...Address comparison line for operand, 71...
...Address comparison line for instruction, 80...Address buffer output line for operand, 81...Address buffer output line groove for instruction Fig. 2 Fig. 3

Claims (1)

[Claims] 1. In a cache memory control device for an information processing device including a main memory, a central processing unit, and a cache memory, a part of instruction information stored in the main memory is temporarily stored in the main memory. an instruction cache memory that exchanges instruction information with the central processing unit instead of the main storage device; and an instruction cache memory that temporarily stores part of the operand information stored in the main storage device Instead, an operand cache memory exchanges operand information with the central processing unit, and stores address information and store data information in response to a store request from the central processing unit to the main storage unit. a cache buffer circuit that receives, temporarily stores, and generates a store request; address information for instruction read requests from the central processing unit; and all address information temporarily stored in the cache buffer circuit. an instruction address match detection circuit that compares the address information and generates instruction address match detection information when matching address information is detected; an operand address match detection circuit that compares all stored address information and generates operand address match detection information when matching address information is detected; and an operand address match detection circuit that generates operand address match detection information when matching address information is detected; Checks whether the requested address exists in the instruction cache memory, and if the requested address exists, reads the instruction information of the requested address from the instruction cache memory. If the requested address does not exist, reads the requested address from the main memory. Controls reading of instruction information and storing it in the instruction cache memory, and checks whether the store address exists in the instruction cache memory in response to a store request from the cache buffer circuit. If there is a requested address, the store information from the store buffer circuit is controlled to be stored at the requested address of the cache memory for the instruction, and if the instruction address match detection information is generated, the store information is stored from the cache memory from the cache memory for the instruction. an instruction cache memory control circuit that controls to give priority to processing of store requests; and a control circuit that controls whether or not the requested address exists in the operand cache memory in response to an operand read request from the central processing unit. If there is a requested address, the operand information of the requested address is read from the cache memory for the operand. If there is no requested address, the operand information of the requested address is read from the main storage device and stored in the cache memory for the operand. In response to a store request from the cache buffer circuit, it is checked whether the store address exists in the operand cache memory, and if the requested address is present, the store information from the store buffer circuit is stored. is controlled to be stored at the requested address of the cache memory for the operand, and when the operand address match detection information is generated, the store request from the cache buffer circuit is controlled to be processed with priority. 1. A cache memory control device comprising: an operand cache memory control circuit.