JP2703255B2 - Cache memory writing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a cache memory writing device provided between a processor of a computer and a main storage unit to enable high-speed access.

(Prior art) The central processing unit of the computer is the research of the architecture, VL
With the development of SI technology, both performance and speed have been greatly improved. In order to utilize the speed of the microprocessor, it is desired to improve the access speed of the external storage unit. Generally, it is desirable that the storage unit has a high speed and a large capacity. However, a high-speed memory (static memory) is expensive and has a low capacity, and a large-capacity dynamic memory has a low speed. Therefore, the storage unit is divided into two layers, a large-capacity low-speed main memory and a small-capacity high-speed buffer storage are combined, and the latter is arranged between the former and the central processing unit, and the data with high access frequency is stored in the latter. By storing the data in the buffer storage unit, the access speed of the whole storage unit is apparently improved. This buffer storage unit is generally called a cache memory. There is a hit detection unit as an element for realizing a cache memory. This is to determine whether the data at the address accessed by the central processing unit (hereinafter referred to as a processor) is stored in the cache memory. If the data is stored, hit information is output. I do. For the detection of hits and misses, another storage unit generally called a tag memory is used. The tag memory stores the address of the contents of the data memory (hereinafter, data memory) of the cache on the main memory. The hit detection unit compares the address output from the processor with the address in the tag memory to determine a match (hit) or a mismatch (miss).

That is, the time required for reading the tag memory and the time required for the comparator are required for hit detection, and the time required for the comparator is longer than the time required for accessing the data memory. Therefore, conventionally, regarding the data read of the processor, a method has been adopted in which the contents of the cache data memory are sent to the processor regardless of the hit / miss, and hit / miss information is notified in the next cycle. However,
Regarding the data write of the processor in the copy-back type cache memory, a write permission cannot be issued to the data portion unless hit / miss detection is performed. In the copy-back cache, a write operation at the time of a cache hit is executed only for the cache and is not reflected in the main memory. Reflection to the main memory is mainly when a data entry in the cache is replaced by data at another address. Therefore, if a cache miss occurs during a write operation, if the contents of the cache have been rewritten earlier and inconsistent with the contents of main memory, temporarily transfer them to the evacuation memory. , The original write operation must be performed. (The saved data is thereafter written back to the main memory.) For such a reason, in a cache memory that uses a method of notifying the processor of hit / miss information in the next cycle, the write operation takes at least two cycles. (Hit detection + write operation).

FIG. 5 is a time chart showing a write operation according to the conventional method. Two cycles of process cycles 0 and 1 are write operations at the time of a cache hit. Cycle 0
The address 0 and the write data 0 are output from the processor from the beginning of the sequence. In cycle 0, hit detection is first performed.

Therefore, the HIT / MISS signal after detection is valid from cycle 1. Therefore, the actual write operation is performed in cycle 1. In cycles 0 and 1, a write signal was output in cycle 1 because of a cache hit.
In No. 3, since a cache miss has occurred, no write signal is output in cycle 3.

The reason why the write signal cannot be output in processor cycle 0 is obvious, because the value of another address stored in the cache is destroyed in the event of a cache miss.

As described above, in the conventional method, the write operation is performed for 2 times.
Cycle required.

(Problems to be Solved by the Invention) As described above, when the hit detection is determined in the next cycle in the copy-back cache memory device, there is a problem that the write operation takes twice as long as the read operation. . In order to avoid this, it is only necessary to speed up the hit detection unit and perform hit detection and data writing in one cycle. To achieve this, a faster tag memory and comparator are required. Required.

An object of the present invention is to solve this problem with lower hardware costs.

[Configuration of the invention]

(Means for Solving the Problems) A cache memory writing device according to the present invention is provided between a processor and a main storage unit, and stores a part of data in the main storage unit in a cache memory; Before writing data to the cache memory, storage means for storing at least data at an address in the cache memory at which the writing is to be performed; and means for writing data from the processor to the address of the cache memory. Determining means for determining whether or not data of a main storage address to be written from the processor exists in the cache memory; and when the determining means determines that the data does not exist, the processor determines that the data does not exist. While the data written to the cache memory is maintained, the cache is Means for reading the data of the main storage address into the cache memory, and means for rewriting the data stored in the storage means to the main storage unit in preference to the data in the cache memory. .

(Operation) In response to a write operation from the processor, the cache memory of the present invention stores at least data (generally one word) read from a corresponding address in the first half of the cycle in the storage means. In the latter half of the cycle, the processor data (generally one word) is written to the corresponding address of the cache memory regardless of the hit / miss signal of the determination means. In the following next cycle, a hit / miss signal is output from the determination means. In the case of a hit, no further processing is required. In the case of a miss, it is necessary to read necessary data from the main memory, but only the address written by the processor retains its contents.

Generally, in a cache memory, data of a plurality of words is stored in a data memory for one main storage address stored in a tag memory. This is called a block (or line), and reading from the main memory and writing back to the main memory are performed in block units.

Also, in the tag memory, there is a flag indicating whether data in the cache has been rewritten by the processor before. When this flag is set when a block is replaced, if the flag is set, the previous value in the cache is set. Data must be written back to the address in main memory indicated by the tag. The data to be rewritten is usually data in the cache, which is transferred to the evacuation memory and then written back to the main memory. In the present invention, especially in the case of the above-mentioned mistake, at least a part of the data to be rewritten is not in the cache but in the storage means. By operation, the result of giving priority to the data stored in the storage means over the data in the cache (generally, data of a plurality of words as described above) is written back to the main storage.

(Embodiment) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. 1 is a processor, 9 (AL) is the lower part of the address output from the processor, and 10 (AH) is the upper part of the address. In the embodiment, the cache memory is of a direct mapping (copy back) type, and AL and AH are each represented by a four-digit number. AL is supplied to the cache memory 2, and the output of the tag memory is compared with AH. (Hit detection unit 3) That is, in the direct mapping cache, on the main storage unit 5,
Data at addresses with the same AL may enter the same entry in the cache. The upper part of the address of the data currently being cached is stored in the tag memory.
That is, by comparing the contents of the tag memory addressed at the lower (AL) of the address output by the processor with the AH, it can be determined whether or not the cache has hit. hit
The HIT / MISS signal 12 is a signal indicating an or miss. The data memory 4 is supplied with the AL address of the processor and accesses data.

If a cache miss occurs, correct data is read from the main storage unit 5 and stored in the data memory 4. If the previous contents of the data memory have already been rewritten by the processor, the contents are written back to the main storage unit 5.

For this purpose, the data before the data memory is stored in the write-back storage unit 6 during the reading from the main storage unit 5.
In the embodiment, one block of the cache has four words.

FIG. 2 is a diagram showing the relationship between the contents of the tag memory and the data memory. In the tag memory, V,
M, has information of upper address. V is a valid flag, and indicates whether data is valid. M is a rewrite flag, and indicates whether the data of the block has been changed by the processor.

For each entry in the tag memory, 4
Words correspond.

FIG. 3 is a timing chart showing a read operation by the processor. The read operation is the same in the related art and the present invention. Processor cycle 0 is a read operation when a cache hit occurs. Data 0 corresponding to address 0 is read during the same cycle. The processor cycle 1 to n is a read operation at the time of a cache miss. First, address 1 was output and data X was read in processor cycle 1, but at the beginning of cycle 2,
Since HIT / MISS = 0, it is known that there is a cache miss. Therefore, data X is treated as invalid data, and the processor stops while HIT / MISS = 0. During this time, the cache side reads the correct data from the main memory and passes the correct data 1 to the processor in the processor cycle n.

FIG. 4 is a timing chart showing the write operation of the present invention. Although the output timing of the HIT / MISS signal compared with FIG. 5 does not change, it can be seen that the write cycle is completed in one cycle.

In the present invention, at the time of writing, writing is performed to the cache memory regardless of HIT / MISS. Instead, control is performed such that data whose original data in the cache is saved in the one-word storage unit is used when writing back to the main storage is necessary. Thus, the write operation, which conventionally required two cycles, can be performed in one cycle.

 The operation of the present invention will be described with reference to FIG.

Processor 1 outputs a write address from AL9 and AH19. AL is the lower part of the address and AH is the upper part. In this embodiment, it is assumed that each has 16 bits. The processor outputs the write data to the DATA bus 15 simultaneously with the output of the address. This is 32 bits (1 word). AL is supplied to the address of the tag memory 2, and the output data 11 from the tag memory and AH are compared by the hit detection unit 3, and if they match, the HIT / MISS signal 12 is set to 1; This signal is determined in the next cycle after the processor outputs the address. In parallel with the comparison operation, AL is supplied to the data memory 4 as an address. Data at the address is read from the data output line 16 and stored in the one-word storage unit 7. Subsequently, the write data output by the processor is transferred to the input buffer 13 through the DATA bus 15.
Is input to the data memory 4 and written.

Actually, the HIT / MISS signal is determined at the next timing. However, if the HIT / MISS signal is 1, the write operation is completed. If the HIT / MISS signal is 0, a cache miss has occurred. There is a need.

This is performed in the route of the main memory 5, the memory data buffer 17, the input buffer 13, and the data memory 4. At this time, the data from the memory is not written to the word whose value has already been written by the processor. In the present embodiment, the data memory 4
Although it is assumed that the words correspond, three of the four words read from the memory except the word written by the processor are written to the cache.

Before the processor writes data to the cache, the V flag, M
When both the flag and (FIG. 2) are set, it indicates that the data portion contains valid data and has been rewritten by the processor after being copied from the main storage portion 5. . In such a case, it is necessary to save the data to the write-back storage unit 6 before the data is replaced with data at another address of the main storage, and then write it back to the main storage unit 5 later. This is a feature of the write-back cache. In this embodiment, the write-back storage unit 6 has a capacity of four words equal to one block size of the cache, and data is written from the data memory 4 through the data output line 16 to this. At this time, if a cache miss occurs due to a write operation, only the data at the written address is written not from the data memory but from the one-word storage unit 7.

Further, in the cache memory system, an operation of bypassing the cache may be permitted. That is, the processor may directly access the main storage unit or directly access the I / O register. This is called a non-cache operation.

There is no problem if non-cache operation is determined when the processor outputs an address.However, if this is determined via some path such as address replacement, it must be non-cache operation. May be coincident with the HIT / MISS signal or later. In such a case, the present invention includes a reproduction buffer 18 for rewriting old values from the one-word storage unit 7 to the data memory.

In the present embodiment, the cache method is described as direct mapping, and the block size is set to 4 words (1 word 32 bits). However, there is no particular limitation. Modifications are possible without departing from the spirit of the invention.

〔The invention's effect〕

If the clock cycle of the processor is sufficiently longer than the time required for detecting a cache hit, the cache memory can perform both reading and writing in one cycle, but the clock cycle becomes shorter and the processor becomes faster. As they become, they face the problem of missed hit detection. Therefore, as a conventional solution, a write is processed in two cycles, a read is processed in one cycle irrespective of a hit or miss, and in the second cycle, the processor is notified of information as to whether the read data is valid or not. Was.

According to the present invention, it is possible to obtain an effect that a write operation can be completed in one cycle as long as a hit is made similarly to a read operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a relationship between a tag memory entry of a direct mapping cache used in an embodiment of the present invention and a data memory block (4 words each). FIG. 3 is a timing chart 4 showing a read operation by the processor of the present invention, FIG. 4 is a timing chart showing a write operation by the processor of the present invention, and FIG. 5 is a timing chart showing a write operation by the conventional method. 1 Processor 2 Tag memory 3 Hit detection unit 4 Data memory 5 Main storage unit 6 Write-back storage unit 7 1-word storage unit 8 Selector 9 …… AL, 10 …… AH 11 …… Tag memory output, 12 …… HIT / MISS signal 13 …… Input buffer, 15… DATA bus 16 …… Data output line, 17 …… Memory data buffer 18 …… Reproduction Buffer

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kenichi Maeda 1 Toshiba Research Laboratory, Komukai Toshiba-cho, Saisaki-ku, Kawasaki-shi, Kanagawa Prefecture (56) References JP-A-53-148344 (JP, A)

Claims (1)

(57) [Claims] A cache memory provided between a processor and a main storage unit for storing a part of data in the main storage unit; and a cache memory for writing data from the processor to the cache memory. Storage means for storing data of at least the address at which the writing is to be performed; means for writing data from the processor to the address of the cache memory; and a main storage address at which the writing from the processor is to be performed. Determining means for determining whether or not the data exists in the cache memory; and when the determining means determines that the data does not exist, the data written from the processor to the cache memory is maintained, and Means for reading data of the main storage address from the main storage unit to the cache memory; Cache memory writing device stored the data in the storage means in preference to the data in the cache memory, characterized by comprising a means for writing back to the main storage unit.