JPS5829187A - Cache memory controller - Google Patents

Abstract

PURPOSE:To prevent the competition between an operand readout request and an instruction readout request and also between a storage request and the readout request, by providing a specific cache storage buffer circuit and a coincidence detection circuit. CONSTITUTION:Cache storage buffer circuits 40 and 50 are provided, which receive storage address information and storage data information with a storage request from a CPU11 to a main storage device 12 independently, store the information tentatively and generate a buffer storage request to an instruction cache memory 31, an operand cache memory 30 and the main storage device 12 when the storage address information and the storage data information to be outputted exist. Further, an instruction address coincidence detection circuit 60 is provided, which compares the instruction readout request address information from the CPU11 with all the address information tentatively stored in the said buffer circuit 40 and generates instruction address coincidence detection information when the coincident address is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a cache memory control device including a cache memory provided between a central processing unit (hereinafter referred to as C!PU) and a main memory, and a control circuit for controlling the cache memory. Regarding.

In general, an information processing device having this type of cache memory control device temporarily stores part of the information stored in the main memory, and stores the information in the main memory at a higher speed than that.
By using a cache memory that exchanges information with the PU, information can be processed at high speed.

Furthermore, in order to further improve processing speed, this type of information processing apparatus processes each instruction by pipeline control.

Conventionally, as an information processing device having a cache memory,
A cache memory for operands and a cache memory for instructions are provided, and when the request from the CPU is to read an operand, reading is performed from the cache memory for operands, and on the other hand, when the request from the CPU is for an instruction.

An information processing device that reads from an instruction cache memory has been proposed.

When there is a conflict between an operand read request and an instruction read request, the information processing device according to this proposal can issue each request in a distributed manner to cache memories for operands and for instructions. can be avoided. However, in an information processing device that performs pipeline control, it is necessary to take into account not only competition between instruction read requests and operand read requests, but also competition between storage requests and instruction or operand read requests in the cache memory. There is.

In this way, as a countermeasure against the case where a storage request and a read request conflict with each other, the present inventors provided one set of cache store buffer circuits each having multiple entries, one for each operand cache memory and one for an instruction cache memory. proposed a cache memory control device (patent application 1982)
-118627). This type of cache memory control device uses two sets of cache buffer store circuits, so it has the advantage of being able to independently process storage requests for instructions and storage requests for operands, but it requires a large amount of hardware. It also has drawbacks.

Furthermore, since a normal program is written using logical addresses, the cache memory control device requires an address converter to convert these logical addresses into real addresses. However, from the outside, the above-mentioned patent application does not consider an address translator suitable for a cache memory control device having a cache store buffer circuit.

An object of the present invention is to provide a cache memory control device that can prevent conflicts between storage requests and read requests as well as conflicts between operand read requests and instruction read requests! It is to provide.

Another object of the invention is to use less hardware.

Therefore, it is an object of the present invention to provide an economical cache memory control device.

Another object of the present invention is to provide an address translator suitable for a cache memory control device of a type that can prevent conflicts between storage requests and read requests.

The present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, a cache memory control device according to an embodiment of the present invention is provided between a central processing unit (hereinafter abbreviated as CPU)-11 and a main storage device 12.

This cache memory control device includes first and second cache memories 60 and 31 for operands and instructions,
The first one that controls each cache memory 30 and 61.
and second cache memory control circuits 20 and 21, respectively. After the CPU 11 has calculated the operand address of a certain instruction, it outputs this operand address via the operand address output line 24. Furthermore, 0PU11 also outputs control information via this line 24, and if this instruction is of a type that stores the calculation result in a certain memory address,
The output operand address is stored in the address buffer circuit 40. Further, when the data of the operation result to be stored in the memory address stored in the address buffer circuit 40 is obtained, the CPU 11 outputs it along with the control information via the store data output line 26, and the data is sent to the data buffer as an operand. stored in circuit 50. The buffer circuits 40 and 50 are first-in, first-out (F'IF'0) buffer circuits having the same depth. The memory address and the data corresponding thereto are stored in corresponding locations (same buffer address) of the buffer circuits 40 and 50 (that is, the data corresponding to the memory address stored in the circuit 40 is stored in the corresponding location of the circuit 50). (stored in the buffer address). All the contents (the memory addresses) stored in the buffer circuit 40 are supplied to one input terminal of each address from each.

The other input of the first address-number construction circuit 60 is supplied with a memory address when the 0PU 11 issues a read request to read an operand from a memory address, thus.

If any of the memory addresses stored in the address buffer circuit 40 matches the read request memory address.

When the first address-number configuration circuit 60 receives a coincidence detection signal from the first and second cache memory control paths 60, the first cache memory control circuit 2o becomes operational; The second cache memory control circuit 21 becomes inactive. Further, the other input of the second coincidence detection circuit 61 has 0PU11.
When a request is made to read an instruction from a memory address, the memory address of the instruction to be read is supplied, and if this memory address matches any memory address stored in the address buffer circuit 40, The second aeru. In this case, the second cache memory control circuit 21 becomes active, and the first cache memory control circuit 20 becomes inactive.

The circuit 20 when these coincidence detection signals are given
The operations of and 21 will be described later, but first, the operation when there is no coincidence detection signal will be explained.

Now, what is the buffer storage request information from the address buffer circuit 40☆←茫 and its output?

÷m via address buffer output line 80, 1iii
≠Supplied to the first and second cache memory control circuits 20 and 21.

Here, if an instruction of a type that stores operation result data at a memory address appears.

At the appropriate step of the instruction, the memory address is transferred to the address buffer circuit 40.

Furthermore, the data resulting from the calculations are stored in the circuits 50 without delay, thereby avoiding disturbances in the pipeline flow caused by conflicting memory accesses for reading and storing, as seen in conventional devices. When the contents are stored in the buffer circuits 40 and 50 in this way, the address buffer circuit 40 sends the buffer storage request information to the first and second cache memory control circuits 20 and 21, respectively, via the output line/80. supply

On the other hand, the first cache-memory control circuit 20 receives a request to read an operand of a certain instruction from the CPU 11 via the output line 24, and if the coincidence detection signal is not present at that time, the first cache-memory control circuit 20 performs the read operation. Request the circuit 4
Buffer storage requests from 0 are accepted with priority. In this case, the buffer circuits 40 and 50 can temporarily store data to be stored in response to a storage request from the CPU 11. As a result, the first cache memory control circuit 20 buffers the storage request from the CPU 11. It is possible to hold the read request in the circuits 40 and 50 and receive the read request with priority. Therefore, even if there is a conflict between a read request and a storage request from the CPU 11, disturbances in the pipeline flow can be avoided. When the read request is accepted in this way, the circuit 20 reads the line 2
The data at the memory address supplied via 4.

It is read from the first cache memory 30 and supplied to the CPU 11 (if the specified memory address does not exist effectively in the cache memory 60, the circuit 20 stores the block containing the data at that memory address in the main memory). The data is read from the device 12 and stored in the first cache memory 60, and at the same time, the data at the designated memory address is controlled to be supplied to the 0PU 11).

If there is no read request from the 0PU 11 and there is a storage request from the address buffer circuit 40, the first cache memory control circuit 20 accepts this storage request and stores the address to be read via the line 80. Specified by data. The memory address of the first cache memory 30 corresponds to this address data. One piece of data stored in the circuit 50 is read out and stored. At this time, if this memory address does not exist validly in the first cache memory 30, these data only need to be read from the buffer circuits 40 and 50 and discarded. This is based on the following principle.

That is, although not particularly shown, the main memory device 12 includes an address buffer circuit and a data buffer circuit that have the same depth as the address buffer circuit 40 and the data buffer 50 and write exactly the same contents as each. The data to be stored in the memory address is stored separately in the cache memory (
This is because the storage process in the main storage device 12 is performed separately, completely independent of the storage process in the operand cache memory 30 and the instruction cache memory 31). That is, the data temporarily stored in the circuit 40 and the circuit 50 is originally data that should not be written to the designated memory address of the main memory 12, and the data is stored in the 1'res buffer path in the main memory 12 described above. The buffer circuit is a buffer that temporarily stores the data in order to store the data in the main memory device 12 by utilizing the idle time when the main memory device 12 is accessed from other circuits. In this way, since an independent route is separately provided for storage in the main storage device 12, especially when there is no valid memory address to be stored in the first cache memory 30, There is no need to perform any special processing for this.

Now, exactly the same type of processing as that for the first cache memory 30 is performed for the second cache memory 31 as well. That is, if the address buffer circuit 40 has data, it also sends a storage request to the second cache memory control circuit 21 via the buffer output line 80. On the other hand, the circuit 21 receives an instruction read request from the 0PU 11 via an instruction read request line 28. If this request is accepted and there is no coincidence detection signal from the second address-number construction circuit 61, the circuit 21 converts the contents of the memory address designated by the line 28 into the second address-number configuration circuit 61. It is read from the character memory 31 and supplied to the CPU 11 (at this time, if the data at the specified memory address does not exist effectively in the cache memory 31, it is read from the main memory 12 and supplied; however, the method is the same as in the case of the first cache memory 30 described above). When there is no instruction read request from 0PU11 and there is a storage request from the circuit 40, the circuit 21.

A memory address to be stored is read from the circuit 40, and if the memory address is validly present in the second cache memory 31, the data at the memory address is rewritten with the data read from the data buffer circuit 50. . However, if the memory address to be stored does not exist effectively in the cache memory 31, as described above, the buffer circuit 40
and 50 corresponding data is simply read and discarded.

Now, the operation above 9 is the operation when there is no coincidence detection signal from the address-number construction circuits 60 and 61, but when there is any coincidence detection signal, the following occurs.

Now, as mentioned above, there is an operand read request from the CPU 11, and the memory address of the operand is a certain data stored in the address buffer circuit 40 (
buttress), the first coincidence detection circuit 6
0 provides a coincidence detection signal to the first and second cache memory control circuits 20 and 21. Upon receiving this, the circuit 20 receives the storage request from the circuit 40 with priority,
The addresses stored in the circuit 40 up to the address where the match occurred and the corresponding data stored in the circuit 50 are read out sequentially (by FIFO control), and the latter is stored in the memory address specified by the former. Store the data of.

In this case, if a specified memory address does not exist validly in the cache memory 30, the data corresponding to that memory address can simply be read and discarded as described above.

After processing the storage request up to the memory address where the match occurred, the circuit 20 processes the C! Accepts read requests from T'U If. By controlling in this way, when a preceding instruction updates a certain memory address in the first cache memory 30 and a subsequent instruction uses data at that memory address as an operand, the operand will be updated. Irrespective of operations such as prefetching or temporary suspension of data to be stored, the subsequent instruction always uses the data updated by the preceding instruction as an operand, so no malfunction occurs.

In this case, the coincidence detection signal from the first address-number construction circuit 60 is also sent to the second cache memory control circuit 21, but the second cache memory control circuit 21
It is recognized that the input is from the address-number construction circuit 60, and the operation is stopped.

Similarly, the 0PU 11 makes a request to read an instruction via the instruction read request line 28, and the specified memory address from which this instruction is to be read.

If the data matches any of the data stored in the address buffer circuit 40, the second address output circuit 61 sends a match detection signal to the second and first cache memory control circuits 21 and 20. give. Upon receiving this, the circuit 21 accepts the storage request from the circuit 41 with priority.

The addresses stored in the circuit 40 up to the address where the match occurred and the corresponding data stored in the circuit 50 are sequentially read out (under PI°FO control) and are stored in the second cache memory. The latter data is stored in the memory address specified by the former of 31. In this case,
If a specified memory address does not exist validly in the cache memory 61, as described above,
Just read and discard the data corresponding to that memory address. After processing the storage request from the circuit 40 up to the memory address where the match occurred, the circuit 21 accepts the instruction read request from the CPTJ 11. By controlling in this way, immediately after an instruction to update a certain memory address in the second cache memory 31, the CPU 11 updates the data at the memory address (
command) is read as a command.

Despite the process of temporarily suspending instructions to be stored in the cache memory 31 and storing them in the circuits 40 and 50, the instruction updated by the preceding instruction is always read out from the instruction cache memory 31. Since it is supplied to 0PU11, no malfunction will occur.

Also in this case, since the -number output signal is also sent to the circuit 20, the circuit 2o operates in the same manner as when the first address-number output circuit 60 detects the coincidence detection signal. stop.

Further, in the above embodiment, when a match is detected in the minus number output circuit 6o or 61, data up to the address corresponding to the address where the match was detected is given priority over others and stored in the cache memory 3o or 31 in the FIFO. Instead of this, it is also possible to control so that only the data at the address where a match occurs is written to the cache memory with priority over others. With such control.

Processing speed can be further improved.

Referring to FIGS. 2 and 3, the cache memory control circuit according to the second embodiment of the present invention is applied to an information processing system in which logical addresses are given as address information accompanying read requests and storage requests of operands. be done.

For this reason.

As shown in FIG. 2, this embodiment includes an address conversion circuit 90 that converts logical addresses from the CPU II into real addresses. Generally, the address associated with an instruction read request is also given in the form of a logical address, so the second
Although it is necessary to connect an address translation circuit to the cache memory control circuit 21, it is omitted here to simplify the explanation. It should be noted that the second address/number configuration circuit 61 is given an address associated with an instruction read request without changing the logical address.

Further, the address conversion circuit 90 shown in FIG. 1 not only converts a logical address into a real address, but also converts a part or all of the logical address to the address buffer circuit 40 and the first address-number calculation circuit, as will be described later. On the other hand, the address buffer circuit 40 has a function of storing not only real addresses but also logical addresses. Here, the first and second address match detection circuits 6
0 and 61 compare the address stored in the address buffer circuit 40 and the address associated with the read request in the form of logical addresses. Thus, in this example,
Since addresses are compared without converting the addresses in the address buffer circuit 40 into real addresses,
Matches and mismatches can be detected quickly.

Referring to FIG. 3, the address translation circuit 90 shown in FIG. 2 is connected to the first cache memory control circuit 20. First cache memory 60. Address buffer circuit 50.
and the first address match detection circuit 60. Note that read requests and store requests are made by the CPU 1 (not shown).
It shall be identified by the circuit within 1.

The logical address accompanying the read request and store request from 0PU11 is set in the logical address register 91 (abbreviated as LAT'L) in the address conversion circuit 90. L.A.
The logical address set to R is indexed in the address conversion key section 92 to check whether a correspondence from the logical address to the real address is registered. If it is registered in the address translation KEY section (TI, B-KEY section) 92, the real page address is registered in the corresponding address translation data section (TLB-DATA section) 93, and the switching circuit 27 converts the TLB-DATA The switching circuit 28 selects each address in the page of LAR to obtain the real address, and the output is transferred to the physical address register 26 (abbreviated as I'AR).
is set to If the logical address is not registered in the TLB-KEY section 92, address translation is performed and the result is stored in the TLB-KEY section 92゜TLB-D.
It is registered in the ATA section 96. Since this address translation algorithm is well known, its explanation will be omitted here.

When there is a store request from the 0PU 11, a real address is obtained from the address conversion circuit 90 and stored in the real address section (abbreviated as 5TB-RA) 45 in the address buffer circuit 40. The logical address set in the L/191 at the same timing is stored in the address buffer circuit 40.
The data is stored in the logical address section (abbreviated as 5TB-LA) 42 within. In this embodiment, the circuit 40 is configured as a FIFO.

When store data is given to the data buffer circuit 50 from the CPU 11, the store operation for the CPU 11 is considered to have been completed, but since the CPU 11 performs advance control using the memory line, the store address is independent of the store data. is stored in the circuit 40.

In the case of a read operation, the real address is obtained from the address conversion circuit 90, and in parallel, the address array 23, which is a directory for the cache memory in the cache memory control circuit 20, is indexed and the desired address is stored in the operand cache memory 30. The comparator circuit 24 checks whether one block containing the data has been registered, and the result is set in the address array hit register 25 (abbreviated as AHR). If it is registered in the normal buffer memory, it is called FO()ND BLOCK (abbreviated as FDB), and if it is not registered, it is called N0TFOUNDBLO.
It is called CK (abbreviated as NF'B). When there is an operand read request from the CPU 11, the read request logical address is set in the LAR 91.

On the other hand, all or part of the address information of the LAR91 is
n comparison circuits 6 in the first address match detection circuit 60
2 and registered in the 5TB-LA 42, it is detected whether the desired data is stored in the circuit 50, and the result is stored. A match detection signal is sent from the 5HR 63 to the switching circuit 46 and the circuit 20, and the LA
The address information associated with the read request set in R91 is temporarily stopped, and the address information of the 5TB-RA 45 is sent to the store buffer output address register (SAR) 29 in the circuit 20, and the switching circuit 28 is sent to the store buffer output address register (SAR) 29 in the circuit 20. AA23 is indexed through the block address AA23 and the corresponding block address is AA23.
23, the circuit 3 is transferred from the AHR 24 to the circuit 3.
An instruction is issued to the data array 32 in 0 to store the store data from the circuit 50 at the address indicated by the PAR 26. In this way, after all the store data stored in the circuit 5o or the store data corresponding to the store address in the 5TB-LA for which the matching signal was detected in the circuit 60 is stored in the DA 32, the data is temporarily stored in the LAR 91. The read request logical address that has been stopped is sent to the TLB-KEY section 92. TLB-DATA section 93. The PA through the comparison circuit 94 and the gate circuit 95
R26 is set, and if desired data is registered in the AA23, the desired data indicated by the PAR26 and the AHR25 is read out from the DA32 via the gate 33 and sent to the 0PU11 via the switching circuit 46. It will be done.

In this embodiment, in particular, the store buffer and AA are indexed in parallel, and the index result of AA is set in the register AHR, so there is an advantage that the store buffer is indexed using logical addresses. In other words, the result of the index of the store buffer is set in the register SHR, and the presence or absence of data in the store buffer and buffer memory can be directly determined from the output of the register (consisting of solid flops). This is very advantageous in terms of time and therefore easier to control.

By the way, in the virtual memory system, the same real address may be assigned to different logical addresses. in this case,
A condition is required that different logical addresses in one logical space must not point to the same real address at the same time. When switching logical spaces and page-in and page-out of the memory area of the main storage device, it is necessary to synchronize the address translation buffer.

You must ensure that write requests are not present in the store buffer. If @write requests are held in the store buffer, flush all write requests from the store buffer.

After the write process is completed in the information processing device, logical space switching and main storage page-in.

It is possible to page out. This is something that is normally done regardless of the present invention and is not a limitation for implementing the present invention.

As described above, according to the present invention, one set of address buffer circuits and data buffer circuits is provided, and this set of buffer circuits is combined with separately provided operand cache memory and instruction cache memory. It is equipped with

Therefore, the present invention improves the cache hit rate and throughput with a relatively small amount of hardware, performs pipeline-based advance control, and improves the time loss caused by disturbances in the pipeline flow of an information processing device with a NOW CPU. It is possible to provide a cache memory control device that solves the problem of pre-fetching an instruction (7) where the result is missing due to pre-fetching of an operand due to advance control. This has the effect of improving the processing efficiency of the information processing device.

Margin below

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache memory control device according to one embodiment of the present invention, FIG. 2 is a block diagram of a cache memory control device according to another embodiment of the present invention, and FIG. 3 is a block diagram of a cache memory control device according to another embodiment of the present invention. There is a block diagram of an address translator used in the embodiment. , in FIG. 1, 11... central processing unit (01) U
). 24... Operand address output line. 26... Store data output line, 12... Main storage device, 28... Instruction read request line, 20.
・・Cache memory control circuit for operand. 21... Instruction cache memory control circuit. 60... Operand cache memory. 31... Instruction cache memory. 40...→-→-# Kinsakaki address buffer circuit. −゛. 50... ≠ 7 half-complete data buffer circuits. + + □ 60...First address match detection circuit. 61...Second address match detection circuit. 70...Address comparison line. 80...Address buffer output line. 90...Address conversion circuit. 92...TLB KEY section, 93...TLB data section. 23... Address array Abbreviation AA32... Data array Abbreviation DA42... Logical address part of store buffer Abbreviation 5TB-LA 45... Real address part of store buffer Abbreviation 5TB-
RA 91...Logical address register Abbreviation LAR26...
・Physical address register Abbreviation PAR29... Store buffer output address register abbreviation 5AR 25... Address array hit register abbreviation AHR 63... Store buffer hit register abbreviation 5IR 94... Comparison circuit 24... 1 62. ...I 27...Switching circuit 1 28...Switching circuit 2 46...Switching circuit 6 95...AND game 1 33...

Claims (1)

[Scope of Claims] 1. In a cache memory control device provided between a main storage device and a central processing unit, a part of instruction information stored in the main storage device is temporarily stored; an instruction cache memory that exchanges instruction information with the central processing unit in place of the main memory; temporarily stores part of the operand information stored in the main memory; an operand cache memory for exchanging operand information with the central processing unit in place of the main storage; in response to a store request from the central processing unit to the main storage; The store address information and store data information associated with the instruction are received and temporarily stored respectively, and when the store address information and store data/event information to be output are complete, the instruction cache memory, + '+II +1t: Cache memory for A perando, a cache store buffer circuit that generates a passoa store request to the main storage device; coupled to the central processing unit and the cache store buffer circuit, which reads instructions from the central processing unit. an instruction address match detection circuit that compares the requested address information with all address information temporarily stored in the cache store buffer circuit, and generates instruction address match detection information when a matching address is detected; coupled to the central processing unit, coupled to the cache store buffer circuit in common with the instruction address match detection circuit, and temporarily transmits operand read request address information from the central processing unit to the cache store buffer circuit. an operand address match detection circuit that compares all stored address information and generates operand address match detection information when a matching address is detected; the central processing unit, the main storage device, and the instruction cache; an instruction cache memory controller coupled to a memory and the cache store buffer circuit; and an operand cache coupled to the central processing unit, the main storage device, the operand cache memory, and the cache store buffer circuit. and a memory control unit; the instruction cache memory control unit checks whether or not the requested address exists in the instruction cache memory in response to an instruction read request from the central processing unit, and reads the requested address. If there is, the instruction information of the requested address is read from the instruction cache memory, and if there is no requested address, the instruction information of the requested address is read from the main storage device and stored in the instruction cache memory, In response to a store request from the store buffer circuit, it is checked whether the store address exists in the instruction cache memory, and if the requested address exists, the store information from the store buffer circuit is transferred to the instruction cache memory. When the instruction address match detection information is generated, the operand cache memory control circuit is stopped and the store request from the cache store buffer circuit is controlled to be processed with priority in the set state. death'
Cache memory lJ control for the operand! In response to an operand read request from the central processing unit, the unit checks whether the requested address exists in the operand cache memory, and if the requested address exists, reads operand information of the requested address from the operand cache memory. If there is no read request address, the operand information of the request address is read from the main storage device and stored in the operand cache memory, and in response to the store request from the cache store buffer circuit, the operand information is stored in the operand cache memory. It is checked whether the store address exists or not, and if there is a request address, the store information from the store buffer circuit is controlled to be stored at the request address of the cache memory for the operand, and the operand address match detection information is generated. In this case, in a state where the instruction cache memory control circuit is stopped, a cache memory control device performs control so that a store request from the cache store buffer circuit is processed with priority.