JPS6149250A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To perform reflection processing at a high speed to an instruction fetch buffer memory of an operand store with simple constitution, by omitting the necessity of synchronization between both pipelines of an operand fetch and an instruction fetch in an operand fetch mode. CONSTITUTION:An operand store address given from an I-UNIT1 is set only at an operand execution address register 31, and it is checked whether said address is stored or not in an operand buffer memory 32. If the memory 32 stores the address, the operand store data set to an operand store data register 37 is written on the memory 32. The operand store address stored in a buffer memory of a store-through system and the addresses of a store address register 390 and a store data register 391 to which data are set are reflected to the operand store of an instruction fetch buffer memory 35.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer storage system in a data processing device, and more particularly to a buffer storage system having separate buffer storage devices for operands and instructions. This invention relates to a buffer storage control method for correctly ensuring data updateability when storing operands in a system.

In recent years, various methods have been considered to improve the performance of data processing devices, and one of the methods is a pipeline method. This method divides one instruction execution sequence into multiple phases, provides multiple stations to execute each phase, and configures each station to operate independently.
It attempts to process multiple instructions at the same time.

Usually, the central processing unit (hereinafter referred to as CPU), which is the core of a data processing device, has three functional blocks, namely, I-UNIT LH, UNIT 2. S
-11NIT 3. and buffer memory bag f(t+s)
It is composed of 4.

1-UNIT '1 decodes instructions and controls the entire pipeline of the CPU. E-UNIT 2 is a unit that performs calculations, and 5-UNIT 3 is a unit that controls access to a buffer storage device (hereinafter referred to as BS) 4 and a main storage device (not shown).

As an example of the above CPU pipeline, I-UNIT
The pipeline of No. 1 is shown in FIG.

One instruction completes the instruction fetch phase (INST FE
TCII) after being read from BS 4, φA~φF
It is processed through the following six phases.

A portion of each phase is divided into two or three cycles, and the processing assignments for each cycle are as follows.

I: Address calculation for instruction fetch.

T: Refer to the address translation buffer (TLB) and the tag section of BS 4 for the address of the instruction.

B: BS4 reading and writing.

Decoding the Dz command.

R: Register read.

A: Address calculation during operand store.

T: Accesses the address translation buffer (TLB) and the tag section of BS 4 for the address of the operand.

B: BS4 read 1 fortune-telling.

El: Operation execution cycle 1゜ E2; Operation execution cycle 2゜ ■: Check cycle.

W: Operation result prediction cycle.

Figure 7 shows how access to BS 4 is performed in the above CPU pipeline.
5-UNIT 3 pipeline controlling BS 4 (
b) is shown in comparison with the pipeline (a) of I-UNIT 1.

As is clear from the figure, both instruction fetch and operand access consist of four cycles, and the processing in each cycle is as follows.

P: Priority cycle that determines the priority of using BS4.

T: Refer to the address translation buffer (TLB) and the tag section of BS 4 for the address of the current fetch.

B: BS4 reading and writing.

R: Depending on the access result, the read data is 1-UN
Result cycle sent to IT 1' and E-UNIT'2.

As shown in FIG. 7, access to BS 4 is issued twice, in the I cycle and the A cycle, in the pipeline that processes the l instruction.

Therefore, in order to avoid a collision between the two BS4 accesses, one instruction is processed every two cycles so that the above-mentioned (2) cycle and A cycle do not overlap. This relationship is indicated by diagonal lines in FIG.

If a CPU using this pipeline is configured so that instructions can be input to the pipeline every cycle, the processing speed of the CPU can be doubled.

However, if the pipeline is started every cycle, there will be a collision between ■ cycle and A cycle, and ■ even if two instructions can be fetched per cycle, the pipeline of the 1-UNIT 1 will The processing power is that only one instruction can be executed in 1.5 cycles.

Therefore, in order to configure an efficient cycle-by-cycle pipeline, it is necessary to separate the instruction fetch BS and operand fetch BS so that they can operate independently.

The problem with the above two BSs is that the same block (32 bytes or 64 high ha) is
This is a control that attempts to match the contents when they exist in the two BSs.

This problem is similar to the control method for matching data when two CPUs each have separate BSs.

[Conventional technology]

FIG. 9 shows an example of the conventional system having the above two BSs.

In this figure, 31 is an operand execution address register (hereinafter referred to as OER), 32 is an operand address register, and 33 is an operand word register (hereinafter referred to as OWI).
'i), 34 is the instruction execution register (hereinafter referred to as IER
35 is an instruction fetch buffer memory.

36 is an instruction word register (hereinafter referred to as IWR) 13
7 is the operand store data register (0SDR
), 38 is an instruction store data register (hereinafter l
5DR).

In this conventional example, the address of the operand fetch from I-IJNIT 1 is set in OER31, the operand buffer memory 32 is accessed, and the read data is set in OWR33 and sent to E-11NI.
Sent to T2.

Similarly, the instruction fetch address is set in the IER 34, the read data from the instruction fetch buffer memory 35 is set in the IWR 36, and the I-UNIT
1.

The above operand store address is OUR1, and IE
R34 is set at the same time, and the operand buffer record t!
32 as well as the instruction fetch buffer memory 35.
It is checked whether a data block at the address exists.

This is because even if the instruction sequence is placed at the beginning of the data block, there is a possibility that data will be included after it.

Then, when the block exists, E-UNIT
The operand store data from operand buffer storage 32.2 is set in 0SDR37 and l5DR38. and writes to the block at the corresponding address in the instruction fetch buffer memory 35.

On the other hand, when fetching an operand or fetching an instruction, if the corresponding address does not exist in the buffer storage, a block transfer request for the data at the address is issued to the main storage (not shown), and the block transfer is performed. The data is stored in the buffer memory.

[Problem that the invention seeks to solve]

In the above conventional method, when storing operands,
S-UNI accessing operand buffer storage 32
Pipeline indicated by P, T, B, R of T3 and 5-UN accessing instruction fetch buffer storage
There is a problem that the IT3 pipeline must be synchronized as shown in FIG.

That is, as shown in ■ in this figure, when priority is obtained with "prPif" in the priority cycle, buffer 1 access for store can be accessed immediately, but as shown in ■, buffer storage for instruction fetch is When a block transfer request (Pmi) is being processed, Pif is delayed by three cycles, and in order to synchronize with this, the pipeline on the operand side is also forced to wait for three cycles.

In view of the above-mentioned conventional drawbacks, the present invention provides operand fetch,
The object of the present invention is to provide a means for reflecting the operand store in the instruction storage without synchronizing the pipelines for the instruction processing and the instruction fetch.

[Means for solving problems]

This purpose is as follows: (1) Instruction fetch is performed from the instruction fetch buffer storage device, operand fetch is performed from the operand access buffer storage device, and operand store is performed from the operand access buffer storage device and the store address register. After performing the store data register, the fact that the cough operand store has been performed is reflected in the instruction fetch buffer storage device.

(2) When the above operand store is performed, the request is turned on at a predetermined timing in the operand pipeline in order to reflect the contents of the store data register in the instruction fetch buffer storage device. control to do so.

(3) Means for indicating, corresponding to each of the plurality of store data registers, that the contents of the store data register should be reflected in the instruction fetch buffer storage device (
For example, a flag) is provided, and the flag is turned on when data is stored in the corresponding store data register, and is reset to off when the store data is reflected in the instruction fetch buffer storage device. Control.

(4) When the contents of the store data register are reflected in the instruction fetch buffer storage device, a pointer is provided that indicates which store data register contents should be reflected in the instruction fetch buffer storage device next. , the contents of the pointer are stored in any store address register,
and controls a selection circuit for reflecting the store data register in the instruction fetch buffer storage device.

(5) The value of the pointer is shifted in synchronization with the operation of the instruction fetch pipeline, and the pointer value causes the store to be stored in the instruction fetch buffer storage device at a predetermined timing of the instruction fetch pipeline. Control the contents of the data register to be selected and written.

This is achieved by the buffer storage control scheme of the present invention.

This uses the address and data of the store buffer provided in the store-only type of buffer storage to write the instruction fetch buffer 1. The operand store is reflected in α.

[Effect]

That is, according to the present invention, the contents of the store data register (ST[l) are stored in correspondence with the store data register (STD) for performing store access to the main memory and the store address register (STAR). A flag (S
TB HOLD), and when storing the operand,
At a predetermined timing of the operand pipeline, a request is issued to the instruction fetch pipeline, and when the store data becomes valid, the above flag is turned on, and at a predetermined timing of the instruction fetch pipeline, the above instruction flag is sent to the instruction fetch pipeline. A pointer is provided to indicate which contents of the store data register (STD) are to be reflected in the instruction fetch buffer memory when controlling the flag to be turned off at the time when the store data is written to the memory. The above store address register (STAR)
, and a store data register (STD), and further synchronizes the value of the pointer with the operation of the instruction fetch pipeline to store the instruction in the store data register at a predetermined timing of the instruction fetch pipeline. Since the contents of (STD) are selected and recessed, there is no need to synchronize both the operand fetch and instruction fetch pipelines when fetching operands, and operand fetching can be performed with a simple configuration of M. This has the effect of speeding up the process of reflecting the instruction in the door's instruction fetch buffer storage.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

The present invention is based on the premise that store access from I-IJNIT 1 is a so-called store-only one-way method in which the store address and data are set in a store buffer that can hold the data at the same time as writing to the buffer memory, and the data is also written to the main memory. There is.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a store buffer (STB), and FIGS. 3 and 4 are diagrams showing the configuration of an embodiment of the present invention. FIG. 4 is a diagram showing a time chart of operations when performing store access.

In FIG. 1, 31 to 38 are the same as those explained in FIG. 9, and store address registers (hereinafter referred to as 5TA
R) 390, and a store data register (hereinafter referred to as S).
(referred to as TD) 391. and the hold flag H shown in FIG. 2 are functional blocks necessary to implement the present invention.

First, the operand store address from the I-UNIT 1 is not set to the IER 34, but only to the OER 31 side, and it is checked whether or not the operand store address exists in the sofa reader 32, and if so, 03D
The operand store data sent to R37 is written to operand buffer storage 32.

At the same time, the operand store address is 5TAR.
390, and the operand store data from E-LINIT 2 is set to STD 391, after which a write request to main memory is issued.

The present invention provides 5 TAR 390° and STD 3 provided in the store-through type buffer storage, in which the operand store address and data are set.
By using the address 91 and data, the operand store is reflected in the instruction fetch buffer storage 35.

Before the operand store address set in the 5TAR 390 is sent to the main memory, it is sent to the IER 34, and it is checked whether the address exists in the instruction fetch buffer storage 35.

If the address exists, the store data in the STD 391 is written to the instruction fesoch buffer memory 35 through the 15DR3B.

Due to the above operation, in operand store access, it is no longer necessary to execute both the operand fetch and instruction fetch pipelines synchronously, and the reflection of the operand store in the instruction fetish buffer memory 35 is as follows:
Store buffer (STB) address (i.e. 5TAR
390) and data (STD 391), it can be performed asynchronously with the pipeline of I-UNIT 1. However, STD 391 is already 5-UNI
It is provided as a component of T3, and its feature is that by reusing it, it can be realized without adding almost any new hardware. (Event described in claim 1) Next, regarding the specific operation when implementing the present invention,
This will be explained using the configuration diagram of the store buffer (STB) shown in FIG. 2 and the time charts shown in FIGS. 3 and 4.

The store buffer (STB) holds the real address of store access to main memory, as shown in FIG.
TAR390 and STD that holds 8 bytes of data
391, a valid (v) flag (hereinafter referred to as 5TARVALID) indicating that a store address has been entered in the 5TAR 390 as a control flag, and STD.
Ready (R) flag indicating that data has entered 391 (hereinafter referred to as STB RE 8 Y) and the above ST
A hold (11) flag (hereinafter referred to as STB HOLD) indicating that the data in D 391 has not yet been reflected in the instruction fetch buffer memory 35, and a dented byte when writing a portion of 8 bytes or less. It consists of a bite mark (BM) that indicates the position.

Among the control flags mentioned above, ST'B ll0LD(H) is a control flag newly provided to implement the present invention.

And 5TARVAIJD (1/), STB REA
The following states can be expressed by the flags DY(R) and STBI(OLD(11)): As mentioned above, the pipeline in S-[INIT a is operand buffer storage 32. Operand pipe play according to Hue Nochibanohpu memory 35.

The pipeline is divided into a one-instruction fetch pipeline and a one-instruction fetch pipeline, each consisting of the following phases.

P NIBRIITY CYCLE.

T near address translation buffer (TLB) and tag section (T
AG).

B: Reading of Sofa memory (13S), indentation cycle.

R/P: Buffer record (1 (BS) Depending on the result of access, read data to I-UNIT 1. IE-U
A cycle sent to NIT 2, and a priority cycle that determines the priority of inputting results to other pipelines.

W: Write cycle to operand buffer storage.

S: Store cycle to main memory.

First, the basic operation of the present invention will be explained with reference to FIG.

The operand store is input to the operand pipeline, and the store address from I-UNIT 1 arrives in the B cycle, so 5TARVALID is set on.

Next, in the R/P cycle of the operand pipeline, in order to issue a request to the instruction fetch buffer storage 35,
Submit a request to the instruction fetch pipeline. (
(event described in claim 2) When the instruction fetch pipeline accepts the input request, a signal r indicating that the operand access may be reflected in the instruction fetch buffer storage 35 is generated.
IF 'STL Go J is turned on, which causes
Store address pointer (P) 3 shown in FIG.
Step 901.

Since the store data from C-UNIT 2 becomes valid after the S cycle of the operand pipeline, in this cycle, the STBI? EADY, 5T
BII OLD is sent on.

If the above store address does not exist in the instruction fetch buffer memory 35, the instruction fetch/7chi pipeline
It ends in P cycles, but if the store address exists, it advances or retreats in S cycles.

In the middle of this W cycle, store 7 hours (ST, B
) is stored in the instruction fetch buffer tα35, STB 1 (OLD is reset at this timing. (event described in claim 3)) The value is incremented by the rIF STL GOJ signal, but the value before being incremented is set in a shift register (not shown) and synchronized with the operation of the instruction fetch pipeline.
This will be communicated until the W cycle.

The value of the pointer passed up to the W cycle (i.e., 5T
AR number) is the number of STDs to write data to the instruction fetch buffer memory 35.
It is used to select from 391. (Events described in claims 4 and 5) Furthermore, the control flag STBR
EADY is reset when the store data is sent to the main memory, and the control flag 5TARVALID is set to STB READY, STB)t.

It operates so that it is reset when the LD is reset.

The time chart in FIG. 4 shows an example in which a request from the operand pipeline is accepted by the instruction fetch pipeline with a delay of one cycle, and the operand store is transferred to the instruction fetch buffer memory 35. The operation to reflect is the same as in FIG.

In this manner, when an operand store is executed, the store data is correctly and quickly reflected in the instruction fetish buffer memory.

〔Effect of the invention〕

As explained above in detail, the buffer storage control method of the present invention has a store data register (STD) for performing store access to the main memory, and a store address register (STAR). A flag (STB ll0L) indicating that the contents of the data register (STD) have not yet been reflected in the instruction fetch buffer memory.
D), and when storing an operand, a request is sent to the instruction fetch pipeline at a predetermined timing of the operand pipeline, and when the store data becomes valid, the above flag is turned on, and the instruction fetch pipeline When controlling the flag to be turned off when store data is written to the instruction fetch buffer memory at a predetermined timing, which contents of the store data register (STD) are written to the instruction fetch buffer memory The store address register (STAR) is provided with a pointer indicating whether to be reflected in memory.

and store data register (STD) selection,
Furthermore, the value of the above pointer is set to U of the instruction fetch pipeline.
The content of the store data register (STD) is selected and written to the instruction fetch buffer memory at a predetermined timing of the instruction fetch pipeline in synchronization with J. , it is necessary to synchronize both the operand fetch and instruction fetch pipelines, and this has the effect of speeding up the process of reflecting the operand store into the instruction fetch buffer storage with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing an example of the configuration of a store buffer (STB). FIGS. 3 and 4 are time charts showing operations when operand store is executed by implementing the present invention. FIG. 5 is a diagram showing the configuration of the central processing unit (CPtl). FIG. 6 is a diagram explaining the operation of the I-UNIT pipeline. FIG. 7 is an explanatory diagram showing the access timing of one instruction to buffer storage. FIG. 8 is an explanatory diagram of two-cycle one-instruction processing. FIG. 9 is a block diagram showing a conventional system having two buffer memories. FIG. 10 is a diagram illustrating the synchronous control timing necessary for the conventional method shown in FIG. 9. In the drawing, ■ is l-11NIT, 2 is E-UNIT
. 3 is 5-UNIT, 4 is buffer storage. 31 is an operand execution address register (OER). 32 is operand buffer storage. 33 is an operand word register (OWR). 34 is an instruction execution register (IER). 35 is an instruction fetch buffer memory. 36 is an instruction word register (IWR). 37 operand store data register (OSDR)
. 38 is an instruction store data register (ISDR). 390 is a store address register (STAR). 391 is a store data register (STD). 3901 is a store address pointer (P). I, T, B, D, R, A, El, E2. V, W, S each cycle 1 STARVALID (V), 5TII READY (
R),'STB ll0LD(11) Lyoa, control flag. are shown respectively. confectionery 1 mouthful 2 (2

Claims (5)

[Claims] (1) A buffer storage device for operand access, a buffer storage device for instruction fetch, and a plurality of store address registers for performing store access to the main storage device;
and a store data register, the instruction fetch is performed from the instruction fetch buffer storage device, the operand fetch is performed from the operand access buffer storage device, and the operand store is performed from the operand access buffer storage device. , a store address register and a store data register, the method comprises means for reflecting the fact that the operand store has been performed on the instruction fetch buffer storage device. (2) When the above-mentioned operand store is performed, in order to reflect the contents of the above-mentioned store data register to the instruction fetch buffer storage device in the instruction fetch pipeline,
2. The buffer storage control method according to claim 1, wherein the buffer storage control method is controlled to turn on the request at a predetermined timing of an operand pipeline. (3) Corresponding to each of the plurality of store data registers, means is provided to indicate that the contents of the store data register should be reflected in the instruction fetch buffer storage device, and the means Claim 1: Controlled to be set to ON when data is stored in the register, and reset to OFF when the stored data is reflected in the instruction fetch buffer storage device. or the buffer storage control method according to item 2. (4) When the contents of the store data register are reflected in the instruction fetch buffer storage device, a pointer is provided that indicates which store data register contents should be reflected in the instruction fetch buffer storage device next. , the contents of the pointer are stored in any store address register,
and a store data register to control a selection circuit for reflecting the instruction fetch buffer storage device.
The buffer storage control method according to any one of paragraphs 3-3. (5) The value of the pointer is shifted in synchronization with the operation of the instruction fetch pipeline, and the pointer value causes the store to be stored in the instruction fetch buffer storage device at a predetermined timing of the instruction fetch pipeline. Claims 1 and 2, characterized in that the content of the data register is controlled to be selectively written.
The buffer storage control method according to any one of Items 3 and 4.