JPH0573311A - Instruction rewriting system for instruction buffer in processor - Google Patents

Abstract

PURPOSE:To improve processing efficiency and to increase processing speed by reading out a rewritten instruction from a memory part in the case of storing the detection of a rewriting geneation graph part at the end of the execution of one instruction and writing it in an instruction buffer. CONSTITUTION:When an instruction stored in a memory part 1 is rewritten for the instruction change during the execution of one instruction in an instruction execution part 3, an rewriting detection part 4 detects whether or not an instruction stored in an instruction buffer 2 corresponds to the one stored in the storage address of the rewritten instruction. When it is detected, a rewriting geneation flag part 5 stores the detection of the geneation of the rewriting of the instruction. At the end of the execution of one instruction in the instruction execution part 3, the rewriting generation part 5 is checked. In the case of the geneation of a rewriting, the corresponding instruction is read out from the same address of the memory part 1 storing the rewritten instruction to be written in the corresponding place of the instruction buffer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention holds a plurality of program instructions read from a memory unit in an instruction buffer, and rewrites the instructions stored in the memory unit during execution of the held instructions. The present invention relates to an instruction rewriting method of an instruction buffer in a processing device for writing this instruction from a memory unit to a read instruction buffer when this instruction corresponds to the instruction held in the instruction buffer.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional processing apparatus. This processing device has a memory 31 in which instructions are stored, and a CPU 36 which analyzes and executes these instructions.
The instruction length of each instruction is 4 bytes, and the number of bytes that can be simultaneously transferred by the bus, the so-called bus width, is 4 bytes.

The CPU 36 has an instruction buffer 32 having a capacity of 16 bytes and capable of holding four instructions in order to speed up the processing, while an instruction executing section 33 for executing these instructions and a memory for executing the instructions. The instruction code in 31 is rewritten, and the instruction code before rewriting is already fetched in the instruction buffer 32 (hereinafter, S
ICONF (STORE INSTRUSION C
ONFLICTION) SIC to detect)
The ONF detector 34 is provided.

FIG. 5 shows a specific circuit of the SICONF detector 34. This circuit compares the write address of the memory 31 in which the rewritten instruction code is stored with the address of the memory 31 from which the instruction held in the instruction buffer 32 is read by the comparator 37, and when they match. The SICONF detection signal is output.

In this processing apparatus, instructions are stored in the memory 3 one by one.
1 is fetched into the instruction buffer 32, and instructions A, B, C and D are sequentially read from the memory 31 as shown in the figure,
This is held in the instruction buffer 32. Then, the instructions held in the instruction buffer 32 are sequentially executed, and when the execution of one instruction is completed, a new next instruction is fetched from the memory 31 to the instruction buffer 32. In the figure, Vi (i =
1, 2, 3, 4) are instruction buffer valid flags provided corresponding to respective instruction holding areas in the instruction buffer 32, and NextA holds the instruction next to the currently executed instruction. Address of the instruction buffer 32 in which the
ch Pointer) indicates a holding address for holding an instruction to be fetched next in the instruction buffer 32.

Further, in FIG. 4, the instructions A, B, and C are already held in the instruction buffer 32, and the instruction D is the next held instruction. When the instruction buffer valid flag at the address pointed to by the IFP is OFF, the next instruction is fetched from the memory 31 and the instruction buffer 32
At the same time that the instruction is held, the instruction buffer valid flag is turned ON. Then, this flag is turned off at the same time when the instruction to be executed is transferred to the instruction execution unit 33.

On the other hand, in the instruction executing section 33, the instruction buffer 3
The instructions A, B, C and D transferred from 2 are executed in order. In this figure, the execution of instruction A is shown.

Now, assume that during execution of the instruction A, the instruction C in the memory 31 is rewritten by the instruction A into the instruction C '(SICONF state). At this time, the instruction to be executed next to the instruction B is the rewritten instruction C ′. However, if the instruction in the instruction buffer 32 is executed as it is, the instruction C is executed and a contradiction occurs.

In the prior art, the memory write address when the memory 31 is rewritten during the execution of the instruction is monitored by the SICONF detector 34 so that such a contradiction does not occur. Then, the address is the instruction buffer 3
When the instruction held in 2 matches the storage address in the memory 31, the SICONF detector 34 detects this and outputs a SICONF detection signal to the instruction buffer 32.

On the other hand, in the instruction buffer 32, all the instruction buffer valid flags are invalidated, the IFP is made to point to the same address as the address pointed to by NextA, and the instructions B, C ', and D are read again from the memory 31 in this order. Is written in the instruction buffer 32. By doing so, the instruction C ′ is executed next to the instruction B, and the contradiction disappears.

[0011]

By the way, in the processing apparatus according to the above-mentioned conventional example, a memory write may occur a plurality of times especially during the execution of an instruction such as a transfer instruction. For example, the memory write may be executed twice during the execution of the instruction A, and the instruction B and the instruction C may be rewritten.

In the above conventional method, when the SICONF state in which the instruction B is rewritten is detected while the instruction A is being executed,
All the instruction buffer valid flags are turned off, and immediately the instructions B ′, C and D are sequentially written from the memory 31 to the read instruction buffer 32, so-called memory write is performed. Then, when it is detected that the instruction C has been rewritten while the execution of the instruction A continues, the instructions B ′, C ′,
D was sequentially read from the memory 31 to perform the memory write.

Therefore, when a memory write occurs a plurality of times during the execution of one instruction in the instruction buffer 32, the memory writes other than the last memory write are wasted.
The processing speed of PU was reduced. For this reason, the performance was greatly reduced as the number of occurrences of the SICONF state increased during the execution of the one instruction.

Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to improve the processing efficiency of a processing device having an instruction buffer 32 capable of holding a plurality of instructions and to increase the processing speed. ..

[0015]

As shown in FIG. 1, the means of the present invention for solving the above-mentioned technical problems includes a memory section 1 for storing program instructions and an instruction read from the memory section 1. The instruction buffer 2 that holds a plurality of instructions, the instruction execution unit 3 that reads the instructions held in the instruction buffer 2 one by one, and executes the instructions, and the instructions stored in the memory unit 1 during the execution of the one instruction are rewritten. And a rewrite detection unit 4 for detecting whether the command held in the command buffer 2 is a command corresponding to the command stored in the storage address of the rewritten command. When the detection unit 4 makes the above detection, the memory unit 1
In the processing device that reads out the rewritten instruction from the above and writes it in the instruction buffer 2, when the instruction executing section 3 is executing the one instruction and the rewriting detecting section 4 performs the detection, this detection is detected. When the rewriting occurrence flag unit 5 for storing the information is provided and the fact that the rewriting occurrence flag unit 5 detects the above is detected when the execution of the one instruction is completed, the memory unit 1 This is to read the rewritten instruction and write it in the instruction buffer 2.

[0016]

According to the above means, the instructions are sequentially read from the memory section 1 and held in the instruction buffer 2. The instruction buffer 2 can hold a plurality of instructions, and the instructions held here are read one by one and executed by the instruction execution unit 3. When an instruction stored in the memory unit 1 is rewritten for instruction change while one instruction is being executed in the instruction execution unit 3, the instruction held in the instruction buffer 2 by the rewriting detection unit 4 is It is detected whether or not the instruction corresponds to the instruction stored in the storage address of the rewritten instruction. When this is detected, the rewriting occurrence flag unit 5 is made to store the fact that the rewriting of the instruction has occurred and the above detection is performed. Further, the rewrite may occur a plurality of times during the execution of the one instruction, but in this case, the rewrite occurrence flag unit 5 simply continues the state in which the rewrite is detected.

Then, when the execution of the one instruction in the instruction executing section 3 is completed, the rewriting occurrence flag section 5 is checked. If the rewriting has occurred, the rewritten instruction is stored. The instruction is read from the same address of the memory unit 1 in which it is stored and written in the corresponding location of the instruction buffer 2. Therefore, even if the rewriting may occur a plurality of times during the execution of the one instruction, the process of reading the instruction from the memory unit 1 and writing the instruction in the instruction buffer 2 is performed only once.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows an embodiment of the processing apparatus according to the present invention. This processing device has a memory 21 in which instructions are stored and a CPU 26 which analyzes and executes these instructions, while the instruction length of each instruction is all 4 bytes,
The bus width is composed of 4 bytes.

The CPU 26 has an instruction buffer 22 having a capacity of 16 bytes and capable of holding 4 instructions, an instruction executing section 23 for executing these instructions, and a memory 2 during the instruction execution.
S as the rewriting detection unit 4 that detects the SICONF state in which the instruction code in 1 is rewritten and the instruction code before being rewritten is already fetched in the instruction buffer 22.
An ICONF detection section 24 and a SICONF generation flag section 25 as a rewrite generation flag section 5 that stores the SICONF generation based on the detection signal from the SICONF detection section 24 are further provided.

FIG. 3A shows the SICONF detector 24.
3 shows a specific circuit of the SICONF occurrence flag unit 25. This circuit comprises a comparator 27, a JK flip-flop 28, and an AND gate 29, and the memory 2 in which the rewritten instruction code is stored.
The write address of 1 and the address of the memory 21 in which the instruction held in the instruction buffer 22 was stored are compared by the comparator 27, and this coincidence signal and the instruction execution completion signal from the instruction execution unit 23 (however, Two signals are ON at the same time
JK flip-flop 28
To the SICONF
Output the generated signal. A time chart of the above-described one-command processing is shown in FIG.

Now, in this processing apparatus, the instruction buffer 22
In the same manner as the conventional example, the initial state of
It is assumed that B and C are already held in the instruction buffer 22 and the instruction D is stored subsequently. Then, the operation of the processing device when the instruction B and the instruction C are rewritten during the processing of the instruction A will be described here.

When the SICONF detection unit 24 detects that the command B has been rewritten while the command execution unit 23 is executing the command A, the SICONF generation flag unit 25 is turned ON based on the detection. And
When it is detected that the instruction C has been rewritten while the execution of the instruction A continues, the SICONF generation flag unit 25 continues to be in the ON state because it has already been turned ON.

Next, in the instruction executing section 23, the above instruction A
When the execution completion point has been reached, the instruction execution section 23 outputs an instruction execution completion signal to the SICONF generation flag section 25. At this time, the SICONF occurrence flag unit 25 checks whether or not SICONF has occurred.
The ICONF occurrence flag unit 25 is ON. Then, from the SICONF occurrence flag unit 25, the SICO
The NF generation signal is output to the instruction buffer 22. Based on the SICONF generation signal, the instruction buffer 22 turns off all the instruction buffer valid flags Vi provided in each holding area of the instruction buffer 22 and refetches the instructions after the instruction B from the memory 21 to the instruction buffer 22. Write. Then, the SICONF occurrence flag unit 25 is set to SIC.
Turns ON without ONF occurrence.

Therefore, in the processing apparatus according to the present embodiment, the rewritten instruction is re-fetched when the execution of the instruction A in the instruction execution unit 23 is completed, so that the instruction A is wasted during execution. Since there is no need to perform re-fetching frequently, the processing efficiency of the processing device is improved and the processing speed is improved.

[0025]

As described above, according to the present invention, when an instruction stored in the memory unit 1 is rewritten while one instruction is being executed by the instruction execution unit 3, this is held in the instruction buffer 2. When the rewrite detection unit 4 detects that it corresponds to the stored instruction, the rewrite occurrence flag unit 5 stores this.
When the execution of one instruction is finished, the rewrite occurrence flag portion 5 is checked, and if the fact that the above detection is detected is stored, the rewritten instruction is read from the memory portion 1 Is written in the instruction buffer 2, so that even if the rewriting may occur a plurality of times during the execution of the one instruction, a process of reading the instruction from the memory unit 1 and writing the instruction in the instruction buffer 2 Since it is performed only once, the processing efficiency of the processing apparatus according to the present invention is improved, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a configuration diagram of a processing device according to an embodiment of the present invention.

3A and 3B are explanatory diagrams of a SICONF detection circuit according to an embodiment of the present invention, FIG. 3A is a circuit diagram, and FIG. 3B is a time chart of one instruction processing.

FIG. 4 is a configuration diagram of a processing device according to a conventional example.

FIG. 5 is a SICONF detection circuit according to a conventional example.

[Explanation of symbols]

 1 Memory 2 Instruction Buffer 3 Instruction Execution Section 4 Rewrite Detection Section 5 Rewrite Occurrence Flag Section

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toru Watanabe, 1015, Kamedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Maruyama 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takumi Takeno 1015, Uedotachu, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Shinya Kato, Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Japan

Claims (1)

[Claims] 1. A memory section (1) for storing program instructions, an instruction buffer (2) for holding a plurality of instructions read from the memory section (1), and an instruction held in the instruction buffer (2). An instruction execution unit (3) that reads out one instruction at a time and executes the instruction, and when the instruction stored in the memory unit (1) is rewritten during the execution of the one instruction, the instruction is held in the instruction buffer (2). Rewriting detection unit (4) for detecting whether the stored instruction corresponds to the instruction stored in the storage address of the rewritten instruction
And a rewriting detection section (4) for detecting the rewritten instruction from the memory section (1) and writing the rewritten instruction in the instruction buffer (2) when the rewriting detection section (4) detects the instruction. When the rewriting detection unit (4) detects the above detection while the execution unit (3) is executing the one instruction, a rewrite occurrence flag unit (5) for storing the detection is provided, and When the rewriting occurrence flag portion (5) stores the fact that the above detection has been made when the execution of the instruction is completed, the rewritten instruction is read from the memory portion (1), and this is read in the instruction buffer (2). ), The instruction rewriting method of the instruction buffer in the processor.