JPS60222969A - Pipeline controlling circuit - Google Patents

Abstract

PURPOSE:To improve the processing capacity of a vector data processor by controlling only an operating pipeline by a clock stop, and reading out a data by a free run, as for an access pipeline. CONSTITUTION:In a vector data processor, when a load data from a main storage device 1 is exhausted, a pipeline control part 6 executes a clock stop to a read-out pipeline based on various chain information from an instruction control part 5. That is to say, it is operated so as to keep a sequential property between a vector load instruction and a vector operating instruction. In this case, the clock stop is executed to only an operating pipeline LAP, and as for an access pipeline STP being other read-out pipeline, the control is executed so as to make it a free run. In this way, the regular vector store processing is executed continuously, a rise of the vector store instruction can be executed quickly, and the processing capacity of the vector data can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION +al Technical Field of the Invention The present invention relates to a pipeline control circuit when chaining occurs in vector registers in a vector data processing device using a pipeline method.

(bl Technical Background FIG. 1 shows a schematic diagram of a vector data processing device related to the present invention.

In the vector data processing process, vector data is first loaded from the main memory 1 through the data buffer 2 into the vector register 3. Next, the load data on the vector register 3 is supplied to the arithmetic pipeline 4, and after being subjected to arithmetic operations, the result of the arithmetic operation is written onto the vector register 3 again.

Now, let's consider the following case. That is, this is the case when the instruction following the load instruction is an operation instruction or a store instruction, and this instruction uses the data written on the vector register 3 by the load instruction.

Vector registers are chained together in such a state.”
It is expressed as shown in Figure 2.

Even in this case, if the next operation or store instruction is started after all elements of the vector load data are written into the vector register 3, there is no problem at all, and the method of the present invention described later is not necessary.

However, when I try to execute a vector instruction using the above method,
As shown in Figure 3, the pipeline that executes the next instruction is forced to wait until the completion of the vector load instruction, which significantly reduces performance in vector data processing devices that process a large amount of vector data with one instruction. This will lead to a decline.

For this reason, in vector data processing devices, the second
As shown in the figure, the load pipeline and the calculation (or store) pipeline 4 are operated in parallel.

Even in this case, while the vector load instruction is being executed, the vector register 3 is reliably loaded from the main memory w1 every cycle.
There is no problem if vector data is supplied above, but
When accessing the main memory device 1, vector data may not be read due to low priority as a result of bank collision or data bus contention that occurs when accessing the banks that make up the main memory device 1. Yes, and in this case vector data will not be supplied every cycle.

However, the operation (or store) pipeline 4 attempts to continue processing vector data every cycle. This means that the load data on the vector register 3 will eventually run out and normal operations (or.

store) processing will no longer be possible.

Therefore, in order to wait for the vector data necessary to deal with such a case to be loaded onto the vector register 3, the calculation (or store) pipeline 4 is stopped for a certain number of cycles, and the vector data is loaded into the vector register 3. 3, it becomes necessary to control the reading of vector data temporarily.

In order to make such control possible, consider a configuration as shown in FIG. In FIG. 4, 1 to 4 are the same as those explained in FIG. 1, 5 is an instruction control section, and 6 is a pipeline control section.

Here, it is assumed that the bus width of the load data from the main memory device l to the vector register 3 is equal to multiple elements.
It is also assumed that the timing of writing data to the vector register 3 is specified. For this purpose, it is necessary to provide a data buffer 2 between the main memory device 1 and the vector register 3 to temporarily hold the vector data. At this time, it is assumed that the data buffer 2 can hold vector data for a certain number of cycles. An outline of the above interruption control will be explained below.

First, various chain information is sent from the instruction control section 5 to the pipeline control section 6, and based on this information, the pipeline control section 6 determines whether to stop the operation (or store) pipeline.

The chain information includes ■°vector register write start signal°, ■°vector register write end signal゛, ■°
There are element enable signals ° and ■ ° vector register chain detection signal ring.

As shown in Figure 5, ■ is a signal that turns on at the timing when the first element is written to the vector register 3, ■ is a signal that turns on at the timing when the last element is written, and ■ is a signal that turns on at the timing when the last element is written. element voice (signal indicating that it is valid. Therefore, ■
When ■ is turned on between ~■, it means that the vector load data is not being continuously sent to the vector register 3. 3 is a signal that turns on at the timing when the operation (or store) pipeline 4 is about to read the first element of the vector register 3. Therefore, the signals (1) to (2) are sent from the instruction control section 5 to the pipeline control section 6 every cycle, and it is determined each time whether or not to stop the operation (or store) pipeline 4.

- As mentioned above, the timing to write vector data to the vector register 3 and the timing to read vector data from the vector register 3 are fixed depending on the element, so once it is stopped, the operation (or storage) will continue until the next timing. ) The pipeline 4 is stopped, and the vector data read from the main memory 1 during this period is not written to the vector register 3 but operates to be held in the data buffer 2.

Then, when the stop is released, writing and reading vector data to and from the vector register 3 is started. By controlling in this manner, the order of the vector load instruction and the vector operation (or store) instruction can be maintained.

Here, the meaning of the fixed timing of writing from the main memory device 1 to the vector register 3 will be explained in detail. The vector register 3 is divided into a plurality of parts called banks, and the timing of writing to each bank is defined.

As an example, FIG. 6 shows the vector register 3 divided into eight banks, and the timings for writing to each bank are assumed to be TO, TI, -111, and T7. TO indicates the timing to write to bank O, and T1 means the timing to write to bank 1.

After writing to bank 7 at T7, the process returns to TO and writes to bank 0, and thereafter the same process is repeated to sequentially write to each bank.

At this time (that is, when returning from T7 to TO), the address that accesses the vector register 3 is of course updated (+1). Here, if vector data is no longer supplied from the main memory device 1 to the vector register 3 (however, this happens asynchronously), it is not possible to write to the next bank, so in this case, wait 8 cycles. It will have to be done. At this time, updating of the address is suppressed.

For example, assume that immediately after writing to bank 2 at timing T2, the element enable signal 2 is turned off. Even if the invalidation of the element enable signal ■ is completed in one cycle, the next write timing is T4, and it is possible to write to bank 4, but this means that bank 3 is skipped and data is written to bank 4. Therefore, it does not mean that each bank of the hector register 3 is written in sequence.

Therefore, even if the data transfer from the main storage device ff1l to the vector register 3 is interrupted for only one cycle, it does not have much meaning. Therefore, until the next T3 timing comes around (that is, 8 cycles in this example),
The write operation is controlled to be stopped, and the vector data from the main memory device l during this period is stored in the data buffer 2.

As a result, the operation (or store) pipeline that reads vector load data from the vector register 3 also
Although it is necessary to interrupt the read operation during the above eight cycles, the basic principle is to stop the read operation pipeline (that is, the operation pipeline and the store pipeline).

In the present invention, when data transfer is being performed from the main memory 1 to the vector register 3 by a vector load instruction, for example, and an interruption in the data transfer occurs, even if the interruption is for one cycle, one pipeline suspending data transfer for a cycle (e.g., 8 cycles);
In a vector data processing device equipped with a control mechanism that restarts data transfer to vector register 3 from the next cycle, if the vector registers are chained, only the arithmetic pipeline of the next read operation pipeline It is related to the pipeline control circuit that stops the

(C) Prior Art and Problems As mentioned above, in the prior art, when data is not supplied from the main memory 1 in the register chain state, all vector register read pipelines are Then, by stopping the clock, the operation of the read pipeline was stopped.

In this case, even if the arithmetic pipeline 4 is controlled in this way, it will not have a large effect on normal pipeline control.

That is, in the arithmetic pipeline 4, the vector register 3 is the target for storing the result of the operation, and the result of the operation is normally stored in the vector register 3 unconditionally.

However, when data read from the vector register 3 is stored in the main memory device 1 as in the store pipeline, an access request is sent to the main memory control device and the request is accepted. Data cannot be transferred to the main storage device 1 until a "memory write permission signal" transferred to the pipeline control unit 6 is received later.

It takes a considerable number of machine cycles until the "memory write permission signal" returns to the pipeline control unit 6, and reading data from the vector register from that point on is not practical due to processing capacity. This will result in big losses.

Also, as mentioned above, the timing at which the read pipeline can access the vector register is stipulated, and in the worst case, it waits 7 cycles (in the case of 8 interleaving) after receiving the "memory write permission signal". There are cases where the vector register is read for the first time in the 8th cycle, and after the access request is received,
The number of cycles until writing to memory is undefined, or
There is a problem that memory access control becomes complicated.

Therefore, in current vector data processing devices, as mentioned above, several stages of data buffers 2 are provided between the main memory 1 and the vector register 3. For example, in the case of store processing, a predetermined Vector data can be read into the data buffer during the number of machine cycles (the time from when an access request is issued until the priority is taken and the above-mentioned "memory write permission main storage device" is returned to the pipeline control unit 6). Under the condition that it is certain, the access request is controlled to be sent to the main storage device 1, and at the same time, the store data is read from the vector register 3 to the data buffer 2, and the "memory write permission signal" is transmitted. When the data is returned, the data buffer 2 is read out and the data is transferred to the main storage device 1.

However, as described above, since the read timing from the vector register 3 is specified, it is possible to advance the access request to the main storage device 1 by that amount in advance.

In a vector data processing device that performs the above control, if all read pipelines are stopped as described above, the read bus from vector register 3 to data buffer 2 will be interrupted due to clock stop. , everything is frozen.

Therefore, there is no guarantee that data for access requests that have already been transmitted or for which priority has been taken can be supplied to the data buffer 2 within the specified cycle.

This is because it is completely unpredictable when the clock stop state will be released, and with this conventional control method, there is a possibility that data changes will occur.

If we dare to stop all the read pipelines as described above by clock stop control, we can read data into data buffer 2 in advance and issue access requests only for the data existing in data buffer 2. It is clear that the overhead in the pipeline control unit 6 will be large.

(dl Purpose of the Invention In view of the above-mentioned conventional drawbacks, the present invention controls only the arithmetic pipeline of the vector register read pipeline by clock stop, and the access pipeline is free-run without clock stop control. The purpose is to provide a method for reading data.

tel Structure and object of the invention According to the present invention, there is provided a vector register that allows one or more elements to be accessed simultaneously, an arithmetic pipeline that performs an operation between the vector registers, a storage device, and the above. an access pipeline for transferring data between vector registers, the vector registers are divided into one or more banks, and the timing for accessing each bank is defined;
In a vector data processing device having a data buffer between the hector register and the storage device, when the vector registers are in a chained state due to an instruction to load the hector register and an instruction to read the hector register. This is achieved by providing a method of clock-stopping only the arithmetic pipeline in the read operation pipeline when the load data from the storage device runs out. In a vector instruction, even if a clock stop condition occurs during register chaining, the vector store instruction can continue normal vector store operation without being affected in any way, and the processing of the vector data processing device It has the effect of preventing a decline in ability. Furthermore, since the store access pipeline is in a free running state, the startup of the vector store instruction can be made faster.

([1 Embodiment of the Invention To summarize the gist of the present invention, the present invention has a main memory WilF
In a vector data processing device having a data buffer between a vector register and a vector register, when the vector register is in a register chain state due to a vector instruction to load data to the vector register and a vector instruction to read the vector register, When the load data from the main memory device runs out, only the arithmetic pipeline among the read pipelines is clock-stopped to control access to the vector register.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 7 is a diagram showing the configuration of a vector data processing device to which the present invention is applied, FIG. 8 is a time chart showing an outline of the operation of the access pipeline according to the conventional method, and FIG. FIG. 3 is a time chart showing an outline of the operation of the access pipeline when the present invention is implemented.

In FIG. 7, 1 to 6 are the same as those explained in FIG. 4, and 7 is a main memory control section.

In this figure, the pipeline control unit 6 not only controls data flowing through the pipeline, but also sends an access request (c) to the main memory control unit 7 and receives the "memory write permission signal" (e). , controls reading out data on the data buffer 2 to the main memory 7, further receives register chain information from the instruction control unit 5, and performs clock stop control for the arithmetic unit (pipeline) 4, etc.

The main memory control unit 7 has a function of receiving the access request (c) sent from the pipeline control unit 6 and allocating a plurality of memory accesses to each access port based on the main memory priority order.

In this vector data processing device, a pipeline control unit 6 controls a load access pipeline LAP, a store access pipeline STP, and an arithmetic pipeline 4 based on instructions from an instruction control unit 5.
It is assumed that the aforementioned register chain exists between the write vector register 3 in the load access pipeline LAP and the read vector register 3 in the arithmetic pipeline 4.

When the load data from the main storage device 1 runs out due to a bank collision or the like, the pipeline control unit 6
executes a clock stop on the read pipeline based on various chain information from the instruction control unit 5,
It operates to maintain the order between the vector load instruction and the vector operation instruction.

At this time, in the present invention, the key point is that the clock stop control is performed only on the part surrounded by the dotted line, and the other read pipeline, the store access pipeline STP, is controlled to be free run. There is.

The effects of such lockstop control will be made clearer with reference to FIG. 7 and operation time charts of FIGS. 8 and 9.

Figure 8 is an operation time chart in the conventional example, (1)
indicates an access request transmission cycle, (■) indicates a priority order determination cycle, (■) indicates a write cycle to the main memory, (■) indicates a data buffer read cycle, and (a) indicates a cycle in which a vector store instruction is executed. (b) shows the timing of reading element data from vector register 3 at data buffer 2.
(C) is the access request transmission timing; (d) is the period during which the main memory control unit determines the memory access priority (in this example, it takes 3 machine cycles). ), (e) shows the timing at which the "memory write permission signal" is received in the pipeline control unit 6, and (f) shows the timing at which the above element data is received in the main storage device 1. , respectively.

As is clear from this figure, in the conventional system, when the clock stop control is executed, the pipeline control circuit operates to stop all read pipelines for the vector register 3. At the timing when the vector data is actually read into the buffer 2, an access request to the main memory device l is sent, and from the sending of the access request until the reception of the "memory write permission signal", the receiving is You need to save the vector data you took.

FIG. 9 is a time chart showing the operation when the present invention is implemented and a vector store instruction is executed.
) to (IV) and (a) to (f) are the same as those explained in FIG.

When the present invention is implemented, the store access pipeline is in a free-running state, so for example, as shown in this figure, the access request (c) to the main storage device 1 is sent to the vector register 1. This is done at the same time as the read timing (ao) of , and it can be clearly seen that the rise of the vector store instruction is faster than in the conventional method shown in FIG.

In this embodiment, an example was shown in which the access request (C) to the main memory device 1 is issued at the same time as the read timing (a) to the vector register 3, but it is not necessarily necessary to do so at the same time. For example, after how many machine cycles, data buffer 2 is transferred from vector register 3 to data buffer 2.
If it is known that data can be read at a certain time, it is obvious that the access request (a) to the main storage device ff may be sent in advance in accordance with the read timing.

(g) - Effects of the Invention As explained in detail above, the pipeline control circuit of the present invention provides data to the vector register in a vector data processing device having a data buffer between the main memory and the vector register. When the vector register is in a register chain state due to a vector instruction to load the vector register and a vector instruction to read the vector register, when the load data from the main memory is exhausted, the operation pipeline in the read pipeline Since this is designed to control access to the vector register by stopping the clock only for the vector store instruction, for example, if a clock stop state occurs during the register chain in another vector instruction that is completely unrelated to the vector store instruction. In addition, the vector store instruction can continue normal vector store processing without being affected in any way, and the start-up of the vector store instruction can be made faster than in the conventional method. This has the effect of improving the processing capacity of the processing device.

[Brief explanation of drawings]

Figure 1 is a diagram showing the outline of the vector data processing device, Figure 2 is a diagram showing the outline of the vector data processing device.
The figure schematically shows the state of the chain of vector registers, Figure 3 schematically shows the other states of the chain, and Figure 4 shows the clock stop of the operation (or store) pipeline. FIG. 5 is a diagram explaining the meaning of chain information, FIG. 6 is a diagram explaining the concept of banks in Hector Regisc, and FIG. 7 is a diagram explaining the vector data processing device to which the present invention is applied. Fig. 8 is a time chart showing the operation when a vector store instruction is executed in the conventional method, and Fig. 9 is a time chart showing the operation when the vector store instruction is executed by implementing the present invention. It is a diagram shown in the form of a chart. In the drawing, 1 is a main memory, 2 is a data buffer,
3 is a vector register, 4 is an arithmetic unit (pipeline),
5 is an instruction control section, 6 is a pipeline control section, and ■ is a hector register write start signal. ■ is a vector register write end signal, ■ is an element valid signal, and ■ is a register chain detection signal. TO-77 is the access timing to the vector register, (a) is the read timing in the vector register, (b) is the timing when vector data is received in the data buffer and is the holding period, and (C) is the sending timing of the memory access request. , (d) is the period during which the main memory control unit takes priority, and (e) is the timing when the pipeline control unit receives the [memory write permission signal]. (f) is the timing when vector data is received in the main memory, (I) is the memory access transmission cycle, (■
) indicates a priority determination cycle, (I[l) indicates a write cycle to the main memory, and (IV) indicates a read cycle from the data buffer.

Claims (1)

[Claims] A vector register that allows one or more elements to be accessed simultaneously, an arithmetic pipeline that performs operations between the vector registers, and an access pipeline that transfers data between the storage device and the hector register. In the vector data processing device, the vector register is divided into one or more banks, the timing for accessing each bank is defined, and a data buffer is provided between the vector register and the queen storage device. When the vector register is in a chain state due to an instruction to load the vector register and an instruction to read the vector register, and when the load data from the storage device is exhausted, only the operation pipeline in the read operation pipeline A pipeline control circuit having a function of controlling access to the vector register by stopping the clock of the vector register, but not stopping the clock of the access pipeline.