JPH0252301B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention A vector register that allows one or more elements to be accessed simultaneously, and one or more operation pipelines that perform operations between the vector registers. In a vector processing device equipped with a storage device and one or more access pipelines for transferring data between the vector registers, when there is a register chain between write and read operations to the vector registers, The present invention relates to a control circuit that performs stop control on the read operation pipeline.

(b) Technical background The configuration of a vector processing device related to the present invention is shown in FIG.

Generally, in a vector processing device, a vector register (VR) 3 is provided between the storage device 1 and the calculation pipeline 4 in order to reduce the number of transfers to and from the storage device 1 in order to increase the processing capacity. The calculation is executed between vector registers, and source data necessary for the calculation or data resulting from the calculation after completion of the calculation is transferred between the vector register (VR) 3 and the storage device 1.

This storage device 1 and the vector register (VR)
The access pipeline (load, store) 2 plays the role of data transfer between the access pipeline 3 and the access pipeline 2.

For example, when performing vector calculation A×B+CD, if the operands A, B, C, and D are located in a certain area of the storage device 1, then the A,
Operands B and C are transferred to vector register (VR) 3 by access pipeline (load) 21
[For example, vector registers A (VRa), B
(VRb), C(VRc)].

After performing multiplication of vector registers VRa and VRb,
Vector register X as a working register
(VRx), perform addition between vector register VRx and vector register VRc, and store the result in vector register D (VRd).
It is stored in the operand D area of the storage device 1 by the access pipeline (store) 22.
The instruction processing unit (IP) 5 controls the entire order of instructions in the vector processing.

The second time chart shows this situation.
It is a diagram.

Assume that the access pipeline 2 in FIG. 1 includes, for example, two load pipelines 21 and one store pipeline 22.

In Figure 2, processing of vector loads A and B
After writing to vector register VRa to vector register VRb is completed in La and Lb,
If A×B multiplication is executed in the multiplication pipeline processing M, the performance of the present vector processing device cannot be improved.

Therefore, as shown in this figure, access pipeline (load) processing La, Lb and arithmetic pipeline processing M are normally operated in parallel.

In other words, vector load A, vector load B
In the processing La, Lb, vector register
When it is recognized that writing to VRa and VRb3 has started, the multiplication pipeline processing M is activated.

In this case, there is a register chain from write vector registers VRa, VRb3 in processing La, Lb of vector load A and vector load B to read vector registers VRa, VRb3 for multiplication.

Also, X+C in addition pipeline processing AD
, between the multiplication pipeline processing M and the vector register VRx3, and from the write vector register VRc3 in the vector load C processing Lc to the read vector register (VR) c3 for addition. It shows that there is.

Access pipeline (load) like this
If register chaining is not performed from the write to the vector register to the multiplication or addition pipeline, or the access pipeline (store), each pipeline can be executed without being aware of the load access pipeline. Needless to say, they can operate independently.

In the case where there is the above register chain, the data transfer to the vector register (VR) 3 by the load access pipeline processing La, Lb may be interrupted due to bank collision or bus collision caused by other accesses to the storage device 1. Data is not necessarily transferred from the storage device 1.

Therefore, when data is no longer transferred from the storage device 1, it is necessary to prevent the read for calculation from overtaking the write to the vector register (VR) 3 (that is, the write to the vector register by load access). Therefore, when there are no more writes to the vector register, the entire operation of the pipeline related to the read operation, the store pipeline, etc. is stopped.

Although this can reduce the amount of hardware, it has been a factor in reducing the processing capacity of the vector processing device because the entire calculation pipeline is stopped.

(c) Prior art and problems Figure 3 is a diagram showing in detail the flow of each pipeline in a vector processing device according to the prior art.As shown in Figure 2, La, Lb, and Lc are load Access pipeline processing, M is multiplication pipeline processing, AD, AD′ is addition pipeline processing,
Sd indicates store access pipeline processing, and D indicates division pipeline processing. This will be explained below with reference to FIG.

First, in order to perform A×B multiplication, vector data is loaded from the storage device 1 into vector registers VRa and VRb3 by load access pipeline processing La and Lb.

, are the timings at which vector data starts to be transferred (written) to vector registers (VR) a and VRb3, respectively.

Twa and Twb indicate the sections written in vector registers (VR) a and VRb3, respectively, and the same applies to Twc and Twd.

Twx1 is running multiplication pipeline processing M,
In the pipeline processing, addition pipeline processing AD using a register chain instruction (i.e. vector addition instruction) indicates an interval in which reading is not yet in progress, and Twx2 indicates an interval in which multiplication pipeline processing M is writing to vector register VRx3. Yes, and addition pipeline processing AD is vector register
This indicates that the section is being read from VRx and VRc3.

The start of the multiplication of A×B is performed when the It is necessary to stop the multiplication pipeline processing M of ×B.

In this case, in the conventional method, the entire read operation pipeline processing for the vector register (VR) 3 (i.e., multiplication, addition, division, store pipeline processing, etc.) was controlled to be stopped. Operations in the arithmetic pipeline (for example, another addition (1), another division (2), etc.) that are not related to the above are also stopped, which causes a problem in that the processing capacity of the vector processing device is reduced.

(d) Purpose of the Invention In view of the above conventional drawbacks, the present invention provides a read operation related to load access pipeline processing La, Lb, Lc or multiplication pipeline processing M in which data transfer from the storage device 1 is exhausted. The purpose of this invention is to improve the processing speed of a vector processing device by providing a method for stopping only pipeline processing.

(e) Structure of the Invention According to the present invention, the present invention provides a vector register that allows simultaneous access to one or more elements, and one or more arithmetic pipes that perform operations between the vector registers. line and
A vector processing device comprising one or more access pipelines for transferring data between a storage device and the vector register, wherein data is transferred from the storage device to the vector register for each access pipeline. , a means for detecting a register chain of vector registers between the access pipeline and a pipeline that performs a vector register read operation, and a pipeline stop identification signal provided for each pipeline that performs a vector register read operation; Since data is no longer transferred from the storage device to the vector register in the access pipeline that is the source of the register chain, only the pipeline that performs the read operation specified by the pipeline stop identification signal is stopped. This has been achieved by providing a method to do this, and has the advantage of being able to prevent a reduction in the processing power of a vector processing device with a relatively small amount of hardware.

(f) Examples of the invention First, to summarize the gist of the present invention, the present invention includes the following:
In load access pipeline processing, when load data is no longer transferred from the storage device to a vector register, instead of stopping the entire read operation pipeline processing (multiplication, addition, division, store, etc.) for the vector register, By stopping only the corresponding pipeline processing such as the calculation pipeline or store pipeline that is chained to the load access pipeline processing, the amount of hardware is kept relatively small to prevent a decline in processing performance. It is something.

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 4 is a diagram schematically showing the main parts of a vector processing device to which the present invention is applied, and FIG.
6 is a diagram showing an embodiment of the pipeline stop control section shown in the figure, and FIGS. 6 and 7 show an embodiment of the register chain detection circuit 51 shown in FIG. 4. It is a diagram.

In Figure 4, 1, 2, 22, 3, 4, and 5 are the same as those explained in Figure 1, and 21
0 and 211 are load access pipeline 1LP1 and load access pipeline 2LP, respectively.
2, 41 is an addition pipeline (AP), 4
2 is a multiplication pipeline (MP), 43 is a division pipeline (DP), and 2101, 2111, and 51 are functional blocks necessary to implement the present invention. , PSC2), 51 is a register chain detection circuit (RCDET).

5, 10 is an addition chain state flip-flop STP A1, 11 is a multiplication chain state flip-flop STP M1, 12 is a division chain state flip-flop STP D1, 13 is a store chain state flip-flop STP S1, 14 is a write state flip-flop, 150 ~153,16
0 is an AND circuit (A), and 161 is a NOT circuit (N).

In FIGS. 6 and 7, C indicates a coincidence circuit, and in its output signal, for example, L-A
indicates that the write vector register in the load access pipeline is chained to the read vector register in the add pipeline. In the same way, for example, in A-MD, the write vector register in the add pipeline is chained to the read vector register in the multiply pipeline, and the write vector register in the multiply pipeline is chained to the read vector register in the divide pipeline. This shows that it is chained to the read vector register, and the same applies hereafter.

In the input signals in Figure 6, for example, the "write operand of load (LOAD)" indicates the register number of the vector register (VR) specified by the vector load instruction, and similarly, the "read operand of addition (ADD)" indicates the register number of the vector register (VR) specified by the vector load instruction. "Operand" indicates the register number of the vector register (VR) specified by the vector addition instruction, and the same applies hereinafter. However, MULTI indicates a vector multiplication instruction, DIV indicates a vector division instruction, and STORE indicates a vector store instruction.

Regarding the output signal in Figure 6, ADXX,
They are indicated by MUXX, DIXX, STXX, where XX indicates the subscript number, AD means addition pipeline, MU means multiplication pipeline, DI means division pipeline, and ST means store pipeline. There is.

And 601 to 649 indicate AND circuits,
701 to 705 indicate OR circuits.

Embodiments of the present invention will be described below with reference to FIGS. 4 to 7 while referring to FIGS. 1 and 3.

First, the register chain detection circuit (RCDET) 51 shown in FIG. 4 will be explained with reference to FIGS. 6 and 7 while referring to FIGS. 3 and 4.

This register chain detection circuit (RCDET) 51 includes a load access pipeline 1 (LP1) 210,
Load access pipeline 2 (LP2) 211
Here, for example, the load access pipeline 1 (LP1) 210 will be explained.

When executing vector load A in load access pipeline processing La, vector register VRa
In the multiplication pipeline processing M, the reading of the vector register VRa for executing multiplication (A×B) is chained from the writing of .

During the register chain period, the write operand (VRa) of LOAD and the read operand (VRa) of multiplication (MULTI) are the same, so the output of the matching circuit CLM is logic "1". "become. During the period ~ above, there is no read operation pipeline chained to the multiplication (MULTI), so the write start signal (LWS) or write in progress signal (LWACK) from the pipeline stop control circuit (PSC1) 2101, which will be described later, is used. As a result, only MU1 becomes logic "1", and only the multiplication pipeline stop identification signal becomes logic "1" through the OR circuit 703 in FIG.
Turn on.

At this time, the above load write start signal (LWS)
The write state flip-flop 14 is set by .

Therefore, the above load access pipeline processing
Load write signal (LW) at La is logic “0”
Then, the output signal of the NOT circuit (N) 161 becomes logic "1", and the output of the AND circuit (A) 151 becomes logic "1" via the AND circuit 160. When the output of the AND circuit (A) 151 becomes logic “1”,
It operates to turn on the clock stop signal (CLKS MP) to the multiplication pipeline (MP) 42.

Next, when vector load C is executed by load access pipeline processing Lc, the period
In Twc, writing to the vector register VRc is chained with reading from the addition pipeline processing AD, so that the addition pipeline processing AD becomes the target of the clock stop from the point in time.

Furthermore, since the store access pipeline process Sd that processes the vector store D starts from the time when the addition pipeline process AD starts writing, the vector register by the calculation process (X+C) in the addition pipeline process AD starts.
Vector register (VR) in store access pipeline processing Sd from writing to VRd
This means that the readings of d are chained.

Here, store access pipeline processing Sd
Since the vector register (VR) d is chained to the addition pipeline processing AD, it goes without saying that this cannot be started until writing in the addition pipeline processing AD starts.

Next, the above load access pipeline processing
In Lc, when vector load C is register-chained to addition pipeline processing AD and further to store access pipeline processing Sd,
The operation of the register chain detection circuit (RCDET) 51 will be explained.

At the time point in FIG. 3, the writing to the vector register VRc in the load access pipeline processing Lc is register-chained to the vector register VRc for reading in the addition pipeline processing AD.

Therefore, since the write operand (VRc) of the load (LOAD) is chained to the read operand (VRc) of the addition (ADD), the coincidence circuit (C)LA becomes logic "1", and as a result, the AND circuit 601
Since the output AD1 becomes logic "1", the OR circuit 702 in FIG. do.

In this state, when the load write signal (LW) in the load access pipeline processing Lc becomes logic "0", similar to the explanation for the period of ~,
It operates to set the clock stop signal (CLKS AP) to the addition pipeline (AP) 41 to logic "1".

Then, at the point of time, the vector register (VR) in the addition pipeline processing AD
Since d is register-chained to the vector register (VR) d in the store pipeline processing Sd, the coincidence circuit (C) A-ST is turned on, so the AND circuit 607 performs the AND with the AD1 signal. The ST20 signal turns on, and the output of the OR circuit 705 in FIG. do.

In this state, when the load write signal (LW) in the load access pipeline processing Lc becomes logic "0", similar to the explanation for the period of ~,
It also operates to turn on the clock stop signal (CLKS SP) for the store access pipeline (SP) 22.

In other words, if the register chain continues, if the first activated read pipeline (in this example, the addition pipeline) stops, the subsequent read pipeline (in this example, the store access pipeline) will start. It also functions to stop.

That is, even if there is a register chain between the addition pipeline processing AD and the store access pipeline processing Sd, unless a stop occurs in the first read operation pipeline (here, the addition pipeline), the subsequent read operation There is no need to stop the pipeline (here, the store access pipeline).

Next, the operation of the pipeline stop control section (PSC1) 2101 in the load access pipeline 1 (LPI) 210 shown in FIG. 4 will be explained with reference to FIG.

In FIG. 5, each addition, multiplication, division, and store chain state flip-flop (STP A1) 10,
(STP M1) 11, (STP D1) 12, (STP
S1) 13 performs addition, multiplication, and
It is set by the division and store pipeline stop identification signal, and is reset by the load write end signal (LWE) in the load access pipeline 1 (LPI) 210 and load access pipeline 2 (LP2) 211.

Also, the write state flip-flop 14 is set by the load write start signal (LWS) and reset by the load write end signal (LWE).

and some chained-state flip-flops [e.g., multiply chained-state flip-flops (STP M
1) 11] is on and the load write signal (LW) is turned off, the output of the NOT circuit (N) 161 becomes logic "1" and the output of the AND circuit (A) 160 becomes logic "1". It becomes “1”.

As a result, the output of the AND circuit (A) 151 becomes logic "1", and the multiplication pipeline (MP) 42
It functions to send a clock stop signal (CLKS MP) to the multiplication pipeline (MP) 42 and stop the operation in the multiplication pipeline (MP) 42.

The main focus of the present invention is concentrated on the operations of the register chain detection circuit (RCDET) 51 and the pipeline stop control sections (PSC1) 2101 and (PSC2) 2111.

Hereinafter, the overall operation when implementing the present invention will be explained with reference to FIG. 3, with FIG. 4 as the main subject.

First, when a vector load instruction, a vector operation instruction, a vector store instruction, etc. are processed in the instruction processing unit (IP) 5, a start signal, an operation code (OPC), a vector data length, etc. are sent to the access pipeline 2. (VL), memory start address, vector data distance, etc., and a start signal, operation code (OPC), vector data length (VL), etc. are sent to the calculation pipeline.

First, the write state flip-flop 14 shown in FIG. 5 is generated in the load access pipeline 1 (LPI) 210 and the load access pipeline 2 (LP2) 211.
At the same time as being set by the load write start signal (LWS), the load write start signal (LWS) and the load write in progress signal (LWACK) of the write state flip-flop 14 (a)
is sent to the register chain detection circuit (RCDET) 51, and according to the logic shown in FIGS. 6 and 7,
Load access pipeline 1 (LPI) 210,
Load access pipeline 2 (LP2) 211
A total of 8 pipeline stop identification signals (b), 4 for each read operation pipeline (in Figure 4, multiplication, addition, division, and store pipelines), are sent to the register chain detection circuit. (RCDET) 51, and is sent to each load access pipeline.

That is, load access pipeline 1 (LP1)
210, Load access pipeline 2 (LP2)
At step 211, when it is recognized that the load data has been written to the vector registers VRa and VRb at the timing shown in FIG. 3, the load access pipeline 1 (LPI) 210, Pipeline stop control unit (PSC1) 2101, (PSC2) 211 of load access pipeline 2 (LP2) 211
1, the multiplication chain state flip-flops (STP M1, STP M2) 11 are turned on by the multiplication pipeline stop identification signal. From this point on, the multiplier pipeline stop identification signal is applied to the multiplier chain state flip-flop (STP
1, STP M2) 11 until the writing is completed in vector registers (VR) a and VRb (that is, during Twa or Twb).

At this point, if writing to vector register (VR) a or VRb is no longer performed due to a bank collision in the storage device, etc., if the pipeline stop identification signal is on, In the embodiment, it operates to stop only the multiplication pipeline (MP) 42].

Specifically, according to the logic explained in Figure 5,
It functions by sending a clock stop signal (CLKS MP) to the multiplication pipeline (MP) 42.

In this case, the above load access pipeline 1
(LP1) 210, Load access pipeline 2
(LP2) Since it is impossible to predict which of 211 will stop, each logical sum condition (in other words, if either stops, the target pipeline will be stopped)
Accordingly, the multiplication pipeline (MP) 42 is configured to be stopped.

The above multiplication chained state flip-flop (STP M
1. STP M2) 11 is configured to be reset at the last timing of Twa and Twb [i.e., the load write end signal (LWE)], so there is no effect on subsequent stops due to load writes. Also, for another addition 1 or another division 2 in the interval Twa, Twb, the pipeline stop identification signal is not turned on, so the pipeline processing AD', D
[Another addition (1), another division (2)] never stops.

Furthermore, regarding the interval Twx1 from the point in time to the start of the addition pipeline processing AD, which is the next register chain, the pipeline processing of the above-mentioned another addition (1) or another division (2) is performed using the vector load A La,
As mentioned above, the operation can be performed without being aware of the vector load B Lb.

Next, at the time point, the multiplication chain state flip-flops (STP M1, STP M2) 11
is already in an invalid state, but for load access pipeline processing Lc that processes vector load C in load access pipeline 1 (LP1) 210, addition pipeline processing AD
Since only registers are chained, the addition chain state flip-flop (STP A1) 10 is turned on by the addition pipeline stop identification signal at the time when the addition pipeline processing AD starts.

When the flip-flop (STP A1) 10 is turned on, the load access pipeline 1 (LP
1) Until the write operation to the vector register VRc of 210 is completed (that is, during the interval Twc)
The addition pipeline (AP) 41 is the load access pipeline 1 (LP1) 210.
It is subject to clock stops from .

At this point, in the register chain detection circuit (RCDET) 51, the store access pipeline processing Sd that processes the vector store D is processed by the addition pipeline processing AD in accordance with the logic explained in FIGS. 6 and 7. , the vector register (VR) d is detected to be chained, so the store chain state flip-flop (STP S1) 13 is turned on by the store access pipeline stop identification signal.

By implementing the present invention in this manner, from the timing (that is, during Twx1), for the load access pipeline 1 (LPI) 210 and the load access pipeline 2 (LP2) 211,
Only the multiplication pipeline (MP) 42 is connected to the load access pipeline 1 from
(LP1) Addition pipeline (AP) for 210
Only 41 are subject to pipeline stop,
From the point onwards, load access pipeline 1
The addition pipeline (AP) 41 and the store pipeline (SP) 22 are subject to pipeline stop until the write operation to the vector register VRc of the (LP1) 210 is completed.

In this way, in the present invention, for each load access pipeline or arithmetic pipeline, only the read operation pipeline with register chain functions as the target of pipeline stop, unlike the conventional method. The feature is that it is controlled so that the operation does not stop even in the pipeline where there is no register chain.

(g) Effects of the Invention As explained above in detail, the pipeline control circuit of the present invention is capable of controlling the vector register when load data to the vector register is no longer received from the storage device in load access pipeline processing. Rather than stopping the entire read operation pipeline process (multiplication, addition, division, store, etc.), only the corresponding read pipeline process such as the arithmetic pipeline or store pipeline that has register chaining to the load access pipeline process Since it is designed to stop the processing, it is possible to prevent a decrease in the processing capacity of the vector processing device with a relatively small amount of hardware.

[Brief explanation of the drawing]

Figure 1 shows the configuration of the vector processing device.
FIG. 2 is a diagram conceptually showing the flow of pipelines in a vector processing device, FIG. 3 is a diagram showing in detail the flow of each pipeline in a vector processing device according to the prior art, and FIG. FIG. 5 is a diagram schematically showing the main parts of the applied vector processing device, and FIG. 5 is a diagram showing an embodiment of the pipeline stop control section shown in FIG. 4.
FIG. 7 is a diagram showing an embodiment of the register chain detection circuit shown in FIG. 4. In the drawing, 1 is a storage device, 2 is an access pipeline, 21 is a load access pipeline, 22 is a store access pipeline, 3 is a vector register (VR), 4 is an arithmetic pipeline,
5 is an instruction processing unit (IP), La, Lb, and Lc are load access pipeline processing, M is multiplication pipeline processing, AD, AD' are addition pipeline processing, Sd is store access pipeline, and D is division pipeline processing. processing, ~ is the timing point, Twa,
Twb, Twc, Twx1, Twx2, Twd are vector processing sections, 210, 211 are load access pipeline 1 (LPI), load access pipeline 2 (LP2), 41 is addition pipeline (AP), 42 is multiplication pipeline (MP), 43 is a division pipeline (DP), 2101, 2111 are pipeline stop control units (PSC1, PSC2),
51 is a register chain detection circuit (RCDET), 10
is an additive chain state flip-flop (STP A1),
11 is a multiplication chain state flip-flop (STP M
1), 12 is a division chain state flip-flop (STP D1), 13 is a store access pipeline chain state flip-flop (STP S1), 1
4 is a write state flip-flop, 150 to 1
53, 160, 601 to 649 are AND circuits (A),
161 is a negative circuit (N), 701 to 705 are OR circuits, CLKS AP, CLKS MP, CLKS DP,
CLKS SP indicates a clock stop signal for the pipeline that performs each read operation.

Claims (1)

[Scope of Claims] 1. A vector register that allows one or more elements to be accessed simultaneously, one or more arithmetic pipelines that perform operations between the vector registers, and a link between a storage device and the vector register. A vector processing device is provided with one or more access pipelines that perform data transfer, and when data is transferred from the storage device to the vector register for each access pipeline, the access pipeline and Means for detecting a register chain of vector registers between pipelines that perform a vector register read operation, and a pipeline stop identification signal for each pipeline that performs a vector register read operation, are provided to detect the access that is the source of the register chain. Since data is no longer transferred from the storage device to the vector register in the pipeline, only the pipeline that performs the read operation specified by the pipeline stop identification signal is stopped. vector processing device. 2 A holding unit is provided to hold a pipeline stop identification signal provided for each access pipeline, and when a pipeline that performs a read operation from the vector register is activated, the pipeline stop identification signal is A line stop identification signal is set in the holding section and reset when a series of operations are completed in the access pipeline, and only when the holding section is in the holding state, a read operation at the location indicated by the holding section is performed. 2. The vector processing device according to claim 1, wherein a pipeline that performs the processing is targeted for pipeline stop. 3. The pipeline that performs each read is configured to stop the pipeline if any of the pipeline stop signals from all the access pipelines indicates a stop state. A vector processing device according to claim 1. 4. A means for detecting a register chain is provided between the pipelines that perform each read operation, and if the first activated read operation pipeline stops, if there is a register chain between the read operation pipelines, A vector processing device according to any one of claims 1, 2, and 3, characterized in that a function is provided to also stop a subsequent read operation pipeline.