JPH0316665B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a method for writing data to and reading data from vector registers when a chain of vector registers occurs in a vector processing device using a pipeline method. This paper relates to a pipeline control method that guarantees synchronization.

[Technology background]

FIG. 1 shows an overview of the vector processing device. In the figure, 1 is a main memory, 2 is a data buffer, 3 is a vector register group, and 4 is an arithmetic pipeline. In the vector processing process, first, a plurality of pieces of vector data are successively loaded from the main memory onto a vector register. Next, the load data on the vector register is supplied to the arithmetic pipeline, and after the arithmetic operation is performed, the result of the arithmetic operation is written onto the vector register again. In this way, in a vector processing device, a vector register group is installed between the storage device 1 and the calculation pipeline 4 in order to reduce data transfer between the storage device 1 and the calculation pipeline 4 in order to increase processing performance. 3 (VR) is provided.

Now, let's consider the following case. That is, this is the case when the instruction following the load instruction is an operation naming or store instruction, and this instruction uses data written on the result vector register of the load instruction. This state is said to be a chain of vector registers.

In this case, as shown in Figure 2, if you start the next operation instruction or store instruction after all elements of the vector load data have been written to the vector register, the next operation instruction will read data from the vector register. , no problem arises. However, in this method, the arithmetic pipeline that executes the next instruction is forced to wait until the vector load is completed, resulting in a significant drop in performance in a vector computer that processes a large amount of data with one instruction.

For this reason, vector computers usually run a load pipeline and an operation pipeline or a store pipeline in parallel, as shown in FIG.

In this case, there is no problem if data is reliably supplied from the main memory to the vector register every cycle while executing the vector load instruction, but when accessing the main memory, there may be a memory bank conflict or , data bus contention may occur, resulting in a lack of priority.
At this time, data will not be supplied every cycle.

However, an operation or store pipeline attempts to continue processing data every cycle. This means that there is a possibility that the load data on the vector register will eventually become exhausted and normal arithmetic or store processing will no longer be possible.

Therefore, in order to deal with such a case, in order to wait for the necessary data to be loaded onto the vector register, the operation or store pipeline is stopped for a certain number of cycles, and the data is read from the vector register. It becomes necessary to have a control that can temporarily interrupt the process.

[Purpose and structure of the invention]

An object of the present invention is to interrupt the transfer of data to the vector register and the reading of data from the vector register when two consecutive vector instructions with a chain of vector registers are executed in parallel. The purpose of the present invention is to control the elements so that they can be held in the correct context even if the elements are stored in the correct context.The structure of the present invention for this purpose includes a vector register that allows access to one or more elements at the same time, and an operation between the vector registers. In a vector processing device comprising an arithmetic pipeline, an access pipeline for transferring data between a storage device and the vector register, an instruction processing section, and a pipeline control section, the instruction processing section transfers data to the vector register. A vector register write start signal indicating the write timing of the first element when writing vector data, a vector register write end signal indicating the write timing of the last element of the same vector data, and a vector register write end signal indicating the write timing of the last element of the same vector data. Creates an element enable signal that indicates whether it is valid or invalid, and a register chain detection signal that indicates the read timing of the first element when reading vector data from a vector register, and supplies them to the pipeline control unit. , the pipeline control section includes a first status display means that is set by the vector register write start signal and reset by the vector register write end signal, and a first status display means that is reset by the register chain detection signal and reset by the vector register write end signal. and a third status display means that is set or not set every cycle depending on whether it is enabled or disabled by an element enable signal, and the first and second state display means are It is detected that the vector register is set and the third status display means is not set, and it is assumed that a register chain has occurred and data transfer to the vector register has been interrupted, and at that point, data is read from the vector register. The feature is that control is performed to stop the calculation or access pipeline.

[Embodiments of the invention]

The details of the present invention will be explained below with reference to Examples.

FIG. 4 is an overall configuration diagram of one embodiment of the present invention. In the figure, 1 is the main memory, 2 is the data buffer, 3 is the vector register group VR, 4 is the arithmetic pipeline, 5 is the instruction processing unit, 6 is the pipeline control unit, 7 is the register chain information, and 8 is the pipeline stop Indicates a control signal.

Here, it is assumed that the bus width for loading data from the main memory device 1 to the vector register group 3 is equal to a plurality of elements, and
It is assumed that the timing for writing data to and the timing for reading data from it are stipulated. Therefore, it is necessary to provide a data buffer 2 between the main memory device 1 and the vector register group 3 to temporarily hold data. This data buffer 2
is assumed to be able to hold data for a certain number of cycles.

From the instruction processing unit 5 to the pipeline control unit 6,
Various types of chain information 7 are sent, and based on this information it is determined whether to stop the calculation pipeline. Chain information 7 includes a VR writing start signal,
These include a VR write end signal, an element enable signal, and a register chain detection signal.

FIG. 6 is a diagram showing the generation timing of each of the above signals, and the VR write start signal is a signal that turns ON at the timing when the first element is written to the vector register.
The VR write end signal is a signal that turns ON at the timing when the last element is written. The element validation signal is a signal indicating that the element to be written is valid. Therefore, the above signal and the signal between
When it is OFF, it means that load data is not being sent continuously.

The register chain detection signal is a signal that turns ON at the timing when the arithmetic pipeline 4 is about to read the first element of the vector register group 3. These signals are sent to the instruction processing unit 5
The data is sent to the pipeline control unit 6 every cycle, and it is determined each time whether or not to stop the calculation pipeline 4.

As mentioned above, the timing of writing data to vector register group 3 and the timing of writing data to vector register group 3
The timing to read data from is fixed by the element, so once it stops, it will remain stopped until the next timing comes.
The data read from the main memory during this time is
It is not written to the vector register immediately, but is held in the data buffer. Then, when the stop is released, writing and reading data to and from VR starts again. By controlling in this way, it is possible to maintain the order of vector load instructions and vector operation instructions.

FIG. 5 is a configuration diagram of one embodiment of the pipeline control section 6 that performs the above-mentioned control operation, and FIG. 6 is a timing chart of one example of the operation.

In FIG. 5, 6 is a pipeline control section, 9
11 to 11 are latch circuits, 12 is a fixed cycle hold circuit, 13 is an inverter, and 14 to 16 are
AND circuits 17 and 18 are OR circuits.

The signals in FIG. 5, and A,
B, C, and D correspond to the signal timings with the same numbers shown in FIG. 6, respectively.

Latch circuit 9 is set by the VR write start signal and reset by the VR write end signal to produce signal A.

Latch circuit 10 is set by the register chain detect signal and reset by the VR write completion signal to produce signal C.

Latch circuit 11 is set every cycle by the element enable signal and produces signal B. Signal B is not set and indicates an off state when the element enable signal is interrupted.

The AND circuit 16 takes the logical product of these signals A, B, and C, and turns off the element enable signal, that is, interrupts data transfer, when a register chain occurs during the vector register write period. It is detected and the fixed cycle hold circuit 12 is activated.

Fixed cycle hold circuit 12, when activated, generates a pipeline stop control signal D that stops the clock for a predetermined period of time, controlling the pipeline to stop operation during that period.

〔Effect of the invention〕

As described above, according to the present invention, parallel processing of two vector instructions with register chaining can be executed with high reliability.
It is possible to easily utilize parallel processing and speed up processing.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of the vector processing device, Figure 2 is a timing diagram showing an example of cascade control when there is a chain of vector registers, and Figure 3 is a timing diagram of an example of parallel control in the same case as Figure 2. 4 is an overall configuration diagram of one embodiment of the present invention, FIG. 5 is a configuration diagram of one embodiment of the pipeline control section, and FIG. 6 is a timing diagram of one operation example of the embodiment shown in FIG. 5. It is. In the figure, 1 is the main memory, 2 is the data buffer,
3 is a vector register group, 4 is an arithmetic pipeline, 5 is an instruction processing unit, 6 is a pipeline control unit,
7 is register chain information, 8 is pipeline stop control signal, is VR write start signal, is VR write end signal, is element enable signal,
represents a register chain detection signal.

Claims (1)

[Claims] 1. A vector register that allows one or more elements to be accessed simultaneously, an arithmetic pipeline that performs operations between the vector registers, and a system for transferring data between a storage device and the vector register. In a vector processing device including an access pipeline, an instruction processing unit, and a pipeline control unit, the instruction processing unit generates a vector register write start signal indicating the write timing of the first element when writing vector data to the vector register. , a vector register write end signal that indicates the write timing of the last element of the same vector data, an element enable signal that indicates whether each element written to the vector register is valid or invalid, and a signal from the vector register. A register chain detection signal indicating the read timing of the first element when reading vector data is generated and supplied to the pipeline control unit, and the pipeline control unit is set by the vector register write start signal and finishes the vector register write. A first status display means is reset by a signal, a second status display means is set by a register chain detection signal and reset by a vector register write end signal, and a second status display means is reset by an element enable signal. , a third status display means that is set or not set every cycle due to invalidity, detects the case where the first and second status display means are set and the third status display means is not set, and registers the register. Assuming that a chain occurs and the data transfer to the vector register is interrupted, at that point, control is performed to stop the operation or access pipeline in which data is read from the vector register. Pipeline control method.