JPS582975A - Controlling system for vector data processing device - Google Patents

Abstract

PURPOSE:To perform efficient operations to improve the processing speed, by controlling the clock of an operation pipeline part only when register numbers of a vector register, from which data is read out, and a vector register to which data is loaded coincide with each other. CONSTITUTION:Only when a register number 22 of a vector register, from which vector data is read out, storing vector data to be supplied to an operation pipeline part and a register number 21 of a vector register to which vector data is written by a load pipeline part coincide with each other as the result of comparison, the clock of this operation pipeline part is controlled, and clocks of other operation pipeline parts are not stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention compares a petator a-do instruction with a vector operation instruction that follows it, and when the vector operation instruction uses the vector data 1w of the preceding vector load instruction, The number of elements loaded from the main memory is compared with the number of elements read from the vector register for the operation, and if the difference between the two is a predetermined value, the vector operation instruction [the execution unit Part 4 concerns a control method for a vector data processing device in which the clock of the vector data processor is stopped.

! 1! FIG. 1 to FIG. 4 are for explaining a conventional vector data processing device, and FIG. 1 is a diagram showing an example of the circuit configuration of the vector data processing device.

FIG. 11E2 is a functional block diagram of the vector data processing device, and FIGS. 3 and 4 are time charts illustrating pipeline operations in the vector data processing device.

In Figure 111, 1 is an access control circuit, 2 is an arithmetic pipeline control circuit, 3 and 4 are align circuits (data rearrangement circuits), 5 is a vector register, 6 is a pipe twin arithmetic unit, 7 is a preprocessing circuit for Fi arithmetic operations, Reference numeral 8 indicates an arithmetic circuit and 9#i arithmetic post-processing circuit. The access control circuit 1 controls storage. The align circuit 3 rearranges the next data corresponding to the address of the main memory sent from the storage control device and stores it in the vector register. The align circuit 4 rearranges and sends data to the storage control device in accordance with the address of the data pipe main storage device read from the vector register. A vector register sFi, for example, consists of an 8-way interleaved memory, and a plurality of vector registers each consisting of 91 elements, for example
Elements are stored. Pipeline operator 6F
i.

For example, the figure has a plurality of addition pipeline sections and multiplication pipeline sections.Only one petator register 5 and one pipeline arithmetic unit 6 are shown in the figure, but actual vector data The processing device is, for example, an align circuit 3.
It has four vector registers 5 and four pipeline arithmetic units 6 corresponding to four data buses.

That is, four sets of arithmetic units perform high-speed arithmetic processing on four elements at a time.

FIG. 2 is a functional block diagram of the vector data processing device shown in FIG. 1, in which 6 indicates an addition pipeline section, 10 to 13 indicate an addition pipeline section, and 14 to 17 indicate a multiplication pipeline section.

18 is a vector register control circuit, 19 is a VL counting control circuit, % is a data wait detection circuit, 21 and 22 are a vector register number holding unit, and 23t! Each figure shows a VL stitch number control circuit. Note that the thick line indicates the control line. Note that VL is an abbreviation for vector length.
otJ indicates the element of the operation to be executed. The access control circuit 1 includes a VL counting control circuit 19. Data wait detection circuit 20, vector-register number holding 1
121, and controls memory access of a specified number of elements.
controls the operation sound of elements with a specified number of holes by four pipeline arithmetic units. Vector register control circuit 18c controls four vector registers 5Yr based on vector register numbers.

FIG. 3 is a diagram illustrating the tie-building process when a vector addition instruction is executed. Vector addition instruction.

It contains the formats VA VRt V, Ra VRs. First cycle (#O cycle)
Then, the #0 element of the vector register V& is read and set in the register R, and at the #l site, the #0 element of the VRs is moved to registers R and IK, and the #0 element of the vector register VRa is set. It is set in register Ra1, and in #2 cycle V R
#0 element of m is moved to register Itss, #3
In cycle #0 element of tiVR, undergoes preprocessing necessary for the operation and is moved to register R,, and similarly, #0 element of VRs is preprocessed and transferred to register R, and in cycle #4, V #0 element of Rm and #0 element of v'R4 are added in the arithmetic circuit 8 and set in register R4, and in cycle #5, the addition result is post-processed and set in register RmK.

In cycle #6, the operation result is moved to register &, and in the next cycle, vector register VRIK is written. FIG. 4 is a diagram for explaining the state of calculation of a processed Salel element string in a pipeline manner.

By the way, when executing a vector load instruction, the timing is indeterminate due to conflicts in main memory accesses, inconsistencies in own accesses, and in the case of volatile memory, 7 retrieval operations. The vector register control circuit executes the vector addition instruction from
Although it is possible to perform calculations immediately using data,
Since the timing of main memory access is undefined as mentioned above, conventional techniques have been used to start calculations after loading is complete, or to stop the clocks of all pipeline calculation units when data is no longer supplied. etc. are being adopted. However, such a method cannot improve the processing speed.

The present invention eliminates the above-mentioned drawbacks, and
The purpose of this article is to provide a control method for a Ptor data processing device that allows operations to be performed as efficiently as possible when using vector data loaded from main memory. There is. Therefore, the control method of the vector data processing device of the present invention is as follows.
A vector register, a plurality of types of arithmetic pipeline units that perform vector operations using vector data in the scissor vector register, and a vector register KO-do for vector data read from the main memory. In a vector medium data processing device comprising an access pipeline section and a register number of a load destination vector conflict register specified by a vector load instruction and a register number of a read destination vector threat register specified by a subsequent vector operation instruction. If they match, the difference between the number of elements loaded based on the execution of the vector load instruction and the number of elements read out for the execution of the vector calculation instruction is calculated, and this difference is determined by a predetermined value. When the difference is less than a predetermined value, K executes the vector load instruction and the vector operation instruction in parallel, and when the difference is less than a predetermined value, the clock of the arithmetic pipeline section that executes the vector operation instruction 2 is a block diagram of one embodiment of the invention, 24 is an element difference detection circuit, 25 is a register number -
Reference numeral 26 indicates a clock control circuit t. Note that each dotted line indicates a newly added signal line and a control line t.

The element difference detection circuit 24 calculates the difference between the number of elements loaded from the main memory into the four vector registers 5 and the number of elements read from the vector register. This element difference detection circuit 2
4 is composed of, for example, a normal subtraction circuit. The register number-scattering product output circuit 25 calculates the vector register number specified by the vector/μm instruction and the vector containing the read vector data specified by the vector operation instruction - the vector of the register.・Register number and t
It compares and detects a match. The four-wheel control circuit 26 includes an element difference detection circuit 26 and a circuit 26tf.

(b) The element difference is smaller than the number of elements (for example, 4) that can be calculated in one machine cycle.

(b) The register numbers must match.

(c) When all the conditions such as access to all elements by the access control circuit IK have not been completed, the operation is executed by the arithmetic tube using the vector element loaded from the 1K storage device. Stop the big line section. In other cases, the vector load instruction and the vector operation instruction are executed in parallel.01+Other unrelated operation circuits can also operate.

As is clear from the above description, according to the present invention, the load pipeline section and the arithmetic pipe twin section can operate independently69, and the clock control of the arithmetic pipeline section is performed only when the arithmetic pipeline section is used. Since the clocks of other arithmetic pipeline units are not stopped, the performance of the vector data processing device is improved.

[Brief explanation of the drawing]

1 to 4 explain a conventional vector data processing device, and FIG. 1 is a diagram showing an example of the circuit configuration of the vector data processing device. Figure 2 is a functional block diagram of the vector data processing device.
FIGS. 3 and 114 are time charts illustrating the line operation in the vector data processing device. FIG. 5 is a block diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Access control circuit, 2... Arithmetic pipeline control circuit, 3 and 4... 7247 circuit (data sorting circuit) 5... Beta 1 register, 6... Pipeline computing unit, 7... Preprocessing circuit, 8... Arithmetic circuit,
9 post-processing circuit, 10 to 13... addition pie f 5
'In part...day-waiting detection port-121 and n...
Behar register number holding section, n...vL counting control circuit, 24... Element difference detection circuit, 25... Register number-scattering output circuit, 26... Clock control circuit. Patent Applicant: Fujitsu Limited Representative Patent Attorney Yotsube Kyotani

Claims (1)

[Claims] A vector register and a pipe-twin unit that performs a plurality of types of calculations using vector data in the #vector register; In a vector data processing device equipped with an access pipeline unit that reads a vector register, the register number of the load destination vector register specified by a vector destruct instruction, the subsequent vector, and an arithmetic instruction are used. Specified read destination vector
If the register <7'' star number matches, the number of elements loaded based on the execution of the vector operation instruction and the number of elements read out based on the execution of the vector operation instruction are calculated. If this difference is greater than or equal to a predetermined value, the vector load instruction and the vector calculation instruction are executed in parallel, and when this difference is less than a predetermined value, -#imt*vector is calculated. A control method for a vector data processing device characterized by stopping a clock cycle of an arithmetic pipeline unit that executes arithmetic instructions.