JPS60181922A - Information processing device - Google Patents

Abstract

PURPOSE:To increase a processing speed, and to reduce a cost by providing an information accumulating part between successive information processing parts, and controlling a write start of the next instruction by monitoring each state of each continuous instruction. CONSTITUTION:In a multiprocessing device which has cascaded plural information processing parts, such as a vector processing deviece, an aligned information accumulating part 14 is provided between its align-processing part 12 and a VR write processing part 15, and also an aligned control information accumulating part 16 and a write address holding part 17 are provided between an align-processing control part 13 and a VR write control part 18. In this regard, a write/read-out address counter having a counter function is provided on a data bus circuit of the aligned information accumulating part 14, and set and counted up from the control part 13. In this state, in order to discriminate each processing state of an instruction, a data quantity written in each instruction and a read-out data quantity are monitored, respectively, and whether the next instruction can be executed or not is determined by checking whether a difference to the total data quantity presence or absence.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an information processing device in which a plurality of processing stages are connected in series, and in particular to an information processing device that monitors the input/output status of processing in the processing stages to improve the multiprocessing rate. The present invention relates to an information processing device equipped with means for controlling.

[Technology background]

In an information processing device, such as a vector processing device, in which a plurality of information processing sections are connected in series, processing of a plurality of instructions is continuously passed to the sequential information processing sections, and multiple processing is performed.

Conventionally, in order to transfer the information necessary for processing an instruction from an information processing unit at one stage to an information processing unit at the next stage (for example, a buffer), the information processing unit at the next stage finishes processing the previous instruction. and was required to be vacant. Therefore, if the next stage is processing, the previous stage cannot transfer information until the next stage completes processing, and the next stage cannot start until the next stage completes the processing, resulting in a decrease in the overall processing speed. Ta.

[Object and structure of the invention]

An object of the present invention is to enable, in a plurality of cascaded information processing units, an information processing unit at the previous stage to start the next process without requiring the information processing unit at the next stage to become vacant. The purpose is to improve overall processing.

Therefore, in the present invention, an information storage section is provided between successive information processing sections, and the processing information of the instruction is sequentially written in the information storage section, and the state changes from ``sWritten'' to ``Reading''. Pay attention to which of the above states each successive instruction is in, and check if the information f15 of the preceding instruction is "written" or "reading".
A means is provided for controlling the writing of the next instruction to be started when the following instruction occurs, and the configuration thereof is used in an information processing apparatus in which a plurality of information processing units are connected in cascade and multiple processing is performed. Between the information processing section and the next-stage information processing section, one or more first and second information processing sections are provided, each storing control information necessary for processing in the next-stage information processing section.
control information storage units are provided, at least one of the first control information storage units stores the amount of processing processed each time the processing of a certain information processing unit is completed, and one of the second control information storage units The information in the first control information storage section is retained at the stage when a series of processing is completed in a certain information processing section, and when at least one of the second control information storage sections has valid information, A processing start instruction is given to the next stage information processing unit, and if all the information in the second control information storage unit is invalid, the first information processing unit recognizes that the information has been stored, and then The present invention is characterized in that a processing start instruction is given to the information processing section of the second stage.

[Principle of the invention]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 5A shows the status sequence of instruction processing information, which is numbered as follows: ①Writing - ③Written → ②Continuous writing. FIG. 3C shows an example of control timing when instructions A, B, and C are successively given to an information processing section having a certain buffer function.

Here, instruction B is enabled to write its own processing information when the processing information of the preceding instruction has been written to ■.
is being written, and instruction C is enabled to write its own processing information on the condition that the processing information for the instruction is being continuously written as ■, and the processing information for instruction B has been written as ■. ■Writing is in progress.

In general, before the information processing unit completes the processing of one or more preceding instructions, it individually determines the processing status of these preceding instructions to execute the next one or more instructions. can do.

The number of instructions that can be executed depends on the capacity of the buffer in the information processing section, the writing speed, the reading speed, the length of processing information for each instruction, and the like.

Figure 2 ((), (o), and (c) conceptually shows an example of processing information transferred via the information storage section. In this example, the processing section tab is relatively short. , processing information C
is for a relatively long case. W is a write terminal, R is a read terminal, a, b, and c are processing information for instructions A, B, and C, respectively, and ■, ■, and ■ are the states shown in FIG. 1(a).

In (A) of FIG. 2, processing information a is in the process of writing ■, processing section @b has already written ■, and processing information C is in the process of writing ■. After a predetermined period of time, as shown in (I+) in the same figure, the reading of the processing information a is completed, and the processing information a is read out.
are being published one after another. At this time, processing information C is still being written. Thereafter, as shown in FIG. 3(C), the processing information is completely outputted one after another, and reading of the processing section v11c is started. At this time, processing information C is in the process of being written as ■, but when read, it becomes written as ■.

From the above example, in order for the processing information of a certain instruction to be able to be written to the information storage unit, at least the processing information of the immediately previous instruction must have been written, and furthermore, the processing information must already exist in the information storage unit. If it is, you know that it is OK if it is being read.

In order to identify each processing state of such an instruction, the amount of data written (for example, the number of elements) and the amount of data read for each instruction are monitored, and the difference from the total amount of data (
A means is provided to check whether there is a difference in length from the length of the processing information, and based on the result, it is determined whether or not the next instruction can be executed.

[Embodiments of the invention]

Next, details of the present invention will be explained according to examples. FIG. 3 is an overall configuration diagram of a vector processing device that is an embodiment of the present invention. In the figure, 1 is a main storage unit (represented as MSU), 2 is a storage control unit (represented as MCU), 3 is an access pipeline, 4 is a vector register (represented as VR), 5 is an adder, and 6 is a multiplier. , 7 is a divider, 8 is an instruction control unit, 9 is a REQ signal to the MCU, 10 is control information added to data, and 11 is load or store data.

FIG. 4 is a main part configuration diagram centered on the access pipeline 3 shown in FIG. 3. In the diagram, 4-○ to 4-3
12 is an alignment processing section, 13 is an alignment processing control section, 14 is an aligned information storage section provided based on the present invention, and 15 is a VR writing processing section.

The alignment processing section 12 and the VR writing processing section 15 correspond to two information processing sections that are the object of the present invention, and the aligned information storage section 14 corresponds to the information storage section.

Four elements of vector data are simultaneously transferred in parallel, and therefore the bus, align processing section 12, aligned information storage section 14, VR write processing section 15, and VR4 each have a four-system configuration.

A summary of the operation of the apparatus shown in FIGS. 3 and 4 is as follows.

In the access pipeline 3, when an instruction is started in the instruction control unit 8, 5TART (start) and OPC (operator) are sent to the supplied access pipeline 3.
Based on signals from the instruction control unit 8 such as John code), vL (vector length), address, etc., an address of MSU1 start address + nX inter-element distance = RQ is generated, and RQ is transmitted for VL.

In MCU2, RQ and O from access pipeline 3
Based on PC, address, MSU in case of load instruction
The specified address is read. The read vector data is input to the access pipeline 3 via the MCU 2.

In access pipeline 3, vector register VR4
(4-0 to 4-3) are configured in the order of elements, so the alignment processing unit 12
corresponds to a request address that has an interface with 4
Conversion is performed to rearrange the buses for the elements so that the vector data is in the order of the elements.

The aligned vector data is once written to the position indicated by the write address in the aligned information storage unit 14.

If the vector register VR4 (4-0 to 4-3) is interleaved (in the illustrated example, it is interleaved into 8 banks), the vector register VR4 is stored in the aligned information storage unit 14 until it becomes accessible. Since the vector data is not read out, the aligned information storage unit 1 is stored so that other vector data can be written during that time.
4 has a multi-stage buffer configuration.

If the vector register VR4 is found to be accessible, it is read from the aligned information storage section 14 and written to the vector register VR4 via the VR write processing section 15.

Next, a mechanism for controlling writing and reading vector data to and from the aligned information storage unit 14 will be explained. Fifth
The figure is a schematic diagram thereof, and elements 4 and 12 to 15 are the same as shown in FIG. Further, 16 is an aligned control information storage section, 17 is a write address holding section, and 18 is a VR write control section.

Corresponding to the fact that the aligned information storage section 14 is provided between the alignment processing section 12 and the VR writing processing section 15,
C. An aligned control information storage section 16 and a write address holding section 17 are provided between the alignment processing control section 13 and the VR writing control section 18. The data bus circuit in the aligned information storage unit 14 is provided with a write address register and a continuous address register having a counter function, as described later in FIG. It has become.

Further, the aligned control information storage unit 16 and the write address holding unit 17 are configured so that they can be controlled by distinguishing between writing and writing, as will be described later with reference to FIGS. 7 and 8, respectively. The processing section can be operated using only the control signal.

The alignment processing control unit 13 generates an alignment control signal necessary for alignment processing from a control signal necessary for alignment given by the MCU. Additionally, aligned control information is output for each alignment process. Align processing section 12
performs alignment based on a signal from the alignment processing control unit 13 and a load data command.

The aligned control information storage unit 16 can know the number of aligned data from the aligned control information, and the write address holding unit 17 sets the write address to the aligned information storage unit 14. ,
The aligned data is held and the data is transferred to the VR write processing section 15 by giving a read address.

The aligned information storage unit 14 accesses aligned data using only write addresses and read addresses.

When it is learned from the information in the aligned control information storage section 16 that readable data exists, read control is performed in accordance with the VR write timing, and a VR write control signal is created using the read control signal.

The VR write processing unit 15 writes vector data to the VR using the read data from the aligned information storage unit 14 and the VR write control signal.

FIG. 6 is a detailed configuration diagram of the -7 line completed 111 information storage section 14 shown in FIG. In the figure, 141-0 to 141
3 is an aligned register stack (not expressed as AR3), 1
42-0 to 142-3 indicate write address registers that function as counters, and 143-0 to 143-3 indicate successive address registers that similarly function as counters.

The write address registers 142-0 to 142-3 and the read address registers 143-0 to 143-3 are initialized with a write address and a read address for each instruction, and thereafter the contents of the write address registers are changed for each alignment process. The read address register is counted up by +1 each time a read is performed. As a result, data input from the alignment processing section 12 is written to the AR 3 in the manner illustrated in FIG. 2, and then read out to the VR writing processing section 15 in the order in which it was input.

FIG. 7 shows the aligned control information storage section 1 in FIG.
FIG. 6 is a detailed configuration diagram of No. 6. In the figure, 161 is an adder, 162
is a subtracter, 163 is a writing number register, l 64-
0 to 164-3 are written number registers, 1
65 is a selector, 166 is a subtracter, 167 is a readout number register, 168 is an AND gate, and 169 is an inhibit gate.

When alignment processing is performed in the alignment processing section 12,
The number of VALID data (elements) among them is notified to the aligned control information storage unit 16. When VALID data is written to AR3141-(1 to 141-3 in FIG. 6), the number is given to one input of the adder 161.The other input of the adder 161 is
The number of VALI'D data written so far in the number-of-writes register 163 is given by a loop through an AND gate 168. Both are added by an adder 161, and the result is stored in the number-of-writes register 163 again.

In this way, the number of data written to AR3 is accumulated in the number-of-writing-in register 163.

AND gate 16B turns off signal AR3WC once when starting writing to AR3, disconnects the signal loop from write-in-progress number register 163, and switches register 162
It has the function of clearing.

As in the example shown in FIG.
The contents of 3 must be reduced. Subtractor 162 and inhibit gate 169 are then activated. AR3R
D is a signal given when a continuation is performed from AR3, and AR3EQ is a signal turned off when AR3 is writing and reading the same instruction. Therefore, each time AR3RD is turned on while signal AR3EQ is off, the number of bits being written is counted down by 4, for example.

When all the writing to AR3 for one instruction is completed, the reading is on standby, so the write-in-progress small value in the write-in number register 163 is transferred to the written-in number registers 164-0 to 164-3 at the end of the loop. any one of
will be moved to In the illustrated example, the written number register 16
4-0 to 164-3 can hold the number of written instructions for up to four instructions. To select the number of written registers, apply a clock (
(not shown).

The selector 165 selects one of the writing number register 163 or the written number registers 164-0 to 164-3 corresponding to the instruction to be read, and applies the selected register to the subtracter 166. When the AR3 read processing of a certain instruction is completed, first the written number register 1 is
Check whether the contents of any one of 64-0 to 164-3 are valid (unprocessed), and if valid, VR
A processing start instruction is given to the write processing unit 15.

On the other hand, if the contents of each written number register are all invalid (processed), next check the contents of the number of pieces being written register 163, and if it is valid, start the VR writing process. A processing start instruction is given to the unit 15. As a result, one register having information on the written number of instructions to be executed is selected. That is, if there is an instruction for which AR3 writing has been completed, data reading from that instruction is executed preferentially, and if there is no instruction, data for an instruction currently being written is read. Subtractor 166, readout number register 1
67 and selector 165 is AR3
Each time the read signal AR3RD is applied, that is, each time a read is performed, the output of the selector 165 is counted down by 4, for example.

FIG. 8 shows the 1-include address holding unit 17 in FIG. 5.
FIG. In the figure, 171 is an adder, 172
are write start address registers, 173-0 to 173
-3 is a read start address register, 174 is a selector, 175 is a read start address output register, and 176 is a write address register 164. -0 to 16
This is a control register that instructs the count amplifier 4-3.

Adder 171 and write start address register 172
recognizes the write address of AR3 that will occur at the next timing based on the aligned control information from the align processing control unit, and for example, when the processing of one instruction unit is completed, the write start address of the next instruction is determined. are given to write address registers 142-0 to 142-3 in FIG.

This address is read start address register 1 at the same time.
73-0 to 173-3 and retained for later use as a read start address for each instruction.

The selector 174 selects read start address registers 173-0 to 173-0 to 173-0 to 164-3 in synchronization with the selector 165 in FIG. 17
3-3 is selected and its read start address is output.

FIG. 9 is a state transition diagram of an example of an algorithm that generally controls the data transfer operation of the aligned information storage unit 14. In the figure, WAQ is the written number register 1
Indicates the number of instructions held in 64-0 to 164-3, W-AB indicates that it is being processed in the writing number register 163, and WAS and W to E indicate instructions in the previous align processing section. 5TART o,
and END, and RAE is a signal representing the next stage VR
This is a signal representing the END of processing in the write processing section 15, and the X mark means the opposite signal.

Although the present invention has been described above using a vector processing device as an example, the present invention can be widely applied to general processing devices having a plurality of cascaded processing units.

〔Effect of the invention〕

According to the present invention, the next process can be started in the previous stage information processing unit even if the next stage information processing unit does not become vacant. Therefore, the overall processing speed is increased, and by simplifying the information processing section, it can be realized by providing multiple circuits with the same function, making it possible to design common circuits and reduce costs. .

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram showing an example of the state of processing information transferred via the information storage unit, and Fig. 3 is an explanatory diagram of a vector processing device which is an embodiment of the present invention. Overall configuration diagram, Figure 4 is a configuration diagram of main parts centering on the access pipeline in Figure 3, Figure 5 is a schematic diagram of the write/read control mechanism for vector data to the aligned information storage unit, and Figure 6 is a detailed configuration diagram of the aligned information storage section, FIG. 7 is a detailed configuration diagram of the aligned control information storage section, FIG. 8 is a detailed configuration diagram of the write address holding section, and FIG. 9 is a detailed configuration diagram of the aligned information storage section. It is a state transition diagram of transfer control. In the figure, 4 is a vector register VR, 12 is an alignment processing section, 13 is an alignment processing control 11 section, 14 is an aligned information storage section, 15 is a VR write processing section, 16 is an aligned control information storage section, and 17 is a writing section. address holding section, 18
indicates a VR write control section. Patent Applicant Fujitsu Limited Representative Patent Attorney Obu Hase (one other person) Figure 1 (A) (B) Figure 2 Figure 8 Official Letter of Dispute in Figure Proceedings (at the time of request for examination) March 18, 1985 1982 Patent Application No. 038415 2, Name of the invention Information processing device 3, Relationship with the amended person case Patent applicant address 1015 Kamiodanaka, Nakahara-ku, Yozaki City, Kanagawa Prefecture Name (522) Representative of Fujitsu Limited Takuma Yamamoto 4, Agent address 4-17-1-5 Nishi-Nippori, Arakawa-ku, Tokyo Number of inventions to be increased by amendment None 6 Subject of amendment [Claims 11゜Contents of amendment ( 11 The scope of claims is amended as follows: [In an information processing apparatus in which a plurality of information processing units are cascade-coupled and perform multiple processing, one information processing a11 and the next stage information!
[One or more first and second control information storage sections are provided between the third processing section and the first and second control information storage sections that accumulate the control information necessary for the processing that goes to the next stage information processing section, respectively. At least one of the first control information storage units stores the processing amount processed each time the processing power of a certain information processing unit changes, and one of the second control information storage units stores the amount of processing processed every time the processing power of a certain information processing unit changes. The information in the first control information storage section is held at the stage when the processing of is completed. If at least one of the second control information storage units has valid information, it instructs the next stage information processing unit to start processing by -5. When all the information in the control information storage unit is invalid, the LSI first step 1uvlN order', Qj country' i By recognizing that the information has been accumulated, it fires up the information processing unit in the next stage and instructs it to start processing. -5
An information processing device characterized by being able to display 1 (2) On page 4, line 15 of the specification, "information processing section" is corrected to "information in control information storage section."that's all.

Claims (1)

[Claims] In an information processing device in which a plurality of information processing units are cascade-coupled and multiplexed processing is performed, control necessary for the processing that goes to the next information processing unit is provided between one information processing unit and the next information processing unit. One or a plurality of first and second control information storage units each storing information are provided, and at least one of the first control information storage units is processed each time a certain information processing unit completes processing. The processing amount is accumulated, and one of the second control information storage units retains the information of the first control information storage unit at the stage when a series of processing is completed in a certain information processing unit, and the second control information storage unit If at least one of the information storage units has valid information, an instruction to start processing is given to the next information processing unit, and if all the information in the second control information storage unit is invalid, the second control information storage unit instructs the next information processing unit to start processing. An information processing apparatus characterized in that, by recognizing that one information processing section has been stored, a processing start instruction is given to the next information processing section.