JPS6343782B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a storage control method in a vector data processing device, and in particular, in executing a vector data access instruction to a main memory, a plurality of consecutive instructions are sequentially and This invention relates to a storage control method for multiple execution.

[Technology background]

Vector computers can process large amounts of data at high speed. Therefore, it is necessary to supply data continuously, and a method is generally used in which data is directly transferred between the main memory and a register or an arithmetic unit without using a buffer memory.

At that time, main memory access time becomes a problem. For example, in the case of a vector load instruction, the first
As seen in the example basic time chart in the figure, several tens of cycles are required between generating an address and writing the fetched data to the vector register VR or mask register MR.

Therefore, when executing vector load instructions consecutively, if the next vector load instruction is issued after the write operation to VR is completed as in the past, as shown by T _D in Figure 2, Sometimes there will always be a delay of several tens of cycles. Therefore, if consecutive instructions are executed in an overlapping manner, processing efficiency can be improved.

[Object and structure of the invention]

An object of the present invention is to provide a means for continuously executing multiple vector access instructions and to improve efficiency. In a vector data processing device, the access pipeline has a plurality of sequential stages that manage instructions and a plurality of sequential stages that manage instructions and execute each operation independently. control blocks, some of the plurality of sequential stages include exclusive parallel stages, and are used to hold instructions pending processing; generating an identifier for each instruction in the first stage and sending the identifier along with the instruction code to each successive stage and control block to be activated;
It is characterized in that it is held in one of the exclusive parallel stages determined by the identifier.

[Embodiments of the invention]

The present invention will be explained below using examples.

FIG. 3 is a block diagram showing the general configuration of the data and address system of the storage control unit in a vector data processing device, and FIG. 4 is a block diagram showing the configuration of the control system according to an embodiment of the present invention. .

In Fig. 3, 1 is an access pipeline;
2 is a vector register, 3 is a mask register, 4
5 is an alignment unit for converting boundaries of multiple element data; 5 is an address operation unit that generates a start address for segment data and performs logical address/real address conversion; 6 is a main memory control unit; and 7 is an ECC generation and check unit. 8 is a block that includes an address spine line for controlling the priority of access requests to the main memory and timing adjustment during partial stores; 9 is a main memory block; It is.

In FIG. 4, blocks 10 to 14 are
These are the stages of the pipeline that sequentially shift the supplied instructions, 10 being the A stage, 11
is the B stage, 12 is the C0 stage, and 13 is the C1 stage. Further, 10a is a 2-bit counter for adding an identifier to sequential instructions supplied. Blocks 14 to 20 are control blocks, 14 is an address control block, 15 is a register read control block, 16 is a main memory control interface, 17 is an align control block, 18 is an align buffer write control block, and 19 is a Align buffer read control block 20 indicates a register write control block.

Next, the operation of the embodiment will be explained with reference to FIGS. 3 and 4.

When a vector load instruction is issued from the instruction control unit, the instruction enters the A stage 10 and simultaneously activates the address control block 14. The address control block 14 controls the address operation unit 5 to generate addresses for a specified number of elements.
Address conversion and a request to the main memory control unit 6 are performed. The instruction moves from the A stage 10 to the B stage 11, activates the alignment control block 17, and moves to the C stage. The C stage consists of a C0 stage 12 and a C1 stage 13, and an instruction is input to either one according to an identifier added to the instruction.

The align control block 17 sends a control signal for aligning data to the align unit 4 in response to a data transfer wake-up (DTW) signal from the main memory control unit 6 that notifies fetch data, and in the next cycle, the align buffer write control block 18 is activated, and the alignment result is put into the alignment buffer in the alignment section 4.

In the next cycle, the align buffer read control block 19 is activated and the vector register 2 is activated.
When the writing timing comes, the aligned result is read from the alignment buffer and is notified to the register write control block 20. Register write control block 20 writes to the address of vector register 2 held in C stage 12 or 13.

The next command is sent to the address control block 14.
However, this is possible if the last address generation of the previous instruction has been completed, and at that time, the instruction has moved to the B or C stage, so it can be entered into the A stage 10.

In a vector load instruction with a small vector length (data size), the first instruction is writing to the vector register, the second instruction is in the alignment buffer after alignment, and the third instruction is in the alignment process. There is. Even in such a vector load instruction with a small vector length, in order to enable pipeline execution of three instructions, the C stage is divided into two stages, C0 and C1, as shown in the figure.
By providing two in parallel, aligned instructions can be held.

The C0 stage 12 and the C1 stage 13 sequentially count input instructions using the 2-bit counter 10a of the A stage 10, and add the values to the instructions as identifiers. When the lower bit is “0”, it goes to the C0 stage, and when it is “1”, it goes to the C1 stage.
Selectively store to stage. Furthermore, the identifier can be sent to each control block to facilitate synchronized control of the stage and the control block. Also 3
When the second instruction moves from the B stage to the C stage, it is sufficient to check in advance whether the C0 stage or the C1 stage is vacant using the identifier.
Note that the above-mentioned C stage is not limited to two, C0 and C1, but can be composed of any number of parallel stages.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to multiplexly control the access pipeline using a plurality of instructions in main memory access of vector data, and the processing speed of a vector data processing device can be improved.

[Brief explanation of the drawing]

Fig. 1 is a basic time chart of a vector load instruction, Fig. 2 is a conventional sequence diagram when vector load instructions are executed continuously, Fig. 3 is an example configuration diagram of a storage control unit of a vector data processing device, and Fig. 4 The figure is a configuration diagram of an embodiment of the control system. In the figure, 1 is an access pipeline, 2 is a vector register, 3 is a mask register, 4 is an alignment unit for converting boundaries of multiple element data, and 5 is a start address generation and logical address/real address for segment data. 6 is a main memory control unit; 7 is an address operation unit that performs conversion;
8 is a data manipulation unit that performs ECC generation and checking or merging processing during partial store, and 8 is a block that includes an address pipeline for controlling the priority of access requests to the main memory and adjusting timing during partial store. , 9 is main memory, 10 is A stage, 11 is B stage, 12 is C0 stage, 1
3 is the C1 stage, 10a is a 2-bit counter for adding an identifier to the supplied sequential instructions, 14 is an address control block, 15 is a register read control block, 16 is a main memory control interface, and 17 is an alignment control block. block, 18
19 is an align buffer write control block, 19 is an align buffer read control block, and 20 is a register write control block.

Claims (1)

[Scope of Claims] 1. In a vector data processing device including a vector register, a main memory, and an access pipeline that transfers data between the vector register and the main memory, the access pipeline manages instructions. a plurality of sequential stages, and a plurality of control blocks that are activated by different stages to independently perform their respective operations; some of the plurality of sequential stages include:
The first stage of the plurality of sequential stages generates an identifier for each instruction and uses the identifier as an instruction code. A vector data storage control system characterized in that the vector data is sent to each successive stage and activated control block, and is held in one of the exclusive parallel stages determined by the identifier. 2. In paragraph 1 above, the identifier generated in the first stage of a plurality of sequential stages is sent to the sequential stages and the activating control block, and these sequential stages and activating control blocks use the identifier. A vector data storage control method characterized in that each stage and control block are managed by a vector data storage control method.