JP2622026B2 - Register writing control method in central processing unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a register write control method in a central processing unit that controls a write process of a master register and a copy register provided in a central processing unit, a master register and a copy register are described in one pipeline flow. The instruction control unit provided in the central processing unit is configured to issue a command instructing simultaneous loading to both the master register and the copy register, and to execute the writing process of the master register. By providing a transfer bus for transferring data to be loaded into the register to the store bus of the copy register, and an activating means for activating the transfer bus when a simultaneous instruction command is issued, the data is fetched from the storage control unit. Data is written to both the master register and the copy register at the same time.

[Industrial applications]

The present invention relates to a register write control method in a central processing unit that controls a write process of a master register and a copy register provided in a central processing unit, and in particular, a write process of a master register and a copy register in one pipeline flow. And a register write control method in the central processing unit which enables the execution of the program.

In the central processing unit, the instruction control unit or the execution control unit has a master register of a control register which is connected to the write / read bus of the instruction control unit and the execution control unit and can be loaded / stored from software. In addition to configuring the execution of load / store instructions efficiently,
A configuration is adopted in which the register of the copy is connected to the store bus, held in the storage control unit, and used for controlling storage area access. The processing of loading data into these master and copy registers must be configured to be executed as fast as possible in order to increase the processing efficiency of the central processing unit.

[Conventional technology]

Conventionally, when a load instruction to these registers is issued, as shown in FIG. 5, the instruction control unit and the storage control unit first fetch (FETCH) the pipeline flow.
Is displayed, the load data is fetched from the local buffer storage (LBS) according to the ACCS code, and the fetched load data is latched in the operand write register (OWR) provided in the input stage of the arithmetic unit. After that, the result is latched in a result register (RR) provided in the output stage of the arithmetic unit, and is loaded into the master register in a subsequent write cycle. Then, in the next pipeline flow, an ACCS code indicating a SET is sent to the instruction control unit and the storage control unit, and the load data latched in the result register is stored in the store data register (STDR) according to the ACCS code. ), And by loading the data into the copy register in the subsequent write cycle, the master register executes the processing of loading the copy register.

[Problems to be solved by the invention]

As described above, in the prior art, two pipeline flows were required for the loading process for one set of the master register and the copy register. Thus, there is a problem that the processing efficiency of the central processing unit is reduced.

The present invention has been made in view of such circumstances,
It is an object of the present invention to provide a register write control method in a new central processing unit that can execute a write process of a master register and a copy register in one pipeline flow.

[Means for solving the problem]

 FIG. 1 is a diagram illustrating the principle of the present invention.

In the figure, 1 is a central processing unit equipped with the present invention, 2 is an instruction control unit provided in the central processing unit 1, provided with a master register 4, 3 is a storage control unit provided in the central processing unit 1, , A copy register 5.
Here, the master register 4 may be provided in an execution control unit of the central processing unit 1 (not shown).

Reference numeral 6 denotes a command decoding unit provided in the instruction control unit 2,
7 is a device for decoding and issuing a command having a processing request, 7 is a data storage unit provided in the storage control unit 3 for storing load data and the like to be loaded into the master register 4 and the copy register 5, and 8 is an instruction control unit. A register provided in the unit 2 for latching load data to be loaded into the master register 4; a register 9 provided in the instruction control unit 2 for latching the load data fetched from the data storage means 7; What to enter in 8, 10
Is a register provided in the storage control unit 3 for latching load data to be loaded into the copy register 5;
Is a transfer bus which transfers load data input to the register 8 to the register 10, and 12 is an activating means constituted by, for example, a selector, which activates the transfer bus 11.

[Action]

In the present invention, the command decoding means 6 is configured to issue a command instructing simultaneous loading to both the master register 4 and the copy register 5. Upon receiving the command of the simultaneous load instruction, the activating means 12 activates the transfer bus 11 at the timing when the load data fetched from the data storage means 7 is transferred from the resist 9 to the resist 8. , The load data latched in the register 8 is also latched in the resist 10 at the same time. By latching in this manner, load data can be written to both the master register 4 and the copy register 5 at the same time.

As described above, in the present invention, the load data fetched from the storage control unit 3 can be written into the master register 4 and the copy register 5 provided in the central processing unit 1 by one pipeline flow.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 2 shows an embodiment of a hardware mechanism of the central processing unit 1 constructed according to the present invention. In the figure, the same components as those described in FIG. 1 are denoted by the same symbols, and the portion indicated by the pipeline flow of DATBEW shown in the upper part is provided in the instruction control unit 2 described in FIG. The hardware mechanism, and the lower part of the PTBRWS shown by the pipeline flow are the hardware mechanisms included in the storage control unit 3 described in FIG.

20 is an instruction buffer for storing an instruction code, 21 is a base register for storing base information described in the instruction code, and 22 is an index register described in the instruction code. 23, which stores index information, 23 is a displacement register, which stores displacement information,
Reference numeral 24 denotes an effective address adder, which is base information held by a base register 21, index information held by an index register 22, and a displacement register 23.
A virtual address to be accessed is obtained by adding the displacement information held by the effective address register 25, an effective address register 25 for storing a virtual address calculated by the effective address adder 24, and a local address register 26. A buffer storage for storing a copy of the main memory data, 27 a control storage for outputting processing type information (ACCS code) of the instruction code, 28-i an ACCS register, The ACCS code output from the control storage 27 flows through the pipeline.

29 is an operand write register that latches data read from the local buffer storage 26, 30 is a first operand register that latches data to be operated on read from the master register 4, and 31 is a first operand register. A two-operand register that latches data to be operated on read from the master register 4. An operation unit 33 that constitutes an execution control unit performs arithmetic processing (input processing for loading to the master register 4) on input data. Sometimes, the data held in the operand write register 29 is output as it is) and a result register 34 is a result register,
35, a store data register for latching data to be loaded into the copy register 5, and a selector 36, which is an ACCS register 28.
−i, the data stored in the operand write register 29, the data stored in the first operand register 30, the data stored in the second operand register 31,
Is selected and transferred to the store data register 35.

The present invention is characterized in that the control storage 27 newly outputs an ACCS code of "FETCH &SET", and the selector 36 newly selects data held in the operand write register 29. The feature is that a configuration is adopted in which data held in the operand write register 29 can be transferred to the store data register 35 by outputting the data.

FIG. 3 shows an embodiment of a circuit for generating a control signal issued when the newly provided ACCS code “FETCH & SET” flows through the pipeline flow of DATBEW.

As shown in this figure, when the decoder detects that the ACCS code of “FETCH” or the ACCS code of “FETCH & SET” flows to the B stage of the pipeline, it is transmitted from the storage control unit 3. At the timing of the FETCH_DATA_VALID signal indicating that the fetch data is valid, the clock of the operand write register 29 is activated, and the data read from the local buffer storage 26 is loaded into the operand write register 29. Here, the ACCS code “FETCH” is a code for instructing that the data is loaded into the master register 4 and the copy register 5 by the conventional two-by-line flow.

And, by the decoder, AC “FETCH & SET”
When the CS code is detected to flow into the E stage of the pipeline, the SEL_OWR_TO_STDR signal is sent to the selector 36, thereby controlling the selector 36 to selectively output the data held in the operand write register 29. As a result, the data held in the operand write register 29 is processed to be taken into the store data register 35.

Then, an ACCS code of "EXCEPTION" indicating exception handling, an ACCS code of "MACHINE_CHECK" indicating machine check, or "CL" indicating a pipeline clear instruction.
When it is detected that the ACCS code “EAR_PIPELINE” flows into the pipeline, processing is performed so as to suppress the loading into the master register 4 by transmitting an INH_REG_WRITE signal. Further, when the INH_REG_WRITE signal is being transmitted, decoding causes an ACCS
When it detects that the code or the ACCS code “FETCH & SET” flows into the W stage of the pipeline,
By sending the ORE_SUPPRESS signal, the copy register 5
Process to suppress the load to.

Thus, in the present invention, as shown in FIG.
Operand write register at B stage of pipeline
29, the data read from the local buffer storage 26 is processed to be fetched into the operand write register 29. At the E stage of the pipeline, the selector 36 sets the operand newly input according to the present invention. By controlling the data held in the write register 29 to be selectively output, the data held in the operand write register 29 is taken into the master register 4 and simultaneously into the store data register 35. With the line flow, the load processing for the master register 4 and the copy register 5 can be executed.

[Effects of the Invention] As described above, according to the present invention, load data fetched from the storage control unit can be written to the master register and the copy register provided in the central processing unit by one pipeline flow. Therefore, the processing efficiency of the central processing unit can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is an embodiment of a hardware mechanism of a central processing unit constituted by the present invention, FIG. 3 is an embodiment of a control signal generating circuit, FIG. Is an explanatory diagram of the process of the present invention, and FIG. 5 is an explanatory diagram of the prior art. In the figure, 1 is a central processing unit, 2 is an instruction control unit, 3 is a storage control unit, 4 is a master register, 5 is a copy register, 6 is a command decoding unit, 7 is a data storage unit, 11 is a transfer bus, and 12 is a transfer bus. It is an activation means.

Claims (1)

(57) [Claims] An instruction control unit (2) or an execution control unit has a master register (4), a storage control unit (3) has a copy register (5), and a command issued by the instruction control unit (2). Fetches data from the storage control unit (3) in accordance with
And a central processing unit provided in the data processing device for processing to load the data into the copy register (5). The instruction control unit (2) transmits the data to the master register (4) and the copy register (5). And a transfer bus (11) for transferring data to be loaded to the master register (4) to a store bus of the copy register (5). An activation unit (12) for activating the transfer bus (11) when a command is issued includes data fetched from the storage control unit (3) and the master register (4). A register writing control method in a central processing unit, characterized in that processing is performed so that data is written to both copy registers (5) at the same time.