JP2806690B2 - Microprocessor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor of a pipeline control system in which instruction execution is divided into several stages.

[0002]

2. Description of the Related Art A microprocessor which includes a main memory read processing pipe (hereinafter, referred to as a MAC pipe) and a data processing pipe (hereinafter, referred to as an EXE pipe) and processes data by a pipeline control method (temporal parallel processing). Is conventionally used. In such a microprocessor, the main memory read processing pipe includes a stage for calculating an effective address for accessing the main memory, a stage for converting the effective address to a physical address, and a cache or cache for the data on the converted physical address. It comprises a stage for reading data from the main memory and storing it in the read buffer, and a stage for storing read data from the read buffer to a general-purpose register. The EXE pipe includes a stage for reading an operand required for an operation from a general-purpose register, a stage for executing the operation, and a stage for storing the operation result in the general-purpose register.

[0003]

In such a conventional microprocessor, since the number of stages of the MAC pipe and the EXE pipe are different, there is a problem that execution of the instruction is delayed as a result.

FIG. 3 shows a state of pipeline control by the conventional microprocessor. In this figure, (a) shows the MAC pipe instruction A, (b) shows the EXE pipe instruction, and (c) shows the MAC pipe instruction B. In the figure, "D" converts a main memory access instruction decode stage (MD stage), "A" converts an effective address calculation stage (MA stage) of main memory access, and "T" converts an effective address into a physical address. The stage (MT stage), “O” is a stage (MO stage) for reading read data from a cache or main storage and stored in a read buffer, and “W” is a stage (MO) for storing read data of the read buffer in a general-purpose register. MW stage).

[0005] As shown in this figure, in the conventional microprocessor, the number of stages of the EXE pipe and the MAC pipe is different. For this reason, after issuing a MAC pipe instruction A for fetching data from the main memory and then attempting to issue an EXE pipe instruction for performing an operation using the fetched data, the MAC pipe instruction A is used to issue a data from the main memory. Is read, and the read data is
Until the data can be transferred to the E pipe side (until the completion of the MO stage in FIG. 3), the execution of the EXE pipe instruction (EO stage in FIG. 3) cannot be performed. For this reason, the instruction issuance control unit waits for the stage of issuing the EXE pipe instruction, and as a result, the execution of the EXE pipe instruction is delayed by S for one stage, and the subsequent MAC pipe instruction B
Similarly, there was a problem that the issuance was delayed.

Therefore, an object of the present invention is to provide a MAC pipe and E
An object of the present invention is to provide a microprocessor in which the number of stages of an XE pipe is the same.

[0007]

According to the first aspect of the present invention, (a) a stage in which an effective address for reading from a main memory is calculated in a main memory processing unit, and the effective address is converted into a physical address. It constituted a stage by a stage of writing a stage for storing the read data read data from the cache or <br/> other main memory to the read buffer unit, the read data stored in the read buffer portion to the general purpose register A main memory read processing pipe, (b) a pseudo stage for matching the number of stages, a stage for reading an operand to be subjected to arithmetic and logical operation processing from a general-purpose register unit or a read buffer unit, and transmitting the operand to an operation processing execution unit. A stage in which arithmetic processing is performed in the arithmetic processing effective part using operands, and the result of this arithmetic processing is By the stage to be written to the register
The number of stages is equal to the main memory read processing pipe
And a predetermined instruction is issued to the pseudo stage.
At the same time, the instruction following this specified instruction is read from main memory.
Issued to the stage that calculates the effective address of the pipe
A microprocessor is provided with a data processing pipe.

That is, in the first aspect of the present invention, the data
A pseudo stage for adjusting the number of stages in the processing pipe is provided, and when a predetermined instruction is issued to the pseudo stage,
Sometimes the instruction following the specified instruction is the main memory read processing pipeline.
Is issued to the stage for calculating the effective address of the group.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows a main part of a microprocessor according to an embodiment of the present invention. The microprocessor includes an instruction issuance control unit 11 for receiving a soft instruction. When receiving the soft instruction, the instruction issuance control unit 11 performs this analysis. When an arithmetic and logic operation is required, an arithmetic and logic operation instruction decode stage (ED stage) is executed and issued to the EXE pipe 13 via the EXE pipe instruction signal line 12.
Here, the EXE pipe 13 includes a pseudo stage (EA stage) for adjusting the number of stages, a read stage (ET stage) of an operand to be operated, an operation execution stage (EO stage), and a write stage (EW stage) of an operation result. It is for control.

When a main memory access instruction is required as a result of analyzing the software instruction, the instruction issuance control unit 11
Executes a main storage access instruction decode stage (MD stage) and issues it to the main storage read processing pipe 15 via the MAC pipe instruction signal line 14. Here, the main memory read processing pipe 14 reads an effective address calculation stage (MA stage) for main memory access, a stage for converting an effective address into a physical address (MT stage), reads read data from cache or main memory, and reads the read data to the read buffer 16. This is for controlling a stage to store the data (MO stage) and a stage to store the read data of the read buffer 16 in the general-purpose register unit 18 (MW stage).

EXE pipe general-purpose register read signal line 2 as ET stage execution control signal of EXE pipe 13
1 is a general-purpose register section 18 as an operand to be operated.
Is read. The data read from the general-purpose register unit 18 is input to the arithmetic processing unit 23 via the EXE pipe operand data line 22 as one operand of the arithmetic processing. The other operand to be operated is supplied from a cache stored in the read buffer 16 or an internal bus 26 for sending data from the main memory to the EXE pipe side by bypassing the general-purpose register section 18 via the read data line 24. Is entered. The input data of the read buffer 16 and the data of the general-purpose register 18 are expressed by EX.
The arithmetic processing unit 23 performs arithmetic processing according to the content indicated by the arithmetic instruction signal line 27 as an EO stage execution control signal of the E pipe 13.

The operation result of the operation processing unit 23 is input to the general-purpose register unit 18 through an operation result data line 28,
EXE as the EW stage execution control signal for E pipe 13
It is written to the location indicated by the pipe general register write signal line 29. The main storage processing unit 30 is provided for the MAC pipe 15
In the MT stage of the MAC pipe 15, the effective address calculated in the MA stage is converted into a physical address in accordance with the instruction of the address calculation instruction signal 31 as the MA stage execution control signal. Then, read data is read from the cache or the main memory at the MO stage using the converted physical address, and stored in the read buffer 16. The data read from the read buffer 16 is input to the general-purpose register unit 18 via the read data line 24, and is written as a MW stage execution control signal at the location indicated by the MAC pipe general-purpose register write signal line 32.

With the microprocessor having such a configuration,
A MAC pipe instruction A for reading data from the main memory and writing the data to the general-purpose register unit 18;
After that, the data read by the MAC pipe instruction A is used as a first operand, the data read from the general-purpose register unit 18 is added as a second operand, and an EXE pipe instruction to be written to the general-purpose register unit 18 is executed. The operation when the software instruction for executing the MAC pipe instruction B is supplied to the instruction issuance control unit 16 will be described with reference to FIG.

FIG. 2A shows a MAC pipe instruction A.
(B) is an EXE pipe instruction, and (c) is a MAC
The pipe instructions B are respectively shown. Reference numerals such as "D" in the figure are the same as those described in FIG.

When the instruction issuance control unit 11 receives the supply of the soft instruction, it analyzes it, executes the MD stage, and issues the MAC pipe instruction A to the MAC pipe 15 first. While the MAC pipe instruction A is executing the MA stage, the instruction issuance control unit 11 executes the ED stage. And M
When the AC pipe instruction A moves to the MT stage, E
An XE pipe instruction is issued to the EXE pipe 13, and at the same time, a MAC pipe instruction B is issued to the MAC pipe 15.

First, the MA of the data read instruction from the main memory is
The C pipe instruction A is issued to the MAC pipe 15 via the MAC pipe instruction signal line 14. MAC pipe 1
In the MA stage No. 5, the effective address calculation of the data read from the main memory is performed by the main memory operation processing unit 30 in accordance with the instruction of the address calculation instruction signal 31. Then, in the MT stage, the execution address calculated in the previous MA stage is converted into a physical address, and the read data is read from the cache or the main memory using the converted physical address.
To be stored. Thereafter, in the MW stage, the data in the read buffer 16 is stored in the general-purpose register unit 18 via the read data line 24 according to an instruction from the MAC pipe general-purpose register write signal line 32.

Next, an EXE pipe instruction is issued from the instruction issuance control unit 11 to the EXE pipe 13 via the EXE pipe instruction signal line 12, and the MAC pipe instruction A is issued simultaneously with the end of the MA stage. The EXE pipe 13 does not operate in the EA stage, and reads the general-purpose register unit 18 serving as the second operand of the arithmetic processing unit 23 in the ET stage.
This is performed by the XE pipe general-purpose register read signal line 21.
At the same time as writing data from the cache or main memory serving as the first operand from the read buffer 16 to the general-purpose register 18, the internal bus A 26
Is input to the arithmetic processing unit 23 via the. In the EO stage, data read from the general-purpose register section 18 via the EXE pipe operand data line 22 and the internal bus A
The data input via the data processing unit 26 is added by the calculation processing unit 23 in accordance with the addition operation instruction on the calculation instruction signal line 27. Then, in the EW stage, the operation result of the operation processing unit 23 is sent to the general-purpose register unit 18 via the operation result data line 28, and writing is performed by the EXE pipe general-purpose register write signal line 29. At this time, by using the internal bus A26, the MW stage of the MAC pipe instruction A and the EXE
The EO stage of the pipe instruction can be executed at the same timing.

Next, the MAC pipe instruction B is issued from the instruction issuance control unit 11 via the MAC pipe instruction signal line 14 at the same time as the preceding EXE pipe instruction.
The process is performed in. Conventionally, at this time, even if the internal bus A is used as shown in FIG.
There is no pseudo stage EA for matching the number of stages with the AC pipe 15. For this reason, since the first operand required for the operation is not stored in the read buffer 16, the EXE pipe instruction from the instruction issuance control unit 11 causes a one-stage issue delay due to the wait for the first operand confirmation. I will. As a result, FIG.
As shown in (c), there is a problem that the issue of the subsequent MAC pipe instruction B is delayed by one stage.

However, in the embodiment of the present invention, EXE
Since an EA stage as a pseudo stage is added to the pipe 13, an EXE pipe instruction can be issued without delay. That is, as shown in FIG. 2C, the subsequent MAC pipe instruction B can be issued one stage earlier than the conventional case.

[0021]

As described above, in the present invention, the data
A pseudo stage for adjusting the number of stages of the main memory read processing pipe has been added to the processing pipe side. For this reason,
After issuing the main memory read processing pipe instruction for main memory read ,
When the subsequent data processing pipe instruction issues an instruction that performs an operation using the read data, the added pseudo-state
Can be issued to a data processing pipe that has
At the same time, the following main memory read processing pipe instruction is also specified.
It can be issued to the read processing pipe. This
Data processing by waiting for the main memory data to be read. <br/> The stage wait of the pipe instruction can be eliminated, and the subsequent pipe instruction can be issued promptly, thereby improving the performance of the microprocessor. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a timing chart showing a pipeline control method of the microprocessor in the embodiment.

FIG. 3 is a timing diagram showing a conventional microprocessor pipeline control method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Instruction issue control part 13 EXE pipe 15 MAC pipe 16 Read buffer 18 General-purpose register part 23 Operation processing part 30 Main storage processing part

Claims (1)

(57) [Claims] 1. A read effective address calculation for performing from the main memory and the stage carried out in the main memory unit, a stage for converting the effective address into a physical address, calibration
A main memory read processing pipe comprising a stage for reading data from the cache or main memory and storing the read data in a read buffer unit, and a stage for writing the read data stored in the read buffer unit to a general-purpose register; A pseudo stage for adjusting the number of stages, a stage for reading an operand to be subjected to arithmetic and logic operation processing from the general-purpose register unit or the read buffer unit, and sending it to the operation processing execution unit, and using the operand to execute the operation processing a stage for performing arithmetic processing in part, <br/> thus the main memory read process pipe and number of stages in the stage to be written to the general purpose register the result of the arithmetic process and the like
And the predetermined instruction is executed by the pseudo-state.
At the same time that the instruction following this instruction is issued.
A switch that calculates the effective address of the main memory read processing pipe
A data processing pipe issued to the stage .