JPH052485A - Pipeline control system - Google Patents

Abstract

PURPOSE:To construct a pipeline control system to make fast the exception processing by making the subsequent instruction remained in a pipeline into an execution object by a hardware arithmetic circuit when the exception occurs. CONSTITUTION:In a pipeline type information processor, the exception detection by operation is performed, and at the time of detecting the exception, the instruction to prepare the exception is read by hardware, emulation is performed (steps (b) and (d)), and when the subsequent instruction remains at the instruction cue, the subsequent instruction is read and re-arranged in the memory (steps (e) and (f)). Subsequently, the re-arranged instruction is read to the instruction cue in the same way as the usual instruction execution, and performed by using a hardware arithmetic circuit (step (g)). Thus, the high-speed of the exception processing is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline control system for realizing high speed processing.

[0002]

2. Description of the Related Art It is a conventional means to perform pipeline control in order to realize high speed calculation. Pipeline control is to perform parallel processing in a pipeline manner for fetching and executing instructions.

In the conventional pipeline control type information processing apparatus, when an exception occurs due to an operation instruction, the pipeline is stopped by an interrupt, the instruction in the pipe is read out by software, and the instruction causing the exception and its succeeding instruction. It was emulation. FIG. 3 shows an operation flowchart for conventional exception handling.

[0004]

According to the above prior art, when an exception occurs, the execution of the instruction causing the exception inside the pipeline and the subsequent instruction are all processed by software emulation. , It took quite a while to handle the exception.

As an example, an exception occurs when an extended precision arithmetic operation instruction is executed in an information processing device in which a hardware arithmetic circuit cannot execute an extended precision arithmetic operation. At that time, the instruction that caused the exception is emulated by software. When the instruction subsequent to the instruction that generated the exception is in the instruction queue, software emulation is performed even if the instruction is an instruction that can be executed by the hardware arithmetic circuit. This was a major cause of delaying exception handling.

The present invention has been made in view of the above circumstances, and when an exception in which an arithmetic instruction cannot be executed by hardware occurs, the subsequent instruction left in the pipeline is processed by the hardware arithmetic circuit. It is an object of the present invention to provide a pipeline control method that speeds up exception processing by making it an execution target.

[0007]

According to the present invention, there is provided a pipeline control type information processing apparatus having an instruction queue for holding an instruction read from a memory and executing instruction fetch and operation execution in parallel from the instruction queue. Exception detection means for detecting an exception due to an operation according to the fetched instruction, means for reading the instruction causing the exception by software and executing emulation, and fetching the subsequent instruction left in the instruction queue when the exception is detected And an instruction relocation unit for relocating the instruction to the memory, and the instruction relocated by the instruction relocation unit to the instruction queue is read and executed.

[0008]

In the pipeline control type information processing device,
When an exception occurs due to an operation, this is detected by the exception detecting means, the pipeline is stopped after executing the instruction to be executed before the instruction causing the exception, and the instruction causing the exception is succeeded. After the instruction is read by software and the instruction in which the exception has occurred is emulated, the subsequent instruction is executed by using the arithmetic function of the hardware arithmetic circuit in the same manner as the normal instruction execution.

That is, according to the present invention, when an exception occurs, the instruction that caused the exception executes emulation by software, and the subsequent instruction is stored again in the memory by software, and normal instruction execution and Similarly, by loading the instruction queue and using the hardware operation circuit to execute the operation, the exception processing can be speeded up.

Instructions subsequent to the instruction in which the exception has occurred are executed by the arithmetic function of the hardware. As a result, especially when a large number of instructions subsequent to the instruction that generated the exception are present in the instruction queue (inside the pipeline), the instruction execution speed is significantly higher than that of the conventional method in which the subsequent instructions are executed by software emulation. improves. This improves the processing performance.

[0011]

1 is a block diagram showing an embodiment of the present invention. In the figure, reference numeral 1 is a memory, a program,
Stores data etc. Reference numeral 2 is an input / output port (I / O port) for connecting an input / output device used by the user. Reference numeral 3 is a memory control circuit, and the address line 30
1, memory 1 via data line 302, input / output port 2
Control the input and output of data to and from. Reference numeral 303 is a signal line, which is used by the memory control circuit 3 to send an instruction read from the memory 1 to an instruction queue. Code 4
Is an instruction queue control circuit, which controls inputting and holding of data in the instruction queue. The instruction queue control circuit 4 also controls the priority of the memory access.

Reference numeral 50 is a first instruction queue, which receives and holds the data output from the memory control circuit 3 through the signal line 303. Whether or not to input the data transferred through the signal line 303 is controlled by the instruction queue control circuit 4 through the signal line 401.

Reference numeral 51 is a second instruction queue, which receives and outputs the data output from the instruction queue 50 through the signal line 501. Whether the data on the signal line 501 is input or not is controlled by the instruction queue control circuit 4 through the signal line 405. The instruction queue 51 is a queue of instructions for integer arithmetic and load / store.

Reference numeral 52 is a third instruction queue, which inputs and holds the data output from the instruction queue 51 through the signal line 511. Whether the data on the signal line 511 is input or not is controlled by the instruction queue control circuit 4 through the signal line 406.

Reference numeral 60 is an instruction decoding circuit, which inputs the data output from the instruction queue 50 through a signal line 501 and decodes (breaks) the data. Instruction decode circuit 60
The decode information of is sent to the instruction queue control circuit 4 via the signal line 601. The instruction queue control circuit 4 uses this information to control the instruction queue.

Reference numeral 71 is a first floating point instruction queue, and a floating point operation instruction is input from the instruction queue 50 through a signal line 501. Control of input and holding is performed by the instruction queue control circuit 4 via the signal line 402.

Reference numeral 72 is a second floating point instruction queue, and a floating point operation instruction is input from the floating point instruction queue 71 through a signal line 711. Control of input and holding is performed by the instruction queue control circuit 4 via the signal line 403.

Reference numeral 73 is a third floating point instruction queue, which inputs a floating point operation instruction from the instruction queue 72 through a signal line 721. Control of input and holding is performed by the instruction queue control circuit 4 via the signal line 404.

Reference numeral 80 is an integer operation & load / store control circuit, which receives the output of the instruction queue 51 from the signal line 511 and the output of the instruction queue 52 from the signal line 521, and performs an integer operation or Control load / store. The necessary register is read from the register file 81 based on the information received from the instruction queue 51. The designation is made by the signal line 803,
The data in this register is received through the signal line 804.

The arithmetic operation (execution of arithmetic instruction) in the integer arithmetic & load / store control circuit 80 is performed in synchronization with the transfer of control of the instruction of the instruction queue 51 to the instruction queue 52.
The result is stored in the register file 81 based on the information in the instruction queue 52. The result storage register is designated by the signal line 805, and the write data is stored in the data line 8
It is stored through 06.

On the other hand, in executing the load instruction, the integer operation & load / store control circuit 80 outputs a control signal to the control signal line 801 based on the information of the instruction queue 52, and the data received from the data line 802 is used. To do. The data received from the data line 802 is the control signal line 801.
The information is read from the memory 1 by the memory control circuit 3 on the basis of the above information.

In executing the store instruction, the integer operation & load / store control circuit 80 receives data from the signal line 804 based on the information in the instruction queue 51 and the data line 80.
It outputs by outputting to 2. The data on the signal line 804 is output from the register file 81 according to the designation of the signal line 803. Control information is output to the memory control circuit 3 via the signal line 801. The memory control circuit 3 executes the memory write of the data of the signal line 802 based on the information.

Reference numeral 81 is a register file, and various calculations are performed on this register file 81. Loading / storing is performed between this register file 81 and the memory 1 or the input / output port 2.

Reference numeral 82 is a first floating-point arithmetic circuit, which receives information from the floating-point instruction queue 71 via the signal line 711 and performs arithmetic on the floating-point. The floating point arithmetic circuit 82 specifies the register file 81 required for arithmetic operation through the control signal line 821, and the data line 822.
The data is floated from the register file 81 through.

Reference numeral 83 is a second floating-point arithmetic circuit, which receives information from the floating-point arithmetic circuit 82 through the signal line 820 and from the floating-point instruction queue 72 through the signal line 721, and performs floating-point arithmetic on the floating-point. The processing is carried over from the arithmetic circuit 82.

Reference numeral 84 is a third floating-point arithmetic circuit, which receives information from the floating-point arithmetic circuit 83 through the signal line 830 and from the floating-point instruction queue 73 through the signal line 731, and performs floating-point arithmetic on the floating-point. It is carried over from the arithmetic circuit 83.

3 of the floating point arithmetic circuits 82 to 84
The floating point arithmetic is completed by the arithmetic unit of the stage. The calculation result is stored in the register file 81 designated by the signal line 841 through the data line 842.

Reference numeral 90 is an exception detection circuit, which receives the information on the operation generated by the floating point operation circuit 84 via the signal line 840 and detects the exception based on the information. Reference numeral 901 is a signal line, and the exception detection circuit 90
When detects an exception, the signal transmitting the information to the instruction queue control circuit 4 is transferred.

FIG. 2 is a flow chart showing the outline of the operation of the embodiment of the present invention. In the figure, START indicates the start of the program. The program does not start until there is input from I / O port 2. Processing is started by inputting data from the input / output port 2 to the memory control circuit 3, and the control proceeds to step a. Step a is a routine for executing an instruction, which reads the instruction from the memory 1 and fetches it into the pipeline and executes it.

Step b is a routine for judging whether or not an exception has occurred. When an exception is detected, the exception processing routine is started. This exception occurs when the floating-point arithmetic circuits 82 to 84 shown in FIG. 1 can execute extended-precision floating-point arithmetic instructions, for example, although they can handle only single-precision and double-precision floating-point arithmetic operations. If an exception occurs, control transfers to step d. If no exception occurs,
The process proceeds to step c.

Step c is a routine for judging whether or not the program has ended. If the instruction read in step a is an instruction indicating the end of the program, the information processing apparatus stops the processing. If not, return to step a to execute the next instruction.

Step d is a routine for executing the instruction in which the exception has occurred, and the software executes the exception processing routine to emulate the instruction in which the exception has occurred (for example, an extended precision floating point arithmetic instruction).

Step e is a routine for judging whether or not the instruction queue is empty. The instruction following the instruction in which the exception has occurred is read by software and it is judged whether or not the instruction is valid.

Step f is a routine for reading an instruction from the instruction queue and re-storing it in the memory, and when it is determined that the instruction following the instruction that caused the exception is valid in the processing of step e, Memory 1
A state in which the instruction is re-stored in the above and then this instruction is read into the instruction queue and can be executed by using the arithmetic function of the hardware arithmetic circuit (integer arithmetic & load / store control circuit 80, floating point arithmetic circuits 82 to 84). To

Step g is a step of reading and executing the instruction rearranged in the memory 1, and reading and executing the instruction stored in the memory 1 in step f in the same manner as normal instruction execution. When the execution of these instructions is completed, or when the instruction subsequent to the instruction that caused the exception does not exist in the instruction queue, control is transferred to step c.
STOP indicates the end of processing.

The operation of the embodiment of the present invention will be described below. First of all, the entire device is in a waiting state. At this time, if an operation start input is input from the input / output port 2, the operation start information is transmitted to the memory control circuit 3 through the signal line 302.

When in the standby state, the memory control circuit 3 always controls the input / output port 2 through the signal line 301, and waits for the information for starting the operation to be input through the signal line 302. When there is an operation start input, the memory control circuit 3 starts reading an instruction.

Next, the memory control circuit 3 reads an instruction from the memory 1 through the signal line 301, and transmits the instruction and its instruction address to the instruction queue 50 through the signal line 303. At the same time, the memory control circuit 3 sends a control signal to the instruction queue control circuit 4 through the signal line 304. The instruction queue control circuit 4 controls the instruction queue 50 through the signal line 401 to latch the instruction and the address.

The command stored in the command queue 50 is sent to the signal line 501. The instruction decoder 60 decodes this instruction and sends the decode information to the instruction queue control circuit 4 through the signal line 601.

Based on the information on the signal line 601, the instruction queue control circuit 4 latches the information on the signal line 501 in the floating point instruction queue 71 if the instruction sent to the signal line 501 is a floating point arithmetic instruction. Control is performed through the signal line 402 so as to If it is not a floating point arithmetic instruction, the instruction queue control circuit 4 controls through the signal line 405 so that the information on the signal line 501 is latched in the instruction queue 51.

By the way, when the instruction transferred through the signal line 501 is a floating point operation instruction, the information latched in the floating point instruction queue 71 is transferred to the floating point operation circuit 82 and the (floating point instruction queue) through the signal line 711. It is latched in the instruction queue 72 of the next stage (of 71). The latch of the floating point instruction queue 72 is controlled by the instruction queue control circuit 4 through a signal line 403.

Next, the information in the floating point instruction queue 72 is output to the signal line 721. The information on the signal line 721 is latched in the instruction queue 73 of the next stage (final stage) of the floating point instruction queue 72 under the control of the instruction queue control circuit 4 performed via the signal line 404.

Information in the floating point instruction queue 73 is output to the signal line 731. Floating point arithmetic circuits 82, 83,
Information of the signal lines 711, 721, and 731 is input to 84, respectively. Floating point arithmetic circuits 82, 83, 84
Performs an operation based on the information (floating point operation instruction) transferred through the signal lines 711, 721, 731.

On the other hand, when the instruction transferred through the signal line 501 is not a floating point operation instruction, the information latched in the instruction queue 51 is latched in the instruction queue 52 of the next stage through the signal line 511. The latch of the instruction queue 52 is controlled by the instruction queue control circuit 4 through the signal line 406.

Next, the information in the instruction queue 52 is the signal line 5
21 is output. The information output to the signal lines 511 and 521 is input to the integer operation & load / store control circuit 80, where the integer operation or load / store function is executed.

The information processing apparatus shown in the embodiment of the present invention has a pipeline structure, and the floating point arithmetic circuit 8
The above operations are executed in parallel unless the operation result of 4 is an exception.

That is, in this embodiment, when three floating-point operation instructions are continuously input to the instruction queue 50,
Floating-point arithmetic instructions are stored in the three-stage floating-point instruction queues 71, 72, 73 in the order of input. If the floating point operation instruction does not cause an exception, these operations continue. However, when the same register in the register file 81 is designated, or when memory access is performed at the same time by reading an instruction from the memory 1 and executing a load / store instruction, the operation that should be executed first is performed. Be seen.

The control for that is performed by the instruction queue control circuit 4
Signal lines 304, 501, 601, 511, 52
This is performed for each instruction queue (50 to 52, 71 to 73) and the memory control circuit 3 based on various information input through 1, 711, 721 and 731. For example, when there is a load instruction in the instruction queue 52 and it is executed, the memory control circuit 3 performs a load operation and then reads a new instruction into the instruction queue 50.

On the other hand, the exception detection circuit 90 monitors the occurrence of an exception. That is, the exception detection circuit 90 constantly monitors the output signal line 840 of the floating point arithmetic circuit 84, and when an exception is detected (step b in FIG. 2), the information is sent through the signal line 901 to the instruction queue control circuit 4. Be transmitted to. As a result, the instruction queue control circuit 4 controls the queue described below to perform exception processing.

That is, when an exception occurs, the instruction queue control circuit 4 firstly, at that time, each instruction queue 50 to 52, 71.
Stop execution of the instruction latched in ~ 73. Next, the instruction queue control circuit 4 uses the instruction queues 50 to 52,
71 to 73 are controlled to sequentially output the commands,
The instructions in the respective queues 50 to 52 and 71 to 73 are sequentially fetched from the final stage queues 52 and 73 to the integer arithmetic & load / store control circuit 80 through the signal lines 521 and 731.

As a result, the integer operation & load / store control circuit 80 sequentially transmits the fetched instructions to the memory control circuit 3 through the signal line 802. The memory control circuit 3 reads this instruction again into the instruction queue, and the integer arithmetic & load / store control circuit 80 or the floating point arithmetic circuit 82 is read.
Re-arrange in the memory 1 so that it can be re-executed in steps (-) to 84 (step f in FIG. 2). Here, after the instruction that generated the exception to be rearranged and executed in the memory 1, the instruction that should be executed, that is, the integer operation or load / store that should be executed before the floating-point operation instruction that generated the exception. If there is an instruction, execute it as usual before exception handling.

When an exception occurs (for example, even though the floating point arithmetic circuit 84 cannot execute the extended precision operation, the extended precision floating point arithmetic instruction is input to the circuit 84, If the exception detection circuit 90 detects an exception), the instruction is executed by software emulation (step d).

Thereafter, with respect to the instruction existing in the instruction queue that is to be executed after the instruction that has generated the exception and has been rearranged in the memory 1 as described above, the above-mentioned series of instructions is executed in the same manner as the normal instruction execution. Processing is performed by operation (step g). Subsequent instructions are also executed continuously. If the input instruction is an instruction indicating the end of the program, after executing the instruction that should be executed before that instruction,
Return to the waiting state.

[0054]

As described above, the instruction following the instruction in which the exception has occurred is executed by the arithmetic function of the hardware. As a result, when a large number of instructions subsequent to the instruction in which the exception occurs exist in the pipeline, the instruction execution speed is improved by software emulation as compared with the case of executing those instructions. As a result, it contributes to the improvement of the execution speed of the information processing apparatus system, that is, the performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of a conventional example.

[Explanation of symbols]

1 ... memory, 2 ... input / output port (I / O port), 3 ...
Memory control circuit, 4 ... Instruction queue control circuit, 50-52
... instruction queue, 60 ... instruction decoding circuit, 71-73 ...
Floating-point instruction queue, 80 ... Integer operation & load / store control circuit, 81 ... Register file, 82-84 ... Floating-point operation circuit, 90 ... Exception detection circuit.

Claims (1)

Claim: What is claimed is: 1. A pipeline control type information processing apparatus, comprising an instruction queue for holding an instruction read from a memory, for executing instruction fetch and operation execution in parallel. Exception detecting means for detecting an exception due to an operation in accordance with a specified instruction, means for executing emulation by reading out the instruction that generated the exception detected by the exception detecting means by software, and when the exception is detected by the exception detecting means And an instruction relocating means for retrieving subsequent instructions remaining in the instruction queue and relocating them in the memory, wherein the instructions relocated in the memory by the instruction relocating means are stored in the instruction queue. The pipeline control method is characterized in that it is read out and executed.