JPS6116112B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an instruction control device in a vector arithmetic processing device that operates on corresponding operands, for example, a plurality of first operands and a plurality of second operands, and particularly relates to an instruction control device in an instruction pipeline of an instruction control device. , the arithmetic control management section that manages the arithmetic processing and storage control section is arranged in multiple stages, and subsequent instructions are controlled by referring to the operation of the instruction pipeline that manages at least the first stage of the arithmetic processing section. The present invention relates to an instruction control device that facilitates control of data processing.

In a general-purpose computer, one element of data is loaded from memory into a register in the central processing unit, and a second element consisting of one element on a register is loaded.
An operation is performed between the input operand and a third input operand consisting of one element to obtain a result operand consisting of one element. An instruction that performs such control is an instruction called a scalar instruction that processes a single element in one instruction.

However, vector arithmetic devices are controlled by vector instructions that process a plurality of elements with one instruction. For example _, in _a load instruction, as _shown in _{FIG .}
b ₃ ......Bn is loaded into the vector register 5 via the memory control unit 3 and main memory control unit 2 based on the instruction to the instruction control device 4, and the arithmetic processing is performed by, for example, the next addition instruction. In section 6, these data are added and A+B=C, that is, a ₁ +
b ₁ = c ₁ , a ₂ + b ₂ = c ₂ ……an + bn = cn, and the resulting multiple addition results
c ₁ , c ₂ , c _{3 .} . . cn is set in the vector register 5 and then stored in the main storage device 1. In this case, with one addition instruction, the above a ₁ + b ₁ = c ₁ , a ₂ + b ₂ = c ₂ …………an+
Multiple operations such as bn=cn are performed sequentially.

When performing such operations, instructions are generally processed in a pipeline in the field of high-speed computers such as vector arithmetic units. For example, as shown in FIG. 2, one instruction process includes fetching an instruction word (Fetch), decoding it (Decode),
It can be divided into three stages: instruction execution (Execute). When the preceding instruction is executing the instruction without processing the instruction one by one, the next instruction is decoding the instruction, and the subsequent instruction is decoding the instruction word. Perform extraction. In other words, as shown in Figure 3, the preceding instruction
When V ₁ is executing an instruction (E), the next instruction V ₂ executes instruction decoding (D), and the next instruction V ₃ executes instruction word fetching (F), and so on. Processing is performed using a pipeline processing method that processes both at the same time. At this time, multiple cycles are required to execute the instruction, but
In general, the arithmetic processing unit does not have a pipeline structure but a single structure.
When executing an instruction, adders and shifters are used multiple times to process one scalar instruction, that is, one element at a time. Therefore, the next instruction cannot be executed until the instruction execution (E) of one preceding instruction is completed.

However, if high-speed calculations are not required, the method described above will not cause much of a problem, but if vector instructions are to be processed at extremely high speeds, the calculation processing section should be constructed in a pipeline structure, and the preceding elements It is necessary to input the subsequent element and start its calculation process before the calculation process of .

For example, when performing addition, the instruction execution in the arithmetic processing unit involves reading the data (Read), comparing the exponents of both operands (Compare), shifting to match the exponents (Aligment), adding (Add), and normalizing after the operation. Shift for (Post
Shift), data writing (Write). Here and above you need to use a shifter. General-purpose computers use the same shifter, but this slows down the calculation speed, so in order to process vector instructions at ultra-high speed, the calculation processing unit naturally has a pipeline structure, and for this purpose, the above and Separate shifters will be provided for each. Therefore, when a vector instruction that processes multiple elements in one instruction is processed by a pipeline arithmetic unit, the final stage of write processing is performed for the most preceding element _l1 , as shown in Figure 4A. When the next element l ₂ is post-shifted, element l ₃ is added and added to element l _4.
Alignment processing is performed for element _l5 , index comparison processing is performed for element l5, and read processing is performed for element _l6 , and each of these processes is sequentially performed for element ln. As a result, when addition is performed using a vector instruction, a process represented by a parallelogram as shown in FIG. 4B is performed for each instruction.

Furthermore, in the case of a load instruction for loading data from the main memory device 1 into the vector register 35 shown in FIG. 1, pipeline processing similar to that for the addition instruction is performed in the storage control unit 3.

However, in an arithmetic processing unit equipped with such a pipeline structure, vector instructions V ₁ and V ₂
(for example, both are addition instructions), the instruction control pipeline structure in the instruction control device processes these vector instructions V ₁ and V ₂ in the state shown in FIG. It can be done.

Now, in the instruction control device, when an instruction word F 1 is read out by the instruction V ₁ and is decoded _{D 1 ,} the instruction word is read out F ₂ by the instruction V ₂ .
will be carried out. When the instruction execution E ₁ of the instruction V ₁ is performed in the arithmetic processing unit, the instruction word in the instruction V ₂ is decoded D ₂ in the instruction control device. However, as shown in FIG. 5, this instruction execution E ₁ ends when the write process for the last element l ₈ is performed at time t ₂ , and then instruction execution E ₂ for the instruction V ₂ is performed. .
Therefore, t ₂ from time t ₁ when the data read process for the last element _{l 8} is finished in the instruction V 1 in the arithmetic processing unit to time t ₂ when the data read process for the first element l ₁ ' starts in the instruction V ₂ −
The period t ₁ =t ₀ is a so-called idle period in which the data read processing circuit is not given any job from the instruction control device, although it is possible to execute a job. Similarly, each of the circuits for index comparison processing, alignment processing, addition processing, postshift processing, and write processing each has an idle period of period t ₀ , and as a result, as shown by the shaded area L in FIG. There will be a period of play like this. As described above, due to limitations in the pipeline structure of the instruction control device, even though it is possible to perform read processing for instruction V ₂ once the read stage for instruction V ₁ is completed in the arithmetic processing unit, it is not possible to do so. As a result, there is a drawback that the above-mentioned idle period occurs, which poses a problem in terms of high-speed processing.

Therefore, as shown in FIG. 6, it is conceivable to manage the instruction execution stage of the instruction pipeline by dividing it into two, for example, into a data read stage and a subsequent stage. In this case, the command control device has the first
An instruction execution register and a second instruction execution register are provided, and instruction _V1 is initially controlled by the instruction set in the first instruction execution register.
An instruction is set in the second instruction execution register at time T ₁ when read processing for all elements is completed in V ₁ , and write processing up to time T ₂ is managed based on the instruction set in the second instruction execution register. I'll do what I do.

However, the following problem occurs when, for example, instruction V ₁ is an addition instruction and instruction V ₂ is a comparison instruction.

In the case of an addition instruction, as described above, reading data (Read), exponent comparison of both operands (Exponent Compare), shift for exponent adjustment (Aligment), addition (Add), and shift for normalization after operation (Post Shift), data writing (Write), processing is completed in 6 cycles, and in the case of a comparison instruction, data reading (Read) and exponent comparison of both operands (Exponent
The process is completed in five cycles: Compare), shift for index alignment (Aligment), comparison (Compare), and writing of comparison results (Write).

Therefore, as shown in FIG. 7, when an addition instruction is processed as instruction V ₁ and a comparison instruction is processed as instruction V ₂ , write cycles are performed simultaneously, but the write register in the arithmetic processing section is Since there is only one, the result of instruction V ₁ and the result of instruction V ₂ will be overwritten at the same time, and they cannot be separated, so
The results of instruction V ₁ and instruction V ₂ will be mixed, and in the end it will not be possible to obtain correct results for either instruction.

To prevent this, either issue the subsequent instruction V ₂ after the preceding instruction V ₁ is completed, or detect the processing cycles required for each instruction, so that it is expected that it will overtake or catch up. When this occurs, it is necessary to make subsequent command transmissions wait until such a situation no longer occurs. However, in the former case, there is no point in creating a pipeline and data processing efficiency decreases, and in the latter case, instructions must be constantly compared and subsequent instruction transmission control must be performed according to the instruction. , control becomes very complex.

Therefore, as described above, an object of the present invention is to provide an instruction control device that can easily prevent a subsequent instruction from catching up and overtaking a preceding instruction. The instruction control device according to the invention includes an arithmetic processing means such as an arithmetic processing section having a pipeline structure or a storage data processing means, and an instruction control device that controls data processing in the arithmetic processing means or storage data processing means such as a storage control section. In a data processing device that processes vector instructions, arithmetic control execution instruction information is transmitted to an arithmetic control execution stage that includes a stage register, a stage setting circuit, an instruction decoder, etc., that holds arithmetic execution instruction information of the instruction control device. A plurality of arithmetic control execution instruction holding means are provided to divide the arithmetic control execution stage into a plurality of stages, and when an instruction is executed in the arithmetic processing means or storage data processing means, one arithmetic processing means. or in one storage data processing means, the number of pipeline stages is made constant for each instruction, and in at least one arithmetic processing means or one storage data processing means, the number of preceding pipeline stages is configured to be constant for each instruction. It is characterized in that the execution of an instruction is completed before the subsequent instruction.

Before explaining the details of the present invention, an outline of the operation of the present invention will be explained with reference to FIG.

When executing a comparison instruction as instruction _V2 , a dummy cycle is inserted after the comparison stage, and then a write stage is performed. Therefore, as shown in FIG. 8, when executing the comparison instruction, it requires 6 cycle time like the addition instruction, and the addition instruction is transmitted as instruction V ₁ , and the addition instruction is transmitted as instruction V ₂ .
Even if a comparison instruction is transmitted as a ``transfer'', the write steps will not overlap.

An embodiment of the present invention will be described below based on FIGS. 9 to 11.

FIG. 9 is a block diagram of an embodiment of the present invention, FIG. 10 is an explanatory diagram of its operation, and FIG. 11 is a partially detailed explanatory diagram of the present invention.

In the figure, 7 is an ER stage setting circuit, 8 is an ER stage register, 9 is an EW stage setting circuit, 10
is an EW stage register, 11 and 12 are decoders, 13 is a vector register, 14 is an arithmetic processing unit, 15 is a first operand register, and 16 is a second operand register.
Operand register, 17 is a comparison circuit, 18 is a first data register, 19 is a second data register,
20 is a comparison holding register, 21 is a first shifter, 2
2 is a first calculation register, 23 is a second calculation register, 24 is a calculation circuit, 25 is a calculation identification register,
26 is a calculation output register, 27 is a second shifter, 2
8 is an output register, and 29 is a dummy register.

The ER stage register 8 and the EW stage register 10 are stage registers each holding an operation execution instruction, and provide operation execution instruction holding means.

The ER stage setting circuit 7 determines whether the read process can be executed when the instruction is transmitted from the decoder 11 to the arithmetic processing unit 14, and when the read process is possible, the decoder D receives the instruction and executes the ER stage setting circuit 7. It is transmitted to the stage register 8 and further decoded by the decoder 11, or when it is no longer necessary to hold the instruction loaded in the ER stage register 8, it is erased, or the next new instruction is accepted. It performs precise control.

The EW stage setting circuit 9 sets the command from the ER stage register 8 to the EW stage register 10, and also sets the command from the ER stage register 8 to the EW stage register 10.
When it is no longer necessary to hold the set command, it is deleted or the next new command is accepted.

The decoder 11 decodes the instructions set in the ER stage register 8, and in particular decodes portions other than write processing instructions.

The decoder 12 decodes the instructions set in the EW stage register 10, and in particular decodes the write processing instruction portion.

The vector register 13 is used to temporarily set a plurality of elements necessary for a vector operation, and is temporarily set by a write instruction decoded by the decoder 12 for the result processed by the arithmetic processing unit 14. be.

The arithmetic processing unit 14 uses the elements set in the vector register 13 to process the decoder 1.
1, and includes a comparator circuit 17, a first shifter 21, an arithmetic circuit 24, a second shifter 27, and the like.

The first operand register 15 and the second operand register 16 each receive a first operand and a second operand to be operated on from the vector register 13. Comparison circuit 17 compares the exponent parts of the first and second operands.

The first data register 18 and the second data register 19 are to which the first and second operands are transmitted from the first operand register 15 and the second operand register 16, respectively. The comparison holding register 20 stores the first and second operands performed by the comparison circuit 17.
A register in which the comparison result of the exponent parts of the operands is set, and based on this comparison result, the first
In the shifter 21, one of both operands is shifted for index matching.

The first arithmetic register 22 and the second arithmetic register 23 are set with the output of the first shifter 21, and both operands after exponent matching are set therein. The arithmetic circuit 24 performs operations such as addition and comparison, and identifies items obtained as a result of the operation, such as which of the two operands is larger, or how many 0s there are at the beginning of the numerical value obtained as the result of the operation. The identification result is set in the calculation identification register 25, and the numerical value of the calculation result is set in the calculation output register 26.

If a 0 exists at the beginning of the numerical value output to the arithmetic output register 26, the second shifter 27 shifts it so that the 0 does not exist in response to a control signal transmitted from the arithmetic identification register 25. The shift result is output to the output register 28.

The dummy register 29 temporarily holds the comparison result data transmitted from the arithmetic circuit 24 without directly transmitting it to the output register. For example, when the instruction to be processed by the arithmetic processing unit 14 is a comparison instruction, This dummy register 29 is operated based on a control signal from the decoder 11, and is used for addition instructions and dummy cycle processing to equalize the number of processing cycles. Figure 11b shows the arithmetic circuit 2 in this state.
4 shows the output path.

Now, in FIG. 9, instruction V ₁ which is an addition instruction
When executing, this instruction _V1 is transmitted to the instruction control device. This causes the instruction control device to perform an instruction fetch _F1 and then decode it _D1 . Then, at time _t0 ', when the ER stage setting circuit 7 determines in the arithmetic processing section 14 that the instruction based on the decode _D1 can be executed, it sets the instruction transmitted by the decoder in the ER stage register 8.

The instruction set in the ER stage register 8 is further decoded by the decoder 11.
Based on this, the decoder 11 transmits an element read request instruction and an element processing request instruction to the vector register 13 and the arithmetic processing section 14. As a result, elements l ₁ , l ₂ ...... set in the vector register 13 are sequentially read out (R ₁ ) (element l ₁ has the first operand a 1 and second operand b 1 , element l 2 has the first operand a ₁ and second operand b ₁ , and element l ₂ has the first (consisting of the first operand a ₂ and the second operand b ₂ ...), these first operands a ₁ , a ₂ ... and the second operands b ₁ , b ₂ ...... are the first operand in order. Register 15 and second operand register 16
, and index comparison (C ₁ ), shift for index adjustment (A ₁ ), addition (Ad), and shift for normalization after addition (PS) are performed. Then, each stage of processing from (R ₁ ) to (PS) described above is performed for the first element l ₁ , and when it comes to the stage where the calculation result should be set in the vector register 13 , the EW stage setting circuit 9 The instruction set in stage register 8 is set in EW stage register 10. This can be done, for example, based on a write stage arrival instruction signal generated from the arithmetic processing unit 14 to the EW stage setting circuit 9, or by predicting the cycle at which the write stage has been reached by means such as a counter. You can also do that. When an instruction is set in the EW stage register 10, the decoder 12 decodes the write processing instruction portion and transmits a write request instruction to the vector register 13. As a result, at time t ₁ ', the calculation results for the elements l ₁ , l ₂ . . . are set in the vector register 13 from the calculation processing section 14. The write stage process will be performed. ( _W1 ).

On the other hand, the above elements l ₁ , l ₂ . . . according to instruction V ₁
When the readout stage of ... ends at time _t2 ', the vector register 13 transfers it to the ER stage setting circuit 7.
Report to. As a result, the ER stage setting circuit 7 transfers the instruction V ₂ , which is the comparison instruction transmitted via the decoder D, to the ER stage register 8.
and is decoded by the decoder 11. In this case, the first operands a ₁ ′, a ₂ ′…… and the second operands b ₁ ′,
b ₂ '...... are read out sequentially (R ₂ ), and the first operand register 15 and second operand register 1
6, and performs exponent comparison (C ₂ ) and shift for exponent matching (A ₂ ) as in the case of instruction V ₁ above.
is performed, and then comparisons (CMP) between the first operand a ₁ ′ and the second operand b ₁ ′, between the first operand a ₂ ′ and the second operand b ₂ ′, and dummy cycle processing (DUMY) are performed. It can be done.

Furthermore, the write stage processing in instruction V ₁ started at time t ₁ ′ ends at time t ₃ ′, but
At this time, for example, the EW stage setting circuit 9 terminates the V ₁ instruction and executes the V 2 instruction by an instruction from the arithmetic processing unit 14 or by an appropriate means such as predicting the write stage end cycle by means such as _a counter. The instruction set in the ER stage register 8 based on the write start information is set in the EW stage register 10. Then, the decoder 12 decodes the write processing command part and transmits the write request command to the vector register 13. As a result, the above comparison result is set in the vector register 13 from time _t3 ' ( _E2 ), and at time _t4 ', the processing of the read stage in the above instruction _V2 is completed, and at time
At t ₅ ′, the write stage processing in instruction V ₂ ends.

Therefore, according to the present invention, a dummy cycle can be inserted when executing an instruction that completes in a short number of cycles, such as a comparison instruction, so that the number of cycles can be made equal, so that the subsequent instruction comes before the preceding instruction. There is no such thing as ending.

Moreover, as in the above-mentioned instruction V ₂ , the execution start stage of the subsequent instruction can be performed continuously after the processing of the first stage portion (read stage) of the preceding instruction V ₁ is completed, thereby improving data processing efficiency. I can do it.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a vector calculation device, Figures 2 to 4 are illustrations of its operation, Figure 5 is an illustration of the problems of the conventional vector calculation device, and Figure 6 is a diagram that has improved the above problems. An explanatory diagram of the operation in the case, Fig. 7 is the 6th
8 is a schematic diagram of the operation of the present invention, FIG. 9 is a configuration diagram of an embodiment of the present invention, FIG. 10 is an explanatory diagram of the operation, and FIG. 11 is a diagram of the operation of the present invention. It is a partially detailed explanatory diagram. In the figure, 1 is a main storage device, 2 is a main storage control device,
3 is a memory control unit, 4 is an instruction control unit, 5 is a vector register, 6 is an arithmetic processing unit, 7 is an ER stage setting circuit, 8 is an ER stage register, 9 is an EW
Stage setting circuit, 10 is an EW stage register, 11 and 12 are decoders, 13 is a vector register, 14 is an arithmetic processing unit, 15 is a first operand register, 16 is a second operand register,
17 is a comparison circuit, 18 is a first data register, 1
9 is a second data register, 20 is a comparison and holding register, 21 is a first shifter, 22 is a first calculation register, 23 is a second calculation register, 24 is a calculation circuit,
25 is an operation identification register, 26 is an operation output register, 27 is a second shifter, 28 is an output register, 2
9 indicates dummy registers, respectively.

Claims (1)

[Scope of Claims] 1. Data processing for processing vector instructions, comprising an arithmetic processing means or storage data processing means having a pipeline structure and an instruction control device for controlling data processing in the arithmetic processing means or storage data processing means. In the apparatus, a plurality of arithmetic control execution instruction holding means for holding arithmetic control execution instruction information in an arithmetic control execution stage comprising a stage register, a stage setting circuit, an instruction decoder, etc. for holding arithmetic execution instruction information of the instruction control device; is provided to divide this arithmetic control execution stage into a plurality of stages, and when executing an instruction in the arithmetic processing means or storage data processing means, one arithmetic processing means or one storage data processing means. Among them, the number of pipeline stages is configured to be constant for each instruction, and in at least one arithmetic processing means,
Alternatively, an instruction control device characterized in that, in one storage data processing means, execution of a preceding instruction is completed before a subsequent instruction.