JPS6217773B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device that performs pipeline processing, and particularly to a data processing device that allows a microprogram to execute instructions at high speed without being aware of the difference between operands in memory or register direct. The present invention relates to a data processing device capable of processing data.

In recent years, as hardware has become faster, an increasing number of computers have been designed to increase the functionality of instructions with the aim of improving software productivity and improving memory usage efficiency. For this purpose, the addressing mode of the operand, which was conventionally dependent on the operation code (hereinafter abbreviated as OP code), has been made independent from the OP code, and a field that specifies the addressing mode is included in the instruction word. An independent command system is emerging.

However, when such an instruction system is processed by a processing device with a conventional data structure, the following problems arise.

FIG. 1 is a diagram showing the basic configuration of a data processing device that performs conventional pipeline processing. 1st
In the figure, if the processing device is divided into two parts, a unit that prepares instructions and a part that executes instructions, the instruction preparation unit 100 includes an instruction fetch circuit 150, an instruction decode circuit 102, and an effective address calculation section for operands. Address calculation circuit 1
03, an operand fetch circuit 104 that controls operand fetching. On the other hand, the instruction execution unit 101 operates the operand buffer 1
06, data selectors 107, 108, arithmetic circuit 109, temporary register 110, microprogram address register 111, microprogram memory 112, microinstruction register 1
It consists of 13 etc. In addition to these units, in a processing device employing a general register system, a general register 114 is shared by the instruction preparation unit 100 and the instruction execution unit 101. Of course, the configuration of a processing device that performs pipeline control may be divided into more detailed units.

FIG. 2 shows the processing device shown in FIG.
This shows more details about the part that executes instructions. In this figure, as an example, the OP code part OP, the part MOD1 that specifies the addressing mode of the first operand, and the register specification part R
1, 2-operand type instruction 20 with R2
The processing of 0 will be explained. MOD1 is a part that specifies the addressing mode of the first operand. If the above MOD1 is register direct, the register indicated by the register specification part R1 becomes the first operand, and if the above MOD1 is the memory reference mode. The register specification part R1
The register indicated by is used as the base register for effective address calculation. Command words 200
OP and MOD1 are decoded by the decode circuit 102 through signal lines 210 and 220 to create a microprogram address for controlling the instruction execution unit, and this address is set in the microprogram address register 111 through a signal line 123.

In the conventional processing equipment described above, the OP
Even if the code was the same, it was necessary to separate microprograms depending on whether the operand was a memory reference or a register direct operand. This is the two sets of output lines 12 of the general register 114.
7,128, one output line 127 is dedicated to the instruction preparation unit, and the other output line 128 is dedicated to the instruction execution unit. Therefore, when both operands are in register direct mode, the operands are used as instructions. The only signal line taken into execution unit 101 is the output line 128 of general register 114, and therefore, as shown in FIG. 3A, an addition instruction with two operands has no choice but to result in two sets of microprograms.

On the other hand, when the first operand is in the memory reference mode, the first operand is the signal line 1 from the memory.
30 to the operand buffer 106, and the microprogram becomes one microinstruction as shown in FIG. 3B.

In this way, separate microprograms must be prepared for cases where the operand is a memory or a register, which has the disadvantage of increasing the capacity of the microprogram and further causing a decrease in instruction processing speed.

The present invention has been made in view of the drawbacks of the prior art described above, and its object is to provide a data processing device that can be executed by the same microinstruction whether the operand is in register direct mode or memory reference mode. Our goal is to provide the following.

The present invention provides a communication register so that when an operand is given in register direct mode, the instruction preparation unit accesses the general register and transfers the contents of the register that will become the operand to the communication register in advance. In addition, when the addressing mode is the register direct mode, a mechanism is provided for reading the operand of this communication register into the instruction execution unit.

Hereinafter, the details of the present invention will be explained with reference to Examples.
FIG. 4 is a block diagram showing an embodiment of the pipeline control data processing device of the present invention. This data processing apparatus has an instruction preparation unit 100 and an instruction execution unit 101 which are mostly similar to the conventional apparatus shown in FIG. 1, but is characterized by the provision of a communication register 300 and a flag 301.

FIG. 5 shows elements related to the instruction execution part extracted from the embodiment shown in FIG. 4 in more detail, and has a format similar to that of the conventional example explained in FIG. The processing sequence of the two-operand instruction 200 will be explained. The OP code (OP) of the instruction word is converted into the start address of the microprogram by the decoding circuit 400, and is set in the microprogram address register 111 through the signal line 123.

MOD1 of instruction word 200 is decode circuit 40
1 and becomes a signal for setting and resetting the flag 301 via the signal line 311. That is, the flag 301 is set so that the selector 107 selects the signal line 310 when MOD1 is in the register direct mode, and so that the selector 107 selects the signal line 131 when MOD1 is in the memory reference mode.

Also, if MOD1 is in register mode,
The contents of the register specification part R1 of the instruction word 200 are set to one of the address registers 202 of the general register 114, and the contents of the corresponding register are set to the signal line 127, the address calculation circuit 103, and the signal line 1.
21 to the communication register 300. If the operand is a memory reference, the operand is set in the operand buffer 106 through a signal line 130 from the memory.

Therefore, when an instruction is executed, the operand is prepared in either the operand buffer 106 (memory reference mode) or the register 300 (register direct mode), and the address of the operand is determined by the flag 301 and selector 107. Since the addressing mode to be selected has already been determined in accordance with the addressing mode, there is no need to be aware of the addressing mode of the operand in the microprogram. Therefore, as shown in FIG. 6, when the present invention is implemented, the microprogram can be used in both the case of memory reference and the case of register direct.

As is clear from the above description, according to the present invention, a microprogram that executes an instruction is not affected by the addressing mode of the operand, and therefore, whether the addressing mode of the operand is memory reference or register direct, Since it is possible to use a common microprogram, it is possible to reduce the microprogram memory and furthermore, it is possible to reduce the number of executed microsteps.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional data processing device, FIG. 2 is a detailed diagram of the instruction execution portion of FIG. 1, and FIG. A diagram showing the program flow, FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a detailed diagram of the instruction execution portion of FIG. 4, and FIG. 6 is a diagram showing the execution of the addition instruction in the case of the present invention. FIG. 2 is a diagram illustrating a microprogram flow for. 100...Instruction preparation unit, 101...Instruction execution unit, 102, 400, 401...Decode circuit, 103...Address calculation circuit, 106
...Operand buffer, 114...General register, 300...Communication register, 301...
...Flag, 107,108...Selector.

Claims (1)

[Claims] 1. An instruction preparation unit that decodes the instruction word read from the storage device and prepares the operand by calculating the effective address of the operand included in the instruction word according to the decoding result; In a pipeline control type data processing device comprising an instruction execution unit that receives a given instruction word and operand and executes the instruction, a communication register, an operand buffer,
In addition, when the addressing mode is register direct, the instruction preparation unit sets the flag according to the addressing mode of the operand included in the instruction word. Set the contents of the specified register to the above communication register,
This content is selectively loaded into the instruction execution unit according to the instructions of the flag, and if the addressing mode is memory reference, the instruction preparation unit selects the memory device with the address specified by the instruction word. A data processing device characterized in that the content is set in the operand buffer, and the content is selectively taken into the instruction execution unit according to the instruction of the flag.