JPS59184948A - Microcomputer of variable structure - Google Patents

Abstract

PURPOSE:To obtain a microcomputer having high variable performance by setting optionally both register and memory regions with clear separation to an RAM incorporated into a microcomputer. CONSTITUTION:A microprocessor consisting of a microprogram control part 21, a microinstruction decoder 22 and an arithmetic part 23 is connected to an RAM12 via a command data bus 5h, address buses 5e, 5d and 5i and a register/ memory switching line 5c. A register field which designates a register number is provided into a microinstruction which is used by the part 21 together with a flag which identifies whether the contents of said register field are delivered to the common address bus. Both register and data regions are set to the RAM12 and then identified for access from the contents of the address bus delivered from the part 23 or the part 21 as well as the flag contents. Thus the number of register groups can be varied without invating a memory space.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] Kiko Mitsuki is a single-chip microcomputer that incorporates a microprogram, random access memory (R, AM), read-only memory (ROM), and peripheral I10 functions on one chip. The present invention relates to a variable structured microcomputer that incorporates a group of registers of a %Vc microprocessor in a RAM and is capable of emulating several types of microcomputers with different numbers and types of registers.

[Background of the invention]

In recent years, semiconductors, especially MOS (Metal QxideS)
With the miniaturization of electronic devices, microcomputers are also becoming more highly integrated and highly functional. Along with this, a highly integrated single-chip microcomputer 10 as shown in FIG. 1 has appeared. That is, with the microprocessor 11 as the core, RAMI 2, ROMI 3, timer 14, serial
It is a highly integrated device that contains I10 functions such as the ink face 15 in one chip. Inside this chip 10, the microprocessor 11 and each unit 12-15 perform input/output operations via an address bus 16 and a data bus 17.

For example, the microprocessor 11 reads instructions from the ROM 13, processes the data in the RAM 12, and the microprocessor 11 performs timekeeping operations by inputting and outputting data to the timer 14. Bus la.

It communicates with other microprocessors and I10 devices via 1b.

Single-chip microcomputer 10 marked -F
As an example of the microprocessor 11 shown in FIG.
The microprocessor 11 includes a microprogram control section 21, a microinstruction decoder 22, a calculation section 23, and a bus 24 that connects them. Although the microprogram control section 21 increases the flexibility of the microprocessor 110, the arithmetic section 2, which is the controlled section,
3 has a problem in terms of flexibility.

In other words, the instruction decoding and execution procedure of the Microphone 73 Processor 1 is based on the architecture (instruction system ) can be adapted.

On the other hand, the arithmetic unit 23 generally has a configuration, an example of which is shown in FIG. That is, it consists of an arithmetic register group 30 and an arithmetic circuit 31, and data read from the arithmetic register group 30 is input to the arithmetic circuit 31 via buses 3a and 3b.
The calculation result is sent back to the calculation register group 3 via bus 3C.
Returned to 0. For example, the arithmetic register group 30 includes a program counter (PC) that indicates the location of instructions in main memory.
), the stack pointer (
SP), an index register (IX) used for addressing operands, an accumulator (A) used for data operations, etc. These registers are the second
, 3, it is specified by the control signal 2C-a after the microinstruction decoder 22 decodes the microinstructions sequentially read out from the microprogram control section 21. Therefore, since the microinstruction is interposed between the instruction and the register specification, flexibility regarding register specification can be ensured by the microprogram control section 21 and the general-purpose register structure. However, since the arithmetic circuit 31 is also microinstruction controlled, flexibility is high.

As described below, the biggest factor in the flexibility of the arithmetic section 23 is the number of arithmetic register groups. In other words, in microprocessors of 11 different architectures (instruction systems), their operation registers are
) and other address-related registers, the number varies.
There are also two. We are trying to realize a highly flexible microprocessor by focusing on the number of registers.
In this case, it may be possible to set the number of registers to the maximum number, but this will increase the chip area, and if you try to expand the instructions, it may become unstable.

Therefore, embedding the arithmetic register group 30 in a part of memory (RAM) has emerged as one solution. This tendency is reflected in the single-chip microcomputer shown in FIG. 1, and can be realized in a system incorporating at least tLAM12. That is,
Between the RAM structure and the regimen structure, the former can be realized with about 115 of the latter, so the RAM is overwhelmingly advantageous in terms of size.

Therefore, according to the system in which memory and register groups coexist, the number of registers is not so much of a problem.

Although the structure in which the arithmetic register group 30 is moved to the RAM 12 makes the microprocessor 11 more compact, this alone causes the following problem. That is, as shown in Figure 4,
Since the register area and the memory area occupy the same address space on the RAM 12, the beginning of the memory area varies depending on the number of operation registers. This is unacceptable from a software standpoint.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a variable structured microcomputer in which a group of operational registers is built into a RAM, and the number of register groups can be made variable without infringing on memory space. be.

[Summary of the invention]

The present invention clearly separates the address output by a microprocessor by one bit stored in a microinstruction,
The structure is made variable by allowing the arithmetic register area and the data memory area to coexist in the RAM, and by configuring the address decoder of the RAM in a programmable manner.

[Embodiments of the invention and their effects]

Hereinafter, the present invention will be explained in detail with reference to Examples.

FIG. 5 is a block diagram showing an embodiment of the variable structured microcomputer of the present invention, showing in detail the relationship between the microprocessor 11 and RAM 12 in FIG. 2.

Below, each bus and microprogram control section, J21,
Microinstruction decoder 22, arithmetic unit 23 and RAM 12
The structure of the following is described below.

(1) Bus data bus 5b, address buses 5e, 5d.

5i register/memory switching signal line 5c (described later).

(2) Microprogram control unit 21 This unit includes an instruction register 50 that receives instructions from the data bus 5h, a multiplexer 51 that selects either the output or a branch address from the microinstruction, a microinstruction address register 52, and a microinstruction address register 52. Program R
It consists of an OM 500, a microinstruction register 53, and bus drivers 55 and 56.

from main memory to instruction register 5 via data bus 5h.
The instruction stored at 0 is selected by multiplexer 51 and stored in microinstruction address register 52. Depending on this content, micro program ROM500
The microinstruction read out is stored in the microinstruction register 53. The OP field of the register is inputted to the microinstruction decoder 22 by a signal 5j, decoded here, and controlled by the arithmetic section 23. The Rg field and μ/M field are parts related to the present invention and have the following functions.

(1) μ/M field This field is 1 bit long and identifies whether the address source when accessing R, AM12 is the Rg field in the microinstruction or the memory address output from the arithmetic unit 23. It's no good. Specifically, when μ/M-0, when the memory address μ/M=1, when accessing the R and g fields, that is, the arithmetic register group in RAM1'2, it is μ/M-1. .

(+i) Rg field In this embodiment, there are 5 pits, and since 25=32, a maximum of 32 operation registers can be specified. This field is valid only when the μ/M field described above is "III".

Now, if the μ/M field of the microinstruction placed in the microinstruction register 53 is 1'', it, / to 4
The value of the field is sent to the bus driver 5 via the signal line 5a.
5.56, the former drives the bus 5c to 0'', and the latter drives the bus 5d according to 11i\ of the Rg field of the microinstruction register 53 transmitted by the signal line 5b.At this time, the bus 5e is "■valid" (
invalid).

The ADR field is a field that indicates the branch address of the microprogram, and the ADR field is a field that indicates the branch address of the microprogram.
It is selected by multiplexer 51 and assigned a value of 1 to microinstruction address register 52.

(3) Microinstruction decoder 22 This unit converts the OP field in the microinstruction register in the microprogram control section 21 to the signal line 5.
j to generate signals that control each part of the arithmetic unit. The control signal is output to the calculation section 23 via the control signal line 5t.

(4) Arithmetic unit 23 This unit has a memory address register (L) 54 that stores the lower 8 bits of the memory address, and a memory address register (H) 59 that stores the upper 8 bits of the memory address.
, arithmetic circuit 60, input latch registers 61, 62, internal buses 63, 64, bus drivers 57, 58, 65 .
It consists of 66. .

The operations of these elements will be described later.

匍'mAMt2 In this embodiment, the RAM 12 has a capacity of 256 words, and a total of 9 bits of the buses 5C, 5e, and 5d described above are used as addresses.
Input to address decoder 521. Further, data input/output is performed between the memory section 522 and the bus 5h, and its correction will be described later.

The configuration of each unit has been mainly described above, but the actual operation will be shown below.

(a) Instruction fetch microinstruction field f (field to program counter (PC) address signal 5b, node driver 5
At the same time as outputting to address 5d via 6,
While the bus driver 56 is activated by setting the 87M field to 1'', the bus driver 55 drives the bus 5C.
- The counter (PC) is output from the RAMI 2 to the memory address register 54 in the arithmetic unit 23 via the bus driver 66 via the data bus 5h.
．． 59 are placed one after another. 87 in the next microinstruction
With the M field set to 0'', the contents of memory address register 54.59 are bus driver 57.58.65.
via address bus 5e.

5d and 5i. At this time as well, the 87M field is set to 0'', and instructions are read from the memory section of the RIV 112 or other memory.The read instructions are sent to the microprogram control section 2 via the data bus 5h.
1 is stored in the instruction register 50 in 1.

On the other hand, the contents of the memory address registers 54 and 59 are set to 1 by the arithmetic circuit 60 to prepare for the next instruction access.If this is not necessary, use the memory address registers 54 and 59. If this content is R
Return to the program counter (pc) in AM12.

(b) Instruction execution For example, when adding the contents of the calculation registers A and B in the RAM 12, the program counter (
The contents of register A are placed in the latch register 61 and the contents of register B are placed in the latch register 62 in the same way as the access method of p c ). The contents of these latch registers 61 and 62 are added by the arithmetic circuit 60, and the result is stored in the latch register 62 via the bus 64. This content is stored in register A in RAM 12 via bus 63, bus driver 66, and data bus 5h. Even during such operations, 87 microinstructions
The M field is 1'', and the g field indicates the address of register A.

Each unit shown above) 21.23 bus 5c.

The RAM 12 is controlled according to the driving of 5e and 5d. FIG. 6 shows an example of actual mapping between the arithmetic register group and memory using the address decoder 521 of the RAM 12.

(1) Arithmetic register (R, 1 to R31) If input signal 5C is 0" (87M field of microinstruction is 1") and bus 5d is in the range of "00001" to "11111", select one of arithmetic registers 1 to 31. is selected.

(2) Special register (R, 00 to It O7) When input signal 5C is 0” and bus 5d is “ooooo”, bus 5
Eight registers are allocated depending on the contents of e. This is an access to the arithmetic register mentioned above, and the bus 5d is RO(
(does not actually exist), one of the eight registers ROO-4LO7 is selected using the 3-bit state on bus 5e. The conditions placed on bus 5e are determined by other fields of the microinstruction register (e.g.
field, etc.) or part of the contents of the instruction register.

This can be used as a work register in multiplication and division.

The bus driver 501 in the microprogram control unit 21 in FIG. 5 is an example of outputting a part of the instruction register 50 to the bus 5e. That is, for example, in a multiplication process, RO is specified in the Rg field of the microinstruction, and μ
If the /M field is 1", it is possible to allocate one dedicated register indicated by the code of the multiplication instruction. This is used to latch the multiplicand or multiplier. According to this method, the microinstruction's Rg You can set or obtain more registers than can be specified in the field.

(3) Memory (MO-M216) Since 31 words were used for the calculation register and 8 words were used for the special register, 217 words can be allocated as memory.

As described above, the allocation of arithmetic registers, special registers, and memory can be performed by performing a mask program that can make the μ/M field and Rg field of the microinstruction variable and the address decoder 521 of the RAM 12 variable during production. and the same memory as RAM1
2 can be specified from an independent address source.

Next, using Figures 7 and 8, replaceable addresses and
The decoder will be explained in detail.

FIG. 7 is a diagram showing the overall configuration of a rewritable address decoder. This decoder consists of a first address decoder 70, a second address decoder 71, and a multiplexer/sense amplifier 72.

(1) Address Decoder 71 The address decoder 71 has a RAM structure, and must store predetermined address information during system initialization. For this purpose, a first address decoder 70
By treating the second address decoder 71 as a memory section, the seat address information is written. In this case, in addition to the μ/M field in the microinstruction described above, an M (Mode) field indicated by the I= line 5c/ is required.

(1) When the M field is 0'' (signal line 5c/ is ``1'') A 1-bit signal is input to the first address decoder 70 from signal line 5c/. decoder 70
One of the other outputs 80a becomes active. In the row of the second address decoder 71 that has become active, the contents of the data bus 5h are transferred to the multiplexer and sense
Data is written via amplifier 72. The first address decoders 70 are arranged linearly from address 0 to address 255 (in the case of 256 words).

The second address decoder 71 functions as follows. The above-mentioned second address decoder 71 can be generated online, and a 256-word RAM can have data for many address areas.

(ii) When the M field is 1” (signal line 5 c
/ is "0") Since the content of the signal line 5c / is "0", the first address decoder 70 is prevented from operating, and the second address decoder 70 is
The address decoder 71 functions simply as an address decoder, and the address decoder 71 of the address bus ! 'id, 5e to match the address to be input according to the specification V of the μ/M field 4-E1]. Activate the line where the manual address and the A/C address information entered in advance are matched.

Address decoder 71 in FIG. 2 is obtained by arranging memory cells 00 corresponding to one bit in FIG. 6 in a matrix. The value entered into the pill 700 becomes a value that forms an address decoder similar to that shown in FIG. In this case, since this decoder can dynamically change the NF, addresses of registers and memory on the RAM can be changed online, making the structure more variable. FIG. 8 shows the internal circuit of self 00 in FIG. 7 in detail. Memory cell 80 for storing whether the decode bit forming the address decoder is 1'' or II Ou, write control signal 80a) when inputting the address pattern 80a) Address pattern for i writing and address input bus 80b and opposite to 80b For the bus 80C1 address input carrying the 80b decoding result with the logic of
A circuit 8 for detecting whether the value matches the value stored in 80.
Consists of 1.

(When the input write control signal 80a of the IJ address pattern is 1", the buses 80b and 80
The value of b is written to memory cell 80.

(2) Address decoding If the value stored in the memory cell 80 in the previous section and the values on the buses 80b and 80b do not match, the detection circuit 81
Set bus C to 0". Therefore, connect 1 to bus C;
Only when all of the input 00's match the addresses of the inputs does the bus C go to 1'' and drive one word in the memory section 522 of FIG.

As explained in detail in Section 111 of the above embodiment, the register/' memory specification bit and RA provided in the microinstruction are
M address decoder mask or software
By adopting a programmable configuration, the register group of the microprocessor and the memory '+iu area can be placed on the same RAM, so the register group can be placed in any location, making the microcomputer's variable structure possible. is obtained.

〔Effect of the invention〕

According to the present invention, the register area and memory area can be arbitrarily set in the random access memory built into the microcomputer, thereby further increasing the variability of the arithmetic unit that is the controlled unit in the data processing device. It is possible to provide a variable +1.

[Brief explanation of drawings]

i, (+1, 1 is a diagram showing the general configuration of a single-chip microcomputer controlled by a microprogram, FIG. 2 is a diagram showing an example of the microprogram in FIG. 1, and FIG. 3 is a diagram showing an example of the microprogram in FIG. 2. Figure 4 shows the mapping of the RAM in the single-chip micro computer. Fig. 6 r, I: A diagram showing an example of the RAM address decoder in Fig. 5, where i≦;・A diagram showing an embodiment of a decoder. FIG. 8 is a diagram showing a specific example of the memory cell shown in FIG. , 56, 57.58... address buffer, 521.70.71... address decoder, 700
10th Fan 2 Kiri 3rd 4th Luo 5 Town

Claims (1)

[Claims] 1. A microprocessor having a microprogram control unit and an arithmetic unit controlled by the microprogram control unit and a random access memory (RAM) for storing data used by the microprocessor are connected to a common bus. In a microcomputer configured to connect with
A register field for specifying a register number and an identification flag for determining whether or not to output the contents of the register field to an address bus in a common bus are provided, a register area and a data area are set in the RAM, and the RAM is M is a variable structured microcomputer characterized in that a register area and a data area are identified and accessed based on the contents of the address bus output by the arithmetic unit or the microprogram control unit and the contents of the identification flag. . 2. The RAM according to claim 1 is a variable RAM that is accessed by the output of a programmable address decoder that changes the correspondence between the contents of the address bus and the addresses of the RAM according to the contents of the identification flag. Structured microcomputer 5. 3. Address decoder p-f according to claim 2
A variable structured microcomputer characterized by being configured with a programmable logic array. 4. A variable structured microcomputer, characterized in that the address decoder according to claim 2 is constructed from a replaceable memory.