JPS6330658B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, particularly a microcomputer.

Due to advances in semiconductor manufacturing technology, information processing devices such as microcomputers, which are mainly composed of insulated gate field effect transistors on the same semiconductor substrate and perform logic operations together with peripheral devices, have recently been applied to a wide range of fields, and are becoming increasingly popular in various fields. Processing is controlled by a program according to the requirements. Thanks to the remarkable improvement in semiconductor manufacturing technology, especially in the degree of integration, these microcomputers have not only a processing device (hereinafter referred to as a processor) that decodes instructions and performs arithmetic processing or supplies control signals internally or externally. Memory in which programs executed by this processor are stored (hereinafter referred to as program memory), memory used to store processing data, flags necessary for data processing, or temporary data obtained during processing. There are devices in which a data memory (hereinafter referred to as a data memory) and an input/output circuit are constructed on the same semiconductor substrate (chip). Some even integrate processors with other functions. However, in the future, as the amount of information increases, there is a great need for even greater processing power, and there is an urgent need to develop microcomputers that can handle this. Conventionally, a so-called 1 semiconductor substrate has a processor data memory, a program memory, and an input/output circuit configured on the same semiconductor substrate.
When processing information using a chip microcomputer, as shown in FIG. 1, a processor 1 first sends the contents of an internal program counter to a program memory (ROM) 2 as an address. The program read from the program memory (ROM) 2, that is, a group of instruction codes configured in a predetermined order, is taken into the instruction decoding circuit inside the processor through the internal data bus 4, where it is decoded and generated as a control signal. be done. This control signal controls the arithmetic unit, input/output circuit, etc. Furthermore, the contents of the address register 5 are given to the data memory (RAM) 3 as an address, and the intended processing is executed while writing and reading data for processing through the internal data bus 4. In such conventional microcomputers, the program memory is usually masked ROM.
is used. This is a ROM in which a fixed program that should be built in at the manufacturing stage is written. Therefore, the contents of this mask ROM cannot be changed or added after that. If it was necessary to change or add a program, it was necessary to rebuild a new microcomputer and create a new mask ROM based on the program that was changed or added during the manufacturing process. In this way, the functions of the processor are determined by the program contents of the program memory composed of ROM, and these are fixed at the manufacturing stage. accordingly
It is possible to improve the functionality of the processor by making the program stored in the ROM highly versatile, but the program becomes extremely complex and large and requires a large amount of memory elements. However, this is not practical because the storage capacity of ROMs that can be constructed on the same semiconductor substrate is limited. Therefore, in order to request more functions from the processor, the program memory can be changed freely instead of the mask ROM externally.
They needed memory that could be added. However, while we can expect some improvement in functionality, it goes without saying that the equipment will be extremely expensive.
The drawback was the complexity of control caused by adding external memory. On the other hand, even in high-grade microcomputers that have two processors on the same semiconductor substrate, it is impossible to change or add programs stored in each program memory, so each It was nothing more than a combination of the functions of the previous processors.

The purpose of the present invention is to enable the user to freely change or add the contents of the program memory;
An object of the present invention is to provide an information processing device with significantly improved program processing ability.

The present invention provides a first processor within the same unit (for example, the same chip), a first memory used as a program memory of the first processor,
and a second processor is provided in addition to the second memory used as the data memory of the first processor, a part of the second memory is used as the program memory of the second processor, and a part of the second memory is used as the program memory of the second processor. The second processor is externally accessed using the first processor.
This feature is characterized in that a program for the processor can be written.

According to the present invention, the types of programs that can be processed can be increased using the original ones (address bus, router bus, control bus) without adding new terminals, signal lines, and control signals. That is, the user can freely set the instruction code for the second processor in the device and use it, which greatly improves versatility.

Hereinafter, one embodiment of the present invention will be described in detail using FIG. 2. In FIG. 2, 10 and 12 are first and second processors, and the first processor 10 has a function of controlling internal memory and external memory. 11 stores program data (instructions) for the first processor 10;
0 is a program memory (ROM) readable by the first processor 10; 13 is a data memory (RAM) readable and writable by the first processor 10; this is simultaneously the program memory of the second processor 12; Also used as Reference numeral 14 indicates an external memory (for example, a magnetic disk may be used) that can be written to and read by an external processor, etc. Reference numeral 15 and 16 indicate internal data buses, and 17 indicates a connection between the microcomputer (dotted line M) and the external memory 14. 18 is an address bus for outputting address information, 19 and 20 are address registers for storing address information, and 21 is a data control circuit for selecting data input/output destinations. ,
22 is an address control circuit that selects the address given to the memory 13. In this example, the microcomputer M is integrated on one semiconductor substrate (one chip).

The processing operation of the microcomputer of this embodiment will be explained below. The first processor 10 first accesses the first memory 11 using the contents of its internal program counter as an address. The instruction code read from the first memory 11 is thereby taken into an instruction decoding circuit (instruction decoder) inside the first processor 10 through the internal data bus 15, and a control signal is generated.
The arithmetic and logic unit, the second memory 13, etc. are controlled by this control signal. By repeating the above operations, the first processor 10 initializes the chip. After the initialization is completed through this series of operations, the first processor 10 can be freely operated by using an external host processor etc. outside the semiconductor substrate on which the first processor 10 is configured. The contents of the address register 20 are given via the address bus 18 to the external memory 14 (in which the program is stored here), the contents of which can be changed and added to. External (data (instruction code) read from memory 14 is transferred to external data bus 17,
The data is stored in the second memory 13 via the internal data bus 15. Furthermore, it is also possible to write not only the instruction code in the external memory 14 but also the data processed by the first processor 10 into the second memory 13. In this way, after the instruction code group is stored in the second memory 13 in a predetermined order, the first processor 10 performs arithmetic processing internally and externally via input/output ports. Performs original functions such as control and data transfer. On the other hand, the second processor 12 uses the second memory 13 as a program memory, sequentially reads out its contents, takes in the instruction code internally through the internal data bus 16, performs initialization, and then reads the information in the second memory 13. Processing is controlled as a command. Note that the first processor 10 and the second processor 12 can operate in parallel while maintaining their relationship with each other.
It will perform many functions. For example, as the first processor 10, a highly versatile processor that has a slow processing speed but has multiple functions under the control of the program in the first memory 11 is used, and as the second processor, a processor that has a fast processing speed but a small number of processors is used. Even if a processor with only special functions is used, the contents of the program memory of the second processor 10 can be easily rewritten by the first processor 12, and as a result, the contents of the program memory of the second processor 10 can be easily rewritten. The processor 12 has multiple functions, and the capabilities of the microcomputer are significantly improved.

Note that the contents of the second memory 12 may be rewritten not only at the start of operation of this microcomputer, but also during the process.

As explained above, the present invention is a microcomputer having two processors, in which the program memory of one processor is configured with a rewritable memory, and the contents can be changed or added using the other processor. It is possible to provide an epoch-making microcomputer with the following functions.

Furthermore, although the embodiment has been explained at the chip level (of course, it is most effective to incorporate this configuration into one chip), even if this configuration is applied within one housing, the effect of expanding the housing functions cannot be obtained. It will be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example of a microcomputer, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1...Processor, 2...Program memory,
3... Data memory, 4, 15, 16... Internal data bus, 5, 6, 19, 20... Address register, 10... First processor, 11... First
memory, 12... second processor, 13...
Second memory, 14...external memory, 17...external data bus, 18...external address bus, 21
...Data control circuit, 22...Address control circuit.

Claims (1)

[Claims] 1. At least a first processing device in the same unit, a first memory used as a program memory for the first processing device, and a readable and writable memory used as a data memory for the first processing device. a second memory, and a second
a processing device, the second memory is connected to the first memory via an address control circuit and a data control circuit.
and a second processing device, and according to the program in the first memory, the first processing device reads out a program for the second processing device from a memory outside the unit and transfers it to the second processing device. 2. An information processing apparatus characterized in that the second memory is used as a data memory for the first processing apparatus and as a program memory for the second processing apparatus.