JPS62150459A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To improve throughput while eliminating the overhead due to scrambling for buses by providing an internal address data bus and an external address data bus independently while incorporating plural CPUs. CONSTITUTION:An internal memory 103 and an internal I/O interface 104 are accessed by a CPU100 via an internal address data bus 114. Further, the external memory 105 and the external I/O interface 106 are accessed by a CPU100 via internal address data buses 114, 121 and an external address data bus 113 coupled by a bus controller 102 and a buffer 111. On the other hand, the internal memory 109 and the internal I/O interface 110 are accessed by a CPU101 via the internal address data bus 120. Further, the external memory 107 and the external I/O interface 108 are accessed via the external address data bus 117.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a high-performance single-chip microcomputer with a plurality of built-in central processing units. The present invention relates to a high-performance single-chip microcomputer equipped with a memory, an input/output interface, etc., and a built-in bus control device that allows each central processing unit to access an external address/data bus of other central processing units.

(2) Prior art With the increase in the integration density of integrated circuits, the functions and performance of microcomputers are rapidly increasing due to VCC and various peripheral circuits (A
With the integration of circuits (such as /D converters, timers, DMA control circuits, etc.), various types of microcomputer systems have been constructed and used.

However, as the real-time processing required to control peripheral integrated circuits (I10 processing) increases and the amount of data processed increases, the processing capacity required of the central processing unit (hereinafter abbreviated as CPU) has also increased dramatically. Processing by a single CPU is reaching its physical limit. For example, a processing request from a peripheral integrated circuit is normally notified to the CPU in the form of an interrupt, and the CPU responds to the corresponding I10
Processing and data processing. However, as the number of peripheral integrated circuits increases, the number of interrupts also increases, and the amount of I10 processing and data processing that the CPU must execute continues to increase. It is necessary for the CPU to execute these processes in real time, but since the burden of processing on only a single CPU is too great, the current situation is that real-time performance has to be sacrificed to some extent.

As a way to avoid sacrificing real-time performance, CP
One idea is to reduce the load on U, and for this purpose a distributed processing system using multiple CPUs has been proposed. This is a system in which the processing performed by the CPU is subdivided into EL processing, data processing, etc. according to its function, and a dedicated CPU is assigned for each processing. The system configuration of such a microcomputer system is shown in FIG. 1, and will be explained below based on the same figure.

In FIG. 1, memory l is read-only (R
OM>, or one that can be read and written (R
AM), or a mixture of both (hereinafter, the term memory is used in the same sense as memory 1). The CPU 2, which performs data processing, has its own address and data bus 8, which can be coupled to the system address and data bus 10 via the bus control device 4. On the other hand, the CPU 3 performing the I10 processing can be coupled to the system address and data bus 10 via its own address and data bus 9 by means of the bus controller 'i14. Address/data bus 10 includes memory 1 and I10.
Interface 7 etc. are connected. , the CPU 3 uses the I10 interface 7 to exchange data with external devices.

In the microcomputer system shown in FIG. 1, programs and data for two CPUs 2 and 3 are stored in a memory 1 connected to a system address/data bus 10. The CPU 2 accesses the memory 1 via the address/data bus 10, and the CPU 3 accesses the memory 1 via the address/data bus 10 for instruction code fetch operations, read/write operations of various calculation data to the memory, and data write/read operations for the I10 interface 7. Memory 1. This is accomplished by accessing I10 Inter 7 Eighth 7 via the same address and data bus 10.

However, the address/data bus 10 can only be connected to one CP at a time.
In order to control this, the bus control device 4 manages the allocation of the right to use the address/data bus 10 to the CPUs 2 and 3.

Assume that the CPU 2 is currently executing data processing.

At this time, the hold signal line 13 is at a low level, the hold signal line 14 is at a high level, and C1) and U3 are in a hold state. After completing data processing, CPU2
Signals are output to the processing request request line 5 and the path switching request signal line 11, respectively. In order to cope with this, the bus control device 4 sets the hold signal line ]3 to a high level so that the bus 8 and the bus 10
The address/data bus 10 is connected to the address/data bus 9 of the CPU 3. Thereafter, the hold signal line 14 is set to a low level to release the CPU 3 from the hold state and cause the CPU 3 to execute processing. CPU
3 outputs signals to the I10 processing completion notification signal line 6 and the bus switching request signal line 12, respectively, when the I10 processing is completed. In response to this, the bus control device 4 sets the hold signal line 14 to high level to put the CPU 3 into a hold state, and then couples the address/data bus 10 to the address/data bus 8 of the CPU 2, and connects the hold signal line 13 to the hold signal line 13. It is set to low level and causes the CPU 2 to resume data processing.

In such a microcomputer system, since the address/data buses 8.9 are coupled to one address/data bus 1o, the address/data buses 10
CPU 2 and CPU 3 cannot execute programs at the same time, and CPU 3
During the processing, execution of data processing by the CPU 2 is stopped, which has the disadvantage that the processing capacity of the computer system is significantly reduced. In other words, even if a plurality of dedicated CPUs are provided on the same semiconductor substrate, unless the problem of bus usage is resolved, processing performance will not improve in the sense of this description. Therefore, there is a strong demand for a system in which the processing capabilities of each CPU are synergistically integrated without reducing the processing capabilities of each CPU.

(2) Purpose of the Invention The purpose of the present invention is to integrate an internal memory and an internal I10 interface that can be accessed at high speed at all times by a plurality of CPUs integrated on the same semiconductor substrate.

In particular, by providing a system that does not cause bus contention when the CPU accesses external hardware resources, we have achieved a significant improvement in processing capacity, and when each CPU performs inter-CPU synchronization processing and communication processing, An object of the present invention is to provide a new bus control device that enables a CPU to access external hardware resources at high speed.

(3) Structure of the Invention The single-chip microcomputer of the present invention is a single-chip microcomputer in which a plurality of CPUs are integrated on the same semiconductor substrate. It has a built-in memory and an input/output interface device corresponding to the CPU, and an address/data bus corresponding to the CPU and an address/data bus corresponding to the CPU to enable each of the CPUs to access an external memory and an external input/output interface device. A major feature of the CPU is that it integrates a bus control device that allows other CPUs to access the address/data bus.

(4) Examples Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a single-chip microcomputer according to an embodiment of the present invention.

The CPU 100 via the address/data bus 114
Access internal memory 103 internal I10 interface 104. Furthermore, the CPU 100 is a bus control device 102.
an address and data bus 114,1 coupled by
21, an external memory 105 and an external processing interface 106 are accessible via an external address and data bus 113 coupled by a buffer 111.

10,000, CPU10I is an internal memory 109 via an address/data bus]20, an internal I10 interface 110
access. Furthermore, CPU10I is the bus control device 1.
Address and data bus 120 coupled by 02
, 122, and the external memory 107 via the external address/data bus 1]7 connected by the buffer 112.
The external interface 108 can be accessed.

Bus m11m device 1102 is address/data bus 11
4, 120 to the address/data bus 121 or address/data bus 122, and set the Hall) signal lines 115, 119 to high level, respectively, and
It has a function of independently controlling the PU100 and CPU10I to a hold state. Register write signal line 116
, 118 & each h CPU 100 , CPU10
1 becomes high level when data is written to a register in the bus controller 102.

Internal hardware resource access signal lines 123 and 124 allow the CPU 100 and CPUl0I to access internal hardware resources (internal memory 103 and internal interface 104 for CPU 100, internal memory 1J109 and internal I10 interface 11
0), which are generated by the CPUs 100 and 101, respectively.

In the figure, according to a preferred embodiment, blocks surrounded by dotted line A are integrated on one semiconductor chip.

Next, one embodiment of the bus control device 1102 will be described using FIG. 3. The bus control device 102 includes bus switch signal generators 200 and 201 and an arbiter 202 with a bus switch. Bus switch signal generator 200,
201 determines whether or not to switch the address/data bus 114 to the address/data bus 122 and the master address/data bus 121' to the address/data bus 121 based on the values set in the registers built therein. When performing bus switching, a bus switching request signal i 20 is sent to the address/data bus 114.
Set 5 to high level. On the other hand, address/data bus 1
20, the bus switching request signal line 206 is set to high level. Bus switch signal generators 200 and 201
The contents of the registers within can be rewritten by instructions from CPU100 and CPU101, respectively.
．． 101 are register write signals i 116 , 118
to make it a no-ireperu.

The arbiter 202 with a bus switch switches the bus according to the levels of the bus switching request signal lines 205 and 206, and also switches the bus according to the levels of the bus switching request signal lines 205 and 206.
CPU 100 according to the level of 123, 124
, has a function of placing the CPU 101 in a hold state.

Bus controller 102 includes address/data bus 114 . ! The address/data bus 120 of the CPU 101 is coupled to the address/data bus 121 or the address/data bus 122, and the bus contention at that time is summarized in FIG. 4.

When the CPU 100 and the CPU 101 are accessing the bus indicated by the area 300 surrounded by dotted lines, no bus contention occurs. When the CPUs 100 and 101 are accessing the bus indicated by the area 301 surrounded by dotted lines, each CPU is accessing its own external address/data bus.

Therefore, no bus contention occurs at this time either. CPU100
, when the CPU 101 is performing a bus access indicated by an area 302 surrounded by a dotted line, the bus access is 1
Bus contention occurs because the data is concentrated on two external address and data buses. At this time, the bus control device 102 is connected to one of the CPUs.
Overhead occurs because the data is placed in a hold state. C
Area 303 where PU100°CPUl0I is surrounded by a dotted line
When performing bus access shown by, each CPU:
Each accesses the external address/data bus of another CPU, so no bus contention occurs.

As stated above, bus contention occurs in the single-chip microcomputer according to the present invention because:
Bus contention does not occur in other cases, only when each CPU accesses the same external address/data bus. Moreover, although each CPU accesses the same-local external address data bus usually when synchronization processing and communication processing are performed between each CPU, each CPU spends most of its execution time on other processing. Therefore, in the single-chip microcomputer according to the present invention, the processing capacity of the system is greatly improved.

A more detailed configuration and operation of the bus-switched arbiter 202 will be described based on FIG.

Arbiter 202 with bus switch is bus switch 400
, 401, and an arbiter control section 402. It is assumed that the bus switching signal lines 403 and 404 and the path switching request signal lines 205 and 206 are coupled to the address/data bus 203 to the address/data bus 121 and the address/data bus 204 to the address/data bus 122 at low level. When the bus switching request signal line 205 becomes high level, the arbiter control unit 402 sets the hold signal line 119 to high level when the internal hardware resource access signal line 124 is low level, and at the same time sets the CPU10I to the hold state, the bus switching signal line 403 is set to high level. The address/data bus 203 is set to high level and the address/data bus 203 is set to high level.
Coupling to data bus 405. Address/data bus 4
05 is connected to the address/data bus 122, and the address/data bus 203 is connected to the address/data bus 12.
It is connected to 2. Therefore, the CPU 100 uses the address
Through data bus 122, hardware resources on external address data path 117 are accessed. after that,
When the bus switching request signal line 205 becomes low level, the arbiter control unit 402 sets the hold signal line 119 to low level, puts CPU10I into the execution state, and at the same time sets the bus switching signal line 403 to low level, changing the address/data bus 203 to the address/data bus. 121.

In the initial state, when the internal node hardware resource access signal @124 is at the no level, the arbiter control section 402 does not operate the hold signal lines 1 to 9, but only performs bus switching.

The same applies when the bus switching request signal line 206 becomes high level.

When the bus switching request signal lines 205 and 206 become 71 levels at the same time, the arbiter control unit 402 simultaneously sets the bus switching signal lines 403 and 404 to 71 levels, and changes the address/data bus 203 to the address/data bus 405.
, address and data bus 204 is coupled to address and data bus 406 . address/data bus 405,
406 are address/data buses 122 and 12, respectively.
1, so the address/data bus 203
, 204 are address/data buses 122 and 121, respectively.
combined into.

Next, assuming that the bus switch signal generating sections 200 and 201 are the same, a more detailed configuration and operation of the bus switch signal generating section 200 will be described.

When the CPU 100 accesses the address area specified by the internal register, the bus switch signal generating unit 200 transfers the CPU 101 to the corresponding CPU 101f7) address area.
The bus switching request signal line 205 is set to no-repel so that the bus switching request signal line 205 is automatically accessed.

For example, in FIG. 6, the address space 5 of the CPU 100
When the CPU 100 accesses the address area 503 of 02, if data is set in the register in the bus switch signal generation unit 200 so that the bus switching request signal 11g1205 becomes high level, the arbiter with a path switch 202 determines that the CPU 100 When accessing the address area 503, the corresponding CPU 1 as indicated by an arrow 504
Bus switching is performed to access address area 505 of 01.

This will be explained below with reference to FIG.

In FIG. 7, decoder 601 decodes the upper three bits of the address bus portion of address/data bus 114. The 8-bit register 602 holds data written by the CPU 100 instruction. 2 person AND gate 60
3 outputs the output of the decoder 601 and the AND between corresponding pits of the register 602. 8 person OR gate 60
4 outputs the OR of the outputs of the eight AND gates 603.

The register write signal line 116 is set to high level when the CPU 100 writes data to the register 602. The register 602 is part 4 of the 8 divisions of the address space of the CPU 100.
Since this is an 8-pit register corresponding to the pits, only the 6th bit of the register 602 is set to 1, and all other pits are set to 0. When the CPU 100 accesses an area other than the 7th address area of the address space divided by 8, the 6th bit of the decoder 601 is always 0, so the AND output with the corresponding register 6020 bits is all 0. The output of OR gate 604 becomes 0. Therefore, the bus switching request signal line 205 becomes low level, and bus switching by the bus switch arbiter 402 does not occur.

When the CPU 100 accesses the seventh address area of the eight-divided address space, only the sixth bit of the output of the decoder 601 becomes 1, and the sixth bit of the register 602 becomes 1.
The AND output between the pits becomes 1. Therefore, the output of the 8-person OR game) 604 becomes high level, and the bus switching request signal line 205 becomes high level. The arbiter 202 with a bus switch sets the hold signal line 119 to a high level to put the CPU10I in a hold state, and simultaneously switches the address/data bus 203 to the address/data bus 122.
CPU 100 is coupled to external address/data bus 1.
access hardware resources on 17.

The above state is shown in FIG. 6 using an address space diagram of CPU 100 and CPU ]01. Figure 6 shows the CPU10
1, and an address space 502 for the CPU 100.
A shaded area 503 is the seventh area of the eight divided address spaces.

When the CPU 100 accesses the address area 503, the seventh address area 5 of the corresponding CPUl0I
05 is automatically accessed as indicated by arrow 504.

As described above, the bus switch signal generating section 200 automatically decodes the upper 3 bits of the address bus and then outputs the AND signal.
High-speed bus switching is realized by operating the bus switching request signal line 205 using a small-scale circuit using gates and OR gates. Register 602 contains CP
Data can be written to CP by command of U100.
U100 is for an arbitrary address space area divided into 8,
The address space area corresponding to CPUl0I can be accessed. In the above embodiment, the number of input bits of the decoder 601 is 3 and the register 602 is an 8-pit register, but the bits may have different values. Further, although the bus switch signal generating sections 200 and 201 are considered to be the same, they may be different.

Next, the operation of the non-glue chip microcomputer according to the present invention will be specifically explained based on FIGS. 2 and 4.

When the CPU 100 and CPU 101 are currently accessing their own external address/data buses 113 and 117, the address/data bus 114 is connected to the address/data bus 121, and the address/data bus 120 is connected to the address/data bus 122. The hold signals @ 115 and 119 are at low level, and the write signal lines 116 and 118 to the register in bus control unit fJjt 102 are at low level. Internal hardware resource access signal lines 123 and 124 are both at low level. At this time, the CPU 100 connects to the external memory 105 via the external address/data bus 113.
, the external I10 interface 106 is accessed, and the CPU I0I accesses the external memory 107 and the external I10 interface 10 via the external address/data bus 117.
8. Therefore, no bus contention occurs. At this time, the system is accessing the bus indicated by an area 301 surrounded by dotted lines in FIG. In the above state, when the CPU 100 accesses an address area that is not specified by the register in the bus control device 102, the bus control device 102 sets the hold signal line 119 to a high level and the CPU
placing l0I in a hold state while simultaneously coupling address/data bus 114 to address/data bus 122;
The CPU 100 and the CPU 10I perform bus accesses indicated by an area 302 surrounded by a dotted line in FIG. In this state, CPU 100 accesses hardware resources on external address/data bus 117. At this time,
The CPU 100 competes for the address/data bus 122.
, and the CPU 101, causing an overhead since the CPU 10I is placed in a hold state. However, since the bus control device 1102 switches buses at high speed, there is no overhead due to bus switching.

Next, when the CPU 100 finishes accessing the address area specified by the register in the bus control bag [102,
The path control bag f102 sets the hold signal i 119 to low level and puts the CPU 10I into the execution state, and at the same time changes the address/data bus 114 to the address/data bus 121.
CPU 100 and CPU 101 perform bus access shown in area 301 surrounded by dotted lines in Table 1. Therefore, no bus contention occurs at this time. In the initial state, when the CPU 100 accesses its own external address/data bus 117\ and CPUl0I accesses its own internal address/data bus 120, CPUl0I
sets the internal hardware resource access signal line 124 to high level and accesses the internal hardware resources, and since bus contention does not occur, the bus control device 102 only performs bus switching and does not operate the hold signal line. do not have.

The above description also holds true when CPU10I accesses the address area specified by the register in the bus control device ]02.

Furthermore, in the above embodiment, when bus contention occurs, priority is given to the access of the CPU 100 to the address/data bus 122, and the access of the CPU 10I to the address/data bus 121, but the priority order is reversed. It is also possible to give priority to the access of the CPU 10I to the address/data bus 122 and the access of the CPU 100 to the address/data bus 121. In that case, in the above description, when bus contention occurs, only the CPU that enters the hold state changes, and other parts of the description do not change. CPU
100, the CPU 101 simultaneously operates the bus control device 1.
Specified by the register in 02.

When accessing the address area, CPU100CP
The UIOI is indicated by the area 303 surrounded by the dotted line in Table 1.
Perform bus access. The bus controller 102 couples the address/data bus ]-14 to the address/data bus 122 and simultaneously couples the address/data bus 120 to the address/data bus ]21 so that the CPU 100
, CPU 301 each have external address/data bus 1.
17 and 113, no bus contention occurs. After that, when the CPU 100 accesses some of the address/data buses 114, the CPU 100,
The CPU 101 is located in the area 30 surrounded by the dotted line in the wJ4 diagram.
Bus contention does not occur because the bus access indicated by 0 is performed.

(5) Effects of the Invention As described above, the single-chip microcomputer according to the present invention has a plurality of built-in CPUs, each of which independently owns an internal address/data bus and an external address/data bus. , there is no overhead due to competition for the bus, and a significant improvement in processing performance has been achieved. In addition, since each CPU has a built-in bus control device that performs high-speed bus switching so that each CPU can access the external hardware resources of other CPUs, bus contention occurs only when multiple CPUs access the same external address/data bus at the same time. occurs, and some CPUs enter the hold state, but in other cases no bus contention occurs. Therefore, processing power has been greatly improved.

When a CPU accesses any address area determined by a register that can be set by an instruction, the bus control device automatically connects the CPU's address/data bus 7 to the external address/data bus of another CPU, thereby performing bus switching. There is no need to use instructions, and software overhead can be greatly reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional microcomputer system, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a bus control device, Fig. 4 is a bus access state diagram, and Fig. 5 is a block diagram of a conventional microcomputer system. is a block diagram of an arbiter with a bus switch,
FIG. 6 is a diagram of the address space of the CPU, and FIG. 7 is a block diagram of the bus switch signal generator. 1...Memory, 2...Data processing C
PU, 3...El processing CPU, 4...
・Bus control device, 5...El processing request signal line,
6... I10 Processing completion notification No. 4g N, 7...
...I10 interface, 8,9.10...
... Address data bus, 11.12 ... Bus switching request signal line, 13.14 ... Hold signal line, 100° 101 ... CPU, 102
...Bus control device, 103.109...
・Internal memory, 104, 110...Internal I10
Interface, 105.107...External memory, 106.108...External I10 interface, 111.112...Buffer, 113,
117...External address/data bus, 114
,120,121.122... Internal address
Data bus, 115, 119... Hold signal line, 116, 118... Register write signal line, 123, 124... Internal hardware resource access signal line, 200, 201・・・・・・
Bus switch signal generator, 202... Arbiter with bus switch, 2 (13, 204... Address/data bus, 205, 206...
Bus switching request signal line, 300. :(01,302,3
03... Area indicating bus access status, 400
, 401... bus switch, 402...
...Arbiter control unit, 403, 404...
Bus switching signal line, 405, 406...address/data bus, 501.502...address space diagram, 503.505...address space 1
Section, 601... Decoder, 602...
8-bit register, 603...2-person AND gate, 604...8-person OR gate. Agent Patent Attorney Susumu Uchihara 3rd Concave CPU10I Written 4 times

Claims (1)

[Claims] In a single-chip microcomputer in which a plurality of CPUs are integrated on a single semiconductor substrate, the plurality of CPUs
built-in memory and input/output interface devices corresponding to each of the CPUs that are accessed via dedicated address/data buses, and each of the CPUs is capable of accessing external memories and external input/output interface devices; A single-chip microcomputer, characterized in that an address/data bus corresponding to the CPU and a bus control device that allows the CPU to access the address/data bus of other CPUs are integrated.