JPH10154124A - Microprocessor and multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microprocessor which has the degree of freedom to the acquisition and release of a bus right which are performed by handshake. SOLUTION: When a microprocessor 1 is assigned to a master processor in a multiprocessor system, and when bus right release permission control information (BREQEN) is initialized to an inactive state by system reset, etc., a bus arbitrating circuit 20 nullifies a bus right release request that is externally asserted by a bus right release request signal (BREQ) arid maintains bus right release permission control information in an inactive state until required processing that is accompanied with an external bus access is completed. Thereby, it is possible to maintain a bus right independently of an external bus release request.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor having a function of controlling acquisition and release of a bus right to the outside by a handshake, and more particularly to a technique for giving a degree of freedom to release a bus right. In a multiprocessor system in which a shared resource requiring initialization, such as a synchronous DRAM, is connected to a common bus, the present invention is applied to prohibit unauthorized access before the shared resource is initialized. And effective technology.

[0002]

2. Description of the Related Art In a multiprocessor system, with respect to transfer of a bus occupation right for each microprocessor to access a shared resource, one microprocessor is set as a master processor and initially acquires the bus right. The remaining microprocessors are slave processors, and acquire the bus right from the master processor as needed. At this time, the priority of the bus right request from the slave processor is set higher than the bus right on the master side. Therefore, when the master processor requests a bus right from a slave processor, the master processor releases the bus right immediately after the end of the bus cycle of the master processor.
For example, when a system reset is performed, the master processor initially acquires the bus right. The master processor
When the bus right request signal supplied from the slave processor is asserted, the bus right is released immediately after the end of the bus cycle of the master processor, and the bus right acknowledge signal is asserted. The slave processor recognizes the release of the bus right by asserting the bus right acknowledge signal, and starts a bus cycle. When acquiring the bus right, the slave processor recognizes the bus right request from the master processor by negating the bus acknowledge signal,
After the bus cycle of the slave processor is completed, the bus right is released and the bus right request signal is negated. As a result, the master processor acquires the bus right again.

An example of a document describing a multiprocessor system is “Microcomputer Handbook”, pp. 674 and 675, issued by Ohm Co., Ltd. on December 25, 1985.

[0004]

In controlling the acquisition and release of the bus right by the handshake described above, the microprocessor has no degree of freedom in releasing the bus right. The master processor must release the bus right upon receiving a bus release request from the slave processor, and the slave processor immediately releases the bus right when the approval of the bus release from the master processor is withdrawn. Must be released. Therefore, the microprocessor may not be able to continue to occupy the bus until it completes the predetermined process, whether it is a slave or a master. That is, there is no degree of freedom in releasing the bus right. For this reason, from the viewpoint of speeding up data processing and reliability of data processing, there has been a problem in system applications that require a series of certain processes via a bus.

For example, in the above-described multiprocessor system, some of the shared resources connected to the common bus require initialization for operation and some do not. SRAM is a shared resource that does not require initialization
(Static Random Access Memory) and DRAM (Dynamic
Random Access Memory). Examples of the shared resources that require initialization include a synchronous DRAM.
In a synchronous DRAM, normal operation is enabled only after the burst length, latency, and the like are initialized.

With respect to the shared resources that do not require initialization, if the master processor and the slave processor acquire and release the bus right by handshaking according to their respective operation programs, both processors can normally access the shared resources.

On the other hand, when a plurality of processors share a resource requiring initialization, the slave processor gives the master processor a bus right even before the master processor completes the initialization of such a shared resource. Can be issued. The master processor immediately releases the bus right in response to a request for the bus right from the slave processor, so that when the slave processor accesses the uninitialized shared resource, its normal operation cannot be guaranteed. .

[0008] It has been clarified by the present inventors that one solution to this problem is to have a degree of freedom in acquiring and releasing the bus right by handshaking. Conventional macroprocessors did not consider the solution. In such a case, it is considered necessary to prepare a special circuit outside the microprocessor on the multiprocessor system. Although it is not publicly known, for example, when the master processor initializes the shared resources, it is necessary to provide an external circuit that negates the reset signal for the slave processor after the initialization is completed by the master processor when performing a system reset. Can be. Also, an initialization completion flag is provided for shared resources that require initialization, the master processor sets the flag after initialization is completed, and the slave processor checks the flag setting state before starting access. I can do it. Alternatively, it can be considered that the slave processor can be controlled to be in a standby state immediately after the reset, and after the initialization operation by the master processor is completed, an interrupt signal generating circuit for releasing the standby state of the slave processor can be provided. Can be

However, in any case, a special external circuit must be configured on the system, and the processing is expected to be complicated in terms of software.

It is an object of the present invention to provide a microprocessor which can have a degree of freedom in acquiring and releasing a bus right by handshaking. In particular, such a degree of freedom can be controlled by an operation program of the CPU.

Another object of the present invention is to provide a microprocessor capable of ignoring an external bus right request until the initialization of an external peripheral circuit is completed.

Still another object of the present invention is to eliminate the possibility that a shared resource requiring initialization is arbitrarily accessed before the completion of the initialization to cause a malfunction. It is an object of the present invention to provide a multiprocessor system which does not need to configure a special external circuit or complicate processing by software.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[0015] The first microprocessor, which is provided with a degree of freedom regarding acquisition and release of a bus right by handshaking, includes a CPU for executing a fetched instruction on a semiconductor substrate, and the operation mode of the microprocessor is set as follows. First storage means in which master / slave mode control information for initially determining a master mode having the bus right or a slave mode for acquiring the bus right is set, and rewritable by the CPU A second storage unit in which the bus right release permission control information is initially set, and the bus right release set in the second storage unit when a master mode is set by the master / slave mode control information. When the permission control information is in an inactive state, the bus right release permission control information is inverted to an active state. Bus arbitration means for invalidating a bus right release request by asserting a bus right release request signal from the outside until the bus right release request signal is asserted.

When the microprocessor is assigned to a master processor in a multiprocessor system and the bus release permission control information is initialized to an inactive state due to a system reset or the like, the bus arbitration means issues an external bus release request. Since the bus right release request due to the assertion of the signal is invalidated, the bus right release permission control information is maintained in an inactive state until the required processing involving the external bus access is completed, so that an external bus release request can be satisfied. Can maintain the bus right independently. That is,
The microprocessor can have a degree of freedom in acquiring and releasing the bus right by handshaking. In addition, the second storage means for storing the bus right release permission control information can be accessed and rewritten by the built-in CPU. Therefore, such a degree of freedom can be controlled by the operation program of the CPU.

In the period during which the bus right is maintained, the microprocessor completes the initialization of a peripheral circuit as a shared resource requiring an initialization operation in a multiprocessor system, for example. After the completion, the CPU reverses the bus right release permission control information to the active state, so that the bus arbitration unit releases the bus right in response to the assertion of the bus right release request signal from the outside. As described above, the microprocessor includes:
When performing the initialization of an external peripheral circuit, the external bus request can be ignored until the initialization is completed. The possibility of occurrence can be eliminated, and for this purpose, it is not necessary to configure a special external circuit on the system or perform complicated processing in terms of software.

Considering such an initialization operation immediately after the reset operation of the microprocessor in which the master mode is set, the first storage means stores the master data in response to the reset operation of the microprocessor in terms of usability of the microprocessor. Slave mode control information is initialized, and the second storage means initializes inactive bus right release permission control information in response to the setting of the master mode by the master / slave control information. Desirably.

Another second microprocessor from the viewpoint that the microprocessor has a degree of freedom regarding acquisition and release of the bus right by handshaking is set in the second storage means in a state where the slave mode is set. When the bus release permission control information is active, the bus that invalidates a bus release request by negating an external bus release approval signal until the bus release permission control information is inverted to an inactive state. Adopt arbitration means.

According to this microprocessor, when the microprocessor is assigned to a slave processor in a multiprocessor system, when the bus arbitration means asserts a bus right release request signal to the master processor, the bus right release acknowledge signal responds thereto. Is asserted by the master processor to acquire the bus right. In this slave processor, the bus right release permission control information is initialized to an active state by a system reset or the like. Therefore, once the bus right is acquired as described above, the bus arbitration means is external (master processor).
Bus release request by negating the bus release acknowledge signal from the master processor by maintaining the bus release permission control information in an active state until the required processing involving external bus access is completed. Bus right can be maintained regardless of the negation state of the bus acknowledge signal. That is, this microprocessor can have a degree of freedom in acquiring and releasing the bus right by handshaking. In addition, since the first storage means in which the bus right release permission control information is stored can be accessed and rewritten by the built-in CPU, such a degree of freedom can be controlled by an operation program of the CPU.

Considering the case where the bus right is acquired from the master processor immediately after the reset operation of the microprocessor in which the slave mode is set and the initialization operation accompanied by the bus access is required for a certain period is taken into consideration, In terms of the usability of the processor, the first storage means has master / slave mode control information initialized in response to a reset operation of the microprocessor, and the second storage means has a slave mode setting based on master / slave control information. It is desirable that the active bus right release permission control information is initialized in response to the request.

Still another third microprocessor from the viewpoint that the microprocessor has a degree of freedom regarding acquisition and release of a bus right by handshaking is a bus arbitration means of the first microprocessor and a second microprocessor. Has both bus arbitration means. Such a microprocessor, whether used as a master or a slave, has the freedom to acquire and release the bus.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

[Microprocessor] FIG. 1 is a block diagram showing a microprocessor according to an example of the present invention. The microprocessor 1 shown in FIG. 1 is a 32-bit RISC (Red
uced Instruction Set Computer) architecture and executes 16-bit fixed-length instructions.

The microprocessor 1 has a floating point unit 2. Further, the microprocessor 1 has a central processing unit (CPU) 3, which is an integer unit capable of processing integers. The CP
U3 is coupled to the floating point unit 2 via a 32-bit data bus 4. The CPU 3 and the floating point unit 2 fetch an instruction from the instruction cache unit 6 via the instruction bus 5. The instruction address is provided from the CPU 3 to the instruction cache unit 6. The data cache unit 7 is connected to the data bus 4, and receives a data address from the CPU 3 via the data address bus 8. The data cache unit 7 and the instruction cache unit 6 include a cache controller and a cache memory, respectively, which are not shown.
The instruction cache unit 6 and the data cache unit 7 are connected to a bus controller 9 via a cache bus 13 including a data signal and a control signal. An instruction address for external access caused by a cache miss or the like in the instruction cache unit 6 is given to the bus controller 9. A data address for an external access due to a cache miss or the like in the data cache unit 7 is given to the bus controller 9. The bus controller 9 responds to the instruction address or the data address by using an address bus 3 coupled to an address output terminal 31 shown in FIG.
3 and a data bus 3 coupled to the data input / output terminal 30
2 to start an external bus cycle for accessing an external memory or the like. A peripheral circuit 10 such as a timer and a serial communication interface controller is connected to the bus controller 9 via a peripheral bus 11. The microprocessor shown in FIG.
It is formed on one semiconductor substrate such as single crystal silicon.

The floating point unit (hereinafter simply referred to as FPU
2) will request data or instructions from memory for floating point processing. The FPU 2 comprises:
It does not have a memory addressing capability for storing data in the cache memory of the data cache unit 7 or acquiring data from the cache memory.
This is to save chip area by eliminating the need for the memory addressing circuit of FPU2. Instead, the CPU 3 has a function of addressing a cache memory or the like instead of the FPU 2. Therefore, FPU2 or floating point instructions
It is not necessary to support the same powerful addressing mode as that of the CPU 3, and the CPU 3 bears all the functions. CPU
3 not only fetches data from memory for FPU2, but CPU3 also fetches all instructions from memory for FPU2, including floating point instructions. The instruction is taken into both the CPU 3 and the FPU 2 and decoded. The CPU 3 outputs the decoded instruction to the CPU
If it is an instruction, it executes the integer processing indicated by the instruction. Further, the CPU 3 determines that the decoded instruction is FP
If the instruction is a U instruction, an addressing process to be executed in place of the FPU 2 is performed. When the decoded instruction is an FPU instruction, the FPU 2 executes a floating point process indicated by the instruction. When the decoded instruction is a CPU instruction, the FPU 2 ignores the instruction.

The microprocessor 1 has master / slave mode control information for determining whether the operation mode of the microprocessor 1 is a master mode having an initial bus right or a slave mode for acquiring a bus right as required. It has a register 22 in which MSMD is set. Master / slave mode control information MSMD is determined by the state of mode signal MD. The mode signal MD is made significant when a predetermined change is given to the reset signal RESET and a reset operation is instructed, and as a part of the reset operation, the master mode or the slave mode is determined. In FIG. 1, reference numeral 34 denotes an input terminal of the mode signal MD, and reference numeral 35 denotes an input terminal of the reset signal RESET.

The microprocessor 1 shown in FIG. 1 has a function of controlling acquisition and release of a bus right by handshake. For this purpose, a bus arbitration circuit 20 is provided. The bus arbitration circuit 20 is connected to an interface terminal 32 of the bus right release request signal BREQ and an interface terminal 33 of the bus right release acknowledge signal BACK.

In the master mode, the bus arbitration circuit 20
Is supplied with a bus right release request signal BREQ from outside,
The bus right release acknowledge signal BACK is output to the outside. At this time, when the bus right release request signal BREQ is asserted, the bus arbitration circuit 20 releases the bus right after completing the currently executed bus cycle, and releases the bus right release acknowledge signal BACK.
Assert When acquiring the bus right, the bus right release acknowledge signal BACK is negated to request the bus right release externally, and in response to this, the system waits until the bus right release request signal BREQ returned from the outside is negated. To get the bus right.

In the slave mode, the bus arbitration circuit 20
Receives a bus right release acknowledge signal BACK from outside,
The bus right release request signal BREQ is output to the outside. At this time, when acquiring the bus right, the bus arbitration circuit 20 asserts the bus right release request signal BREQ to the outside and waits for the bus right release acknowledge signal BACK returned from the outside in response to the assertion. You can get the bus right. When the bus right release acknowledge signal BACK is negated,
After completing the currently executed bus cycle, the bus right is released and the bus right release request signal BREQ is negated.

In the bus release state, the bus controller 9 is connected to the output terminal 31 connected to the external address bus 33.
And the data input / output terminal 30 coupled to the external data bus 32 are controlled to a high output impedance state.

In particular, the microprocessor 1 controls the signal B
A register 21 for storing bus right release permission control information BREQEN in order to allow a degree of freedom in handshake control regarding acquisition and release of a bus right by REQ and BACK.
Having. This register 21 is a type of control register made accessible by the CPU 3.

In the master mode, the bus arbitration circuit 2
0 is the bus release request signal BR when the bus release permission control information BREQEN is inactive.
The bus right release request by the assertion of the EQ is invalidated. That is, when the microprocessor 1 is assigned to a master processor in a multiprocessor system,
When the bus right release control information BREQEN is initialized to an inactive state, the bus arbitration circuit 20 invalidates a bus right release request by asserting the bus right release request signal BREQ from outside. Therefore, the microprocessor 1 in which the master mode is set keeps the bus right release permission control information BREQ until the required processing involving the external bus access is completed.
By keeping EN inactive, the bus right can be maintained irrespective of the externally asserted state of the bus right release request signal BREQ. That is, the microprocessor 1 can have a degree of freedom in acquiring and releasing the bus right by handshaking. Moreover, the register 21 storing the bus right release permission control information BREQEN
Can be accessed and rewritten by the built-in CPU 3, such a degree of freedom can be controlled by an operation program of the CPU 3.

In the slave mode, when the bus right release permission control information BREQEN is activated, the bus arbitration circuit 20 outputs the bus right release approval signal BA.
Invalidates a bus right release request by negation of CK. That is, when the microprocessor 1 is assigned to a slave processor in a multiprocessor system, the bus arbitration circuit 20 asserts the bus right release request signal BREQ to the master processor, and sends a bus right release acknowledge signal BACK in response thereto from the master processor. The bus right can be acquired by being asserted. When the bus right release permission control information BREQEN is activated in the microprocessor 1 in which the slave mode is set, when the bus right is once acquired as described above, the bus arbitration circuit 20 is connected to the external (master processor). )
, The bus right release request by negating the bus right release acknowledge signal BACK can be invalidated. As a result, the microprocessor 1 performs the bus right release permission control information BREQE until the required processing involving the external bus access is completed.
By maintaining N in the active state, the bus right can be maintained regardless of the negation state of the bus right release acknowledge signal BACK from the master processor. Therefore, even in the slave mode, the microprocessor 1 can have a degree of freedom in acquiring and releasing the bus right by handshaking. Moreover, the register 21 in which the bus right release permission control information BREQEN is stored can be accessed and rewritten by the built-in CPU 3, and such a degree of freedom can be controlled by the operation program of the CPU 3.

In particular, in this example, the bus right release permission control information BREQEN is initialized in the register 21 according to whether the operation mode of the microprocessor 1 determined by the reset operation is the master mode or the slave mode. That is, when the master / slave mode control information MSMD set in the register 22 indicates the master mode in the reset operation, the bus right release permission control information BREQEN is initially set in the register 21 to the inactive state. Therefore, immediately after the reset, the microprocessor 1 in which the master mode is set, releases the bus right release permission control information BREQ.
Until EN is rewritten to the active state, a certain process involving bus access can be completed without releasing the bus right to the slave processor. Such a process is a general initialization operation for a shared resource or the like of a multiprocessor system, which will be described later in a specific example. The slave processor accesses the shared resource before the initialization operation is completed. This can easily prevent a malfunction from occurring.

In the reset operation, the master / slave mode control information MS set in the register 22 is set.
When the MD indicates the slave mode, the bus right release permission control information BREQEN is initially set in the register 21 to the active state. Therefore, the microprocessor 1, in which the slave mode is set, immediately acquires the bus right from the master processor immediately after the reset, and then releases the bus right to the master processor until the bus right release permission control information BREQEN is rewritten to the inactive state. A certain process involving a bus access can be completed without performing.

[Multiprocessor System] FIG. 2 is a block diagram of a multiprocessor system using two microprocessors shown in FIG. In FIG. 2, a master processor 1m is a microprocessor 1 in which a master mode is set, and a slave processor 1s is a microprocessor 1 in which a slave mode is set. In FIG. 2, reference numeral 40 denotes a mode signal MD.
m, MDs. MDm is a mode signal for setting the master mode in the master processor 1m, and MDs is a mode signal for setting the slave mode in the slave processor 1s. The mode signal generating circuit 40 is simply constituted by, for example, a pull-up circuit and a pull-down circuit. 21m and 22m correspond to the bus release permission control information BR in the master processor 1m.
The registers 21 and 22 in which EQEN and master / slave mode control information MSMD are set. 21s, 2
2s are registers 21 and 22 in which the bus right release permission control information BREQEN and master / slave mode control information MSMD are set in the slave processor 1s. 20m is the bus arbitration circuit 2 of the master processor 1m
0 and 20 s are bus arbitration circuits 2 of the slave processor 1 s
0. Bus arbitration circuit 20m of master processor 1m
Receives a bus right release request signal BREQ and outputs a bus right release acknowledge signal BACK. Slave processor 1s
The bus arbitration circuit 20s outputs the bus right release request signal BREQ and inputs the bus right release acknowledge signal BACK.

In FIG. 2, reference numeral 44 denotes a synchronous DRAM coupled to an address bus 33, a data bus 32, and a control bus (not shown) as a common bus. The synchronous DRAM 44 is used as a shared resource of the microprocessors 1m and 1s, and is, for example, a main memory used as a work area or a primary storage area for data.

In FIG. 2, reference numerals 42 and 43 denote a local address bus and a local data bus of the master processor 1m, to which a boot memory 41 is connected.
The boot memory 41 stores an initialization program for initializing the multiprocessor system shown in FIG. 2, and the initialization program includes the synchronous D
An initialization program for initially installing the RAM 44 is also included. For example, the synchronous DRAM 44 includes a mode register in which a burst length, a burst type, a CAS latency, and the like are set, and an initialization program of the boot memory 41 is an operation program for initializing such a mode register. If the memory cell of the synchronous DRAM 44 is accessed without performing the optimal initialization for the multiprocessor system of FIG. 2, a malfunction or a data error may occur.
Considering this, it is desirable that after the system reset, the slave processor 1s accesses the synchronous DRAM 44 after the master processor 1m completes the initialization operation.

FIG. 3 is a flowchart showing the operation of the master processor 1m immediately after the reset, and FIG. 4 is a flowchart showing the operation of the slave processor 1s immediately after the reset.

When the reset signal is input, the master processor 1m initializes the master / slave control information MSMD instructing the master mode in the register 21m according to the mode signal MDm, and sets the inactive bus right release permission control information in the register 21m. BREQEN is initialized in the register 22m (M1). As a result, the master mode is set in the master processor 1m, and the bus arbitration circuit 20m
Ignores the bus right release request by asserting the bus right release request signal BREQ until the bus right release permission control information BREQEN is rewritten to the active state. Thereafter, the master processor 1m accesses the boot memory 41 and performs initialization of the shared resources represented by the synchronous DRAM 44 (M2, M3).

On the other hand, when the reset signal is input, the slave processor 1s receives the master / slave control information MSMD instructing the slave mode in accordance with the mode signal MDs.
Is initialized in the register 21s, and the active bus right release permission control signal BREQEN is initialized in the register 22s (S1). As a result, the slave mode is set in the slave processor 1s, and the bus arbitration circuit 20s issues a bus right release request by negating the bus right release approval signal BREQ until the bus right release permission control information BREQEN is rewritten to an inactive state. ignore.
This state is effective when the slave processor 1s acquires the bus right. For example, after resetting, the slave processor 1s asserts the bus right release request signal BREQ to the master processor 1m to access the synchronous DRAM 44 (S2), and the master processor 1m
It waits until the bus right release acknowledge signal BACK is asserted (S3).

When the master processor 1m completes the initialization of the shared resource, the CPU of the master processor 1m rewrites the bus release permission control information BREQEN to an active state (M4). When detecting that the bus right release request signal BREQ from the slave processor 1s is asserted (M5), the master processor 1m asserts the bus right release acknowledge signal BACK to release the bus right.

As a result, the slave processor 1 s acquires the bus right by detecting the assertion of the bus right release acknowledge signal BACK in step S 3, and can access the synchronous DRAM 44. At this time, since the initialization of the synchronous DRAM 44 has already been completed, no malfunction occurs due to the access by the slave processor 1s.

At this time, since the bus right release permission control information BREQEN of the slave processor 1s is in the active state, the bus arbitration circuit 20s causes the bus right release acknowledge signal BACK until the CPU of the slave processor 1s inverts the information. Ignoring the bus right release request from the master processor 1m due to negation of the synchronous DRAM 4
4 can be continued.

FIG. 5 is a block diagram of a multiprocessor system using the microprocessor 1 of FIG. 1 as a master processor 1m and another microprocessor 50 as a slave processor. Microprocessor 50
Also has a bus arbitration circuit 51. This bus arbitration circuit 51
Is different from the bus arbitration circuit 20 in that it does not have a control function according to the bus right release permission control information BREQEN. The microprocessor 50 outputs a bus right release request signal B
By outputting REQ and inputting the bus right release acknowledge signal BACK, it operates as a slave processor.
Even in such a system configuration, the master processor 1m has a degree of freedom in acquiring and releasing the bus right as described above, so that the master processor 1m does not release the bus right to the slave processor 50 until the initialization of the synchronous DRAM is completed. I'm done.

FIG. 6 is a block diagram of a multiprocessor system using the microprocessor 1 of FIG. 1 as a slave processor 1s and another microprocessor 50 as a master processor. Microprocessor 5
0 also has a bus arbitration circuit 51. This bus arbitration circuit 5
1 differs from the bus arbitration circuit 20 in that it does not have a control function according to the bus right release permission control information BREQEN. The microprocessor 50 operates as a master processor by inputting the bus right release request signal BREQ and outputting a bus right release acknowledge signal BACK.
Even in such a system configuration, the slave processor 1s has a degree of freedom in acquiring and releasing the bus right, as described above, so that the slave processor 1s ignores the bus right release request from the master processor 50 for a certain period of time and involves the bus access. It is possible to obtain a degree of freedom in which a series of processes can be continuously executed. In the example of FIG. 6, DRs that do not require initialization are
The AM 52 is shown as an example of a shared resource.

FIG. 7 shows an example of a multiprocessor system using still another microprocessor.
The microprocessor 60 shown in the figure includes a CPU 61 for executing a fetched instruction on a semiconductor substrate, and the operation mode of the microprocessor is initially a master mode having a bus right or acquires a bus right as necessary. A register 62 in which master / slave mode control information MSMD for determining the slave mode is set, and a mode signal MD for initially determining the master / slave mode control information MSMD for the register 62 at the time of resetting operation It has a terminal and a bus arbitration circuit 63. The bus arbitration circuit 63 transmits the bus right release permission control information BR
It has a bus right request and release control function by handshaking, excluding the EQEN control function. Further, when the master / slave mode control information MSMD initially set in the register 62 indicates the master mode, the bus arbitration circuit 63 releases the bus right to the outside only once after reset according to the operation program of the CPU. A series of changes such as a high level, a low level, and a high level are caused in the acknowledge signal. When the master / slave mode control information MSMD initially set in the register 62 indicates the slave mode, the reset is performed. After that, it is possible to request the bus right by the bus right request signal BREQ only after detecting that the series of changes such as the high level, the low level, and the high level has occurred in the bus right acknowledge signal BACK from the outside. It has a function called. The microprocessor 60 (master processor) in which the master mode is set,
Until the initialization of a shared resource such as the synchronous DRAM 44 requiring initialization is completed, the degree of freedom that the bus right is not released to the microprocessor 60 (slave processor) in which the slave mode is set can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, bus right release permission control information BREQ
The registers 21 and 22 storing the EN and the master / slave mode control information MSMD are not limited to being built in the bus controller, and may be arranged anywhere in the microprocessor. In the above embodiment, the mode signal and the reset signal are directly input to the bus controller to initialize the registers 21 and 22. However, these signals are supplied to the mode control logic of the microprocessor, where the signals are supplied. It is also possible to initialize the registers 21 and 22 by the generated internal control signal. Further, the built-in function modules of the microprocessor and the connection arrangement are not limited to the example of FIG. 1 and can be changed as appropriate. The degree of freedom for acquiring and releasing the bus right in the microprocessor can be obtained in both the master mode and the slave mode in the microprocessor 1 of FIG. 1, but only in one of the master mode and the slave mode. It is also possible to configure the bus arbitration circuit so as to obtain it. Further, the number of microprocessors included in the multiprocessor system is not limited to two, and may be three or more. Also, as a slave that can acquire the bus right, DMAC (Direct Memory Acce
It is of course possible to connect an ss Controller) to the common bus. If there are multiple slaves, for example,
By utilizing an external circuit for bus arbitration between slaves, a bus release request signal and a bus release acknowledgment signal are exchanged with the master processor. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a condition having a function of requesting and releasing a bus right in a handshake.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the microprocessor can have a degree of freedom in acquiring and releasing the bus right by handshaking. In particular, such a degree of freedom can be controlled by an operation program of a CPU having a built-in microprocessor.

When the microprocessor is responsible for the initialization of the external peripheral circuit, it can ignore the external bus request until the initialization is completed.

A multiprocessor system to which the above-mentioned microprocessor is applied can eliminate the possibility that the shared resource which is required to be initialized is arbitrarily accessed before the initialization is completed, thereby causing a malfunction. It is not necessary to configure a special external circuit on the above or to complicate the processing by software.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microprocessor according to an example of the present invention.

FIG. 2 is a block diagram of a multiprocessor system using two microprocessors shown in FIG.

3 is an example operation flowchart of a master processor immediately after reset in the multiprocessor system of FIG. 2;

4 is an example operation flowchart of a slave processor immediately after reset in the multiprocessor system of FIG. 2;

5 is a block diagram of a multiprocessor system using the microprocessor of FIG. 1 as a master processor and another microprocessor as a slave processor.

FIG. 6 is a block diagram of a multiprocessor system using the microprocessor of FIG. 1 as a slave processor and another microprocessor as a master processor.

FIG. 7 is a block diagram showing an example of a multiprocessor system using a microprocessor different from that of FIG. 1;

[Explanation of symbols]

 Reference Signs List 1 microprocessor 3 CPU 9 bus controller 20 bus arbitration circuit 21 register BREQEN bus right release permission control information 22 register MSMD master / slave mode control information RESET reset signal MD mode signal BREQ bus right release request signal BACK bus right release approval signal 40 mode Signal generation circuit 41 Boot memory 44 Synchronous DRAM

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Norio Nakagawa 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd.

Claims (10)

[Claims] 1. A microprocessor including a CPU for executing a fetched instruction on a semiconductor substrate, wherein an operation mode of the microprocessor is initially a master mode having a bus right or acquiring a bus right as necessary. First storage means in which master / slave mode control information for determining the slave mode is set; second storage means in which bus right release permission control information is initialized to be rewritable by the CPU; In a state where the master mode is set by the master / slave mode control information, when the bus right release permission control information set in the second storage means is in an inactive state, the bus right release permission control information is in an active state. Bus arbitration means for invalidating a bus right release request by asserting a bus right release request signal from outside until inverted. A microprocessor comprising: a microprocessor; 2. The first storage means has master / slave mode control information initialized in response to a reset operation of a microprocessor, and the second storage means has a master / slave mode control information.
2. The microprocessor according to claim 1, wherein the inactive bus right release permission control information is initialized in response to the setting of the master mode by the slave control information. 3. A microprocessor including a CPU for executing a fetched instruction on a semiconductor substrate, wherein the operation mode of the microprocessor is a master mode having an initial bus right or a bus right is acquired as necessary. First storage means in which master / slave mode control information for determining the slave mode is set; second storage means in which bus right release permission control information is initialized to be rewritable by the CPU; In a state where the slave mode is set by the master / slave mode control information, when the bus right release permission control information set in the second storage means is in an active state, the bus right release permission control information is in an inactive state. Bus arbitration means for invalidating a bus right release request from negating an external bus right release acknowledge signal until inverted. A microprocessor, comprising: a microprocessor; 4. The first storage means has master / slave mode control information initialized in response to a reset operation of a microprocessor, and the second storage means has master / slave mode control information.
3. The microprocessor according to claim 2, wherein the active bus right release permission control information is initialized in response to the setting of the slave mode by the slave control information. 5. A microprocessor including a CPU for executing a fetched instruction on a semiconductor substrate, wherein an operation mode of the microprocessor is initially a master mode having a bus right or acquiring a bus right as necessary. First storage means in which master / slave mode control information for determining the slave mode is set; second storage means in which bus right release permission control information is initialized to be rewritable by the CPU; When the bus right release permission control information set in the second storage means is in an inactive state in a state where the master mode is set by the master / slave mode control information, the bus right release permission control information is inverted to an active state. Until the bus release request signal is asserted by the external device until the bus release request signal is asserted. When the bus right release permission control information set in the second storage means is in the active state in a state where the slave mode is set by the slave mode control information, the bus right release permission control information is inverted to the inactive state. A bus arbitration means for invalidating a bus right release request by negating an external bus right release approval signal. 6. The first storage means initializes master / slave mode control information according to a mode signal in response to a reset operation of a microprocessor, and the second storage means stores a master mode based on master / slave control information. The inactive bus right release permission control information is initialized in response to the setting of (1), and the active bus right release permission control information is initialized in response to the setting of the slave mode by the master / slave control information. The microprocessor according to claim 5, wherein 7. A plurality of microprocessors according to claim 6, a bus commonly connected to the microprocessors, a peripheral circuit connected to the bus and requiring an initialization operation, and the plurality of microprocessors. A mode signal generating means for setting a master mode for any one of the processors and setting a slave mode for the remaining microprocessors, and a microprocessor for setting the master mode to initialize the peripheral circuits A memory for storing an operation program executed by the
A multiprocessor system characterized by comprising: 8. A microprocessor including a CPU for executing a fetched instruction on a semiconductor substrate, wherein the operation mode of the microprocessor is initially a master mode having a bus right or acquiring a bus right as necessary. First storage means in which master / slave mode control information for determining whether the mode is the slave mode is set, and master / slave mode control information to be set in the first storage means is initially determined during a reset operation. A mode terminal for, and when the master / slave mode control information initially set in the first storage means indicates the master mode, the bus right release permission control information is initially set to an inactive state and set. Second storage means in which the bus right release permission control information can be rewritten by the CPU, and a bus right release request signal from an external device in the master mode. Inputs a bus release approval signal to the outside and outputs a bus release approval signal to the outside. In the slave mode, outputs a bus release request signal to the outside and inputs an external bus release approval signal. Bus arbitration means for invalidating a bus right release request by asserting the bus right release request signal from outside when the right release permission control information is in an inactive state. Microprocessor characterized. 9. A microprocessor including a CPU for executing a fetched instruction on a semiconductor substrate, wherein the operation mode of the microprocessor is initially a master mode having a bus right or acquiring a bus right as necessary. First storage means in which master / slave mode control information for determining whether the mode is the slave mode is set, and master / slave mode control information to be set in the first storage means is initially determined during a reset operation. A mode terminal for setting the bus right release permission control information to an active state when the master / slave mode control information initially set in the first storage means indicates a slave mode; A second storage unit whose right release permission control information can be rewritten by the CPU, and a bus right release request signal from an external device in the master mode. The bus right release acknowledge signal is output to the outside and the bus right release acknowledge signal is output to the outside.In the slave mode, an external bus right release acknowledge signal is input and the bus right release request signal is output to the outside. Bus arbitration means for maintaining the currently acquired bus right regardless of whether the bus right release approval signal is negated from the outside when the bus right release permission control information is active. A microprocessor. 10. A plurality of microprocessors according to claim 6, a bus commonly connected to the microprocessors, a peripheral circuit connected to the bus and requiring an initialization operation, and the plurality of microprocessors. Are reset in parallel, a mode signal generating means for setting a master mode to any one of the microprocessors and setting a slave mode to the remaining microprocessors, and the master for initializing the peripheral circuits. A memory for storing an operation program to be executed by a microprocessor in which a mode is set, the multiprocessor system comprising: