JPS61251943A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the overhead accompanied with inputs/outputs of a large quantity of data by providing an operation processor with an interface control circuit to make it possible that data is inputted to and outputted from a memory which is in the course of operation. CONSTITUTION:When a host processor CPU 1 accesses a data memory 4, the memory 4 is connected to the side of a numerical operation processing unit 6 by an interface control circuit 5. When the CPU 1 and the unit 6 access the memory 4 simultaneously, the memory 4 is connected to a CPU bus 2 by the control of the circuit 5, and the unit 6 is set to the temporary stop state, and the unit 6 is released from the temporary stop state and is connected to the memory 4 when the access of the CPU 1 is completed. By this operation, the memory 4 is shared between the CPU 1 and the unit 6, and address mapping is possible to transfer data between an external device and an operation numerical processor 3, thus reducing the overhead accompanied with inputs/outputs of a large quantity of data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improving the processing power of a data processing device having a numerical processor.

(Prior art) In a CPU system with a numerical calculation processor,
The numerical calculation processor is generally treated as an input/output device ffi'('f/○ device) from the CPU's perspective, and data for performing calculations is sent to this processor, the calculation is started, and the calculation process is completed. It is normal to write a message and return the data.

(Problems to be solved by the invention) However, in such a conventional CPU system,
Data cannot be input or output until the calculation on the processor is completed, and if the calculation results are to be stored in another device, such as a disk, the data must be transferred to the CPU memory via DMA.
(Direct memory access) transfer and then further DMA transfer to the disk to store data, which poses a problem in that data transfer takes time.

SUMMARY OF THE INVENTION An object of the present invention is to solve these problems, and to provide a data processing device having a processing ability that allows data to be input/output to a memory even while a numerical arithmetic processor is performing calculations.

<Means for solving the problem> In order to achieve such an objective, the present invention provides a host
a processor, a numerical arithmetic processor having data memory, and a data processor that controls sharing of the data memory between the host processor and the numerical arithmetic processor;
It is equipped with a memory control means so that data can be input and output from the host processor to the data memory even while the numerical arithmetic processor is performing calculations.

<Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing device according to the present invention. In the figure, 1 is the host processor (
(hereinafter abbreviated as CPU) communicates with the numerical arithmetic processor 3 via the CPU bus 2.

It is configured to allow data and control signals to be exchanged. The numerical arithmetic processor 3 has a data memory 4. Data memory control means5. It is composed of a numerical calculation processing unit 6.

The data memory control means 5 controls the data memory 4 to
It consists of an interface circuit 51 for connecting to U1 or a numerical arithmetic processing unit, and an interface control circuit 52 for controlling this interface circuit.

The interface circuit 51 is a type of changeover switch and is dynamically controlled by the interface control circuit 52. That is, when there is a memory access request, switching is performed immediately, and when requests from CPU 1 and numerical arithmetic processing unit 6 overlap, selection switching is performed according to the priority order set in advance by interface control circuit 52. In the embodiment, CPUI requests are given a high priority.

The operation in such a configuration will be explained next.

When the CPU 1 accesses the data memory 4, the interface control circuit 5 causes the data memory 4 to
Connected to U bus 2. When the numerical arithmetic processing unit 6 accesses the data memory 4, the data memory 4 is connected to the numerical arithmetic processing unit side by the interface control circuit 5.

If the data memory 4 is accessed by the CPtJl and the numerical arithmetic processing unit 6 at the same time, the data memory 4 is accessed by the CPU under the control of the interface control circuit 5.
It is connected to the bus 2, and the numerical arithmetic processing unit is temporarily stopped and on standby. When the access by the CPU 1 is completed, the suspension state of the numerical arithmetic processing unit is released, and the data memory is connected to the numerical arithmetic processing unit.

Through this operation, the data memory 4 can be shared between the CPU 1 and the numerical calculation processing unit 6, and address mapping is also possible, so data can be transferred between an external device such as a disk and the numerical calculation processor, and large amounts of data can be input. Over l-bed with output is reduced.

FIG. 2 is a block diagram showing another embodiment of the present invention, in which the data memory 4 in the numerical arithmetic processor is divided into two parts of 41° and 42°, and the interface circuit 5 is also divided into 51a and 51b.
This configuration is designed to reduce the frequency of simultaneous memory access.

(Effects of the Invention) As described above, according to the present invention, by providing the arithmetic processor with an interface control circuit, the processing capacity is improved as follows. That is, data can be input/output to/from the data memory even while the numerical processor is performing calculations. Therefore, preparation for the next operation can be made in advance, and the remaining memory portion not used for the operation can be used as CPIJ memory.

Furthermore, address mapping enables data transfer between an external device such as a disk and a numerical arithmetic processor, thereby reducing overhead associated with input/output of large amounts of data.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a data processing device according to the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. 1...Host processor 2...・CPU bus 3... Numerical calculation processor 4... Data memory 5... Data memory control means 6... Numerical calculation processing unit

Claims (1)

[Claims] It consists of a host processor and a numerical arithmetic processor capable of transmitting and receiving signals via a bus, and this numerical arithmetic processor has a data memory, a numerical arithmetic processing unit, and the data memory is connected to the bus or the numerical arithmetic processing unit. Data comprising: an interface circuit that connects selectively; and an interface control circuit that controls the interface circuit to switch data memory connections in response to memory access requests from a host processor and a numerical arithmetic processing unit. Processing equipment.