JPS616754A - Direct memory access transfer system - Google Patents

Abstract

PURPOSE:To attain DMA transfer without reducing the using efficiency of a processor by separating buses at the time of DMA transfer. CONSTITUTION:When a DMA request is outputted from an I/O apparatus 5 to a DMA control circuit 2, the circuit 2 makes the outputs of bus buffers floating status. Namely, an address bus 11b, a data bus 12b and control buses 13b, 14b are separated from an address bus 11a, a data bus 12a and control buses 13a, 14a. Therefore, the right of possession of the address bus 11a, the data bus 12a and the control buses 13a, 14a is assigned to a microprocessor 1, but that of the address bus 11b, the data bus 12b and the control buses 13b, 14b is transferred to the DMA control circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a direct memory access transfer method in a microcomputer system or the like.

[Prior art]

When input/output is controlled by a program in a microcomputer system having a microprocessor as the control center, several instruction cycles are required for the processing, so 20 to 100 Is are required.

Therefore, when high-speed input/output is required, a direct memory access (hereinafter referred to as DM8) transfer method is used. In this method, the DMA control circuit transfers data between input/output devices, between memories, or between input/output devices and memory, and high-speed transfer is possible, but in the conventional method, the microprocessor Since the data transfer is in an open/stop state, there is a drawback that the efficiency of microprocessor usage is low.

The conventional frame transfer method will be briefly explained below with reference to the drawings.

FIG. 3 is a block diagram of the conventional I) MA transfer method, in which the microprocessor 1 includes a program memory 3 that stores programs for controlling its operation, a memory 4 that stores data to be transferred by DMA, and an open memory 4 that stores data to be transferred. The input/output device 5, DMA control circuit 2, etc. to be transferred to are connected via an address bus 21, a data bus 22, and control buses 23 and 24. The direct memory control circuit 2, the microprocessor 1, and the input/output device 5 are connected through a control line.

FIG. 4 is a time chart showing the procedure of the DMA transfer method in the above-mentioned circuit.

At all times, the microprocessor 1 has exclusive rights to the address bus 21 □ data bus 22 and control buses 23 and 24, and uses these to read program data from the program memory 3 and control the input/output devices 5. or memory 4
continues, and write control is executed according to the program.

Then, as shown in FIG. 4(a), from the input/output device 5 to the DM
When the A request is issued to the DMA control circuit 2, that is, the signal DR
When Q = "1", the control circuit A receives this and outputs a bus release request signal +IRQ = "1" to the microprocessor 1 as shown in FIG. 4(b). When the microprocessor l receives this, it sets the address bus 21, data bus 22, and control buses 23, 24 to a high impedance floating state at a convenient time for its operation, and at the same time sets these buses to a floating state. Signal that reports HLDA = “1”
[FIG. 4(C)] is issued to the DMA control circuit 2. As a result, the microprocessor 1 "stops" its operation and gives possession of the bus to the DMA control circuit 2, as shown in FIG. 4+d).

In response to this, the DMA control circuit 2 outputs the address 1 of the memory 4 to be DMA transferred to the address bus 22 [FIG. 4(r)), and then outputs a signal for specifying the input/output device 5 from which the data should be read. Set DACK to 0'' [Figure 4 (e)
].

Next, the DMA frlJ control circuit 2 sets the signal 110R instructing to read data from the input/output device 5 to "θ".
In FIG. 4 (hl), data to be read from the input/output device 5 is transferred to the control bus 23 and transferred to the data bus 21 (fourth
Next, the 1MA control circuit sets the signal pre-i instructing data writing to the memory 4 to "0".
), on the control bus 24, and causes the above data to be written into the memory 4. In this way, the DMA control circuit 2 sequentially outputs the address, T10R, and plane.
After the transfer of the required data is completed, the input/output device 5 listens to the signal DR (1 as “0”) and the control circuit 2
to notify the end of DMA transfer. In response to this, the DMA control circuit 2 sets the signal IRQ to θ'', sets the address bus 21, data bus 22, and control buses 23 and 24 to a floating state, and transfers the exclusive right to the lotus to the microprocessor 1.Microprocessor 1 In response to this, the signal ①LDA is set to "O" to return to normal operation from the stopped state.

As is clear from the above detailed description, in the case of the conventional DMA transfer method, the microprocessor's bus is occupied by the DMA control circuit during transfer, and its operation is stopped, resulting in a decrease in usage efficiency.

〔the purpose〕

The present invention has been made in view of such circumstances, and
It is an object of the present invention to provide a DMA transfer method that can perform DM^ transfer without deteriorating processor usage efficiency by separating buses during MA transfer.

〔composition〕

The transfer method according to the present invention includes an address bus, a data bus, and a control bus that connect a processor and a program memory that stores a program for controlling its operation, a direct memory access control circuit, and a direct memory access control circuit. An address bus, a data bus, and a control bus that connect the access transfer memory or the direct memory access transfer input/output circuit are coupled via a bus buffer, and during direct memory access transfer, the processor side is [Embodiment] Hereinafter, the present invention will be described as an embodiment thereof. This will be explained in detail based on the drawings.

FIG. 1 is a block diagram showing the implementation state of the method of the present invention, and FIG.
The figure is a time chart for explaining the operation.

In the figure, l is a microprocessor which is the control center of the microcomputer system, and includes address buses lla and lib, and data buses 12a and 12b.

DMA control circuit 2, program memory 3, memory 4,
It is connected to input/output equipment 5.6. address bus ll
One end of the control bus 13a, 14a of the data bus 1281 is directly connected to the output port of the microprocessor I, and unrelated to the program memory 3 storing the program for controlling the operation of the microprocessor and the DFI eight. The input/output devices 6 are connected to these buses lla and 12a.

13a and 14a.

The other end of the address bus lla is connected to the address bus llb via the bus buffer 7, the other end of the data bus 12a is connected to the data bus 12b via the hash buffer 78, and the control bus 1
3a and 14a are connected to control buses 13b and 14b via bus buffers 9 and 10, respectively.

Surrounded by these buses llb, 12b, 13b, and 14b that are not directly connected to the microprocessor 1 are a control circuit 2, a memory 4, and an input/output device 5, as well as I) others that are not shown and are subject to M/1 transfer. input/output devices and memory will be connected. Other DMA control circuit 2
is connected to the hash buffers 7.8 and 9.10 for their control, and is also connected to the input/output device 5.6 via a control line.

The DMA transfer method of the present invention is carried out in the following procedure in a system having the above configuration. That is, the DMA control circuit 2 normally sets the signal HQR (FIG. 2(b)) to the bus buffer 7, 8, 9, and 10 to "0" to enable data transfer between the busses. In this case, the microprocessor has exclusive rights to all the buses, and the microprocessor sends or receives required data to the memory and input/output devices connected to each bus according to the program.

Now, as shown in Figure 2 (al), the input/output devices 5 and DMA
When a request is sent to the control circuit 2, that is, the signal oR
When q- becomes "1", the frame control circuit 2 receives this and sets the signal IRQ to "1" [FIG. 2(b)].

This signal differs from the conventional bus buffer 7, 8゜9.1
0 to the output control terminal, and as a result, the output of each hash buffer becomes a floating state. In other words, the address bus 11b and the data bus 12b.

The control buses 13b and 14b are separated from the atrus bus Ila, the data bus 12a, and the control buses 13a and 14a.

Therefore, while the microprocessor 1 has the exclusive rights to the address bus 11a, the data bus 12a, and the control buses 13a and 14a as before, the exclusive right to the address bus 11b, the data bus 12b, and the control buses 13b and 14b is held by the DMA.
Transferring to the control circuit 2 [Fig. 2 tc+, (d13°), the DMA control circuit 2 outputs the memory address for DMA transfer to the address bus 11-b [Fig. 2 (
Then, the DMA control circuit 2 sets the signal plane to "O" [FIG. 2(e)], and also sets the signal I10 to "O".
Set R to "0" [Fig. 2 (h)] and give it to the input/output device 5, and put the data on the data bus 12b [second
Figure (g)].

Further, the signal MEMW is set to 0'' to cause the data on the second (il) data bus 12b to be written into the memory 4.

Similarly, the DMA transfer address and signal 110R
and MEMW to perform n data transfers.

During this time, while the DMA transfer is being performed, the microprocessor 1 uses the address bus 11a, data bus 12a, and control buses 13a and 14a to read instructions from the program memory 3 and to read instructions from the input/output device 6 unrelated to the DMA transfer. Control etc. can be performed in parallel with the open transfer operation.

And D? 'lA control circuit 2 gives signal TC indicating the end of DM^ transfer to input/output device 6, and microprocessor 1
reads this and detects its completion. Upon completion of the DMA transfer, the address bus 11 is set to IRQ (signal) as “0”.
a, flb, data buses 12a, 12b, control buses 23a, 13b, and control buses 14a, 14b. As a result, ownership of all these buses is transferred to the microprocessor I.

In addition, when performing DMA transfer from the memory 4 to the input/output device 5, the signal plane ``■'' instructing to read the memory is placed on the control bus 14b, and the signal l10-, instructing to give it to the input/output device 5, is controlled. The data can be transferred to the bus 13b. Transfer to other memory-to-memory locations is also possible. The present invention is applicable not only to microcomputer systems but also to larger computer systems.

〔effect〕

In the case of the present invention as described above, while DMΔ transfer is executed between high-speed input/output devices and memories or between memories, the microprocessor performs DM transfer in parallel without stopping.
Processing and control other than A transfer can be executed.

In other words, DMA transfer is possible without reducing the usage efficiency of the microprocessor. Further, the present invention has excellent effects such as enabling DMA transfer even in a microprocessor that cannot set the address bus, data bus, and control bus in a floating state, that is, does not have a stop function.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the implementation state of the method of the present invention, and FIG.
The figure is a time chart for explaining its operation, FIG. 3 is a block diagram of the conventional system, and FIG. 4 is a time chart for explaining its operation.

Claims (1)

[Claims] 1. An address bus, a data bus, and a control bus that connect a processor and a program memory that stores a program for controlling its operation, a direct memory access control circuit, and a direct memory access control circuit. An address bus, a data bus, and a control bus that connect the transfer memory or direct memory access transfer input/output circuit are coupled via a bus buffer, and during direct memory access transfer, the address on the processor side is transferred by the bus buffer. bus, data bus, control bus and direct memory bus
A direct memory access transfer method characterized by separating an address bus, a data bus, and a control bus on the access control circuit side.