JPH01240960A - Dma transfer control circuit - Google Patents

Abstract

PURPOSE:To perform data transfer between peripheral devices without deteriorating the performance of a microprocessor bus by generating the address of a main memory circuit by an address counter when data of the data width of the microprocessor bus is held at a data buffer, and writing it in a main memory. CONSTITUTION:In a processing for reading out the data from the peripheral device 6 by a DMA transfer request from a peripheral LSI 5, the data read out from the peripheral device 6 is held at the data buffer 10 via the peripheral LSI 5 and a peripheral LSI control circuit 12. When the data of the data width is held at the data buffer 10, the address of the main memory circuit 2 is generated by the address counter 8, and the data in the data buffer 10 is written in the main memory circuit 2 via a bus control circuit 7. At the time of accessing the peripheral LSI 5 by a microprocessor 1, the read/write of control data is performed via a control data buffer 11. In such a way, the data transfer can be performed without deteriorating the performance of the microprocessor bus.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a DMA transfer control circuit, and more particularly to a DMA transfer control circuit whose transfer data width of a microprocessor is larger than that of a peripheral device control LSf.

Prior Art In a conventional DMA transfer control circuit, peripheral device control L
The SI was connected to the microprocessor bus and transferred data to the main memory circuit with a data width smaller than that of the microprocessor bus.

Problems to be Solved by the Invention As described above, the conventional DMA transfer control circuit has the disadvantage that it degrades the performance of the microprocessor bus when transferring data from the peripheral device control LSI to the main memory circuit.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel MA transfer control circuit which makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, a DMA transfer control circuit according to the present invention includes a microprocessor bus control circuit that controls a microprocessor bus, and a main memory circuit address for DMA transfer. An address counter to generate, a data counter to count the number of data transfers, a data buffer that temporarily holds data for data transfer and converts the data width between the Mitaro processor bus and the peripheral control LSI, and one-periphery cylinder control. 1. It has a control data buffer that temporarily holds control data of S1, and a peripheral device 4 control LSI control circuit that controls the peripheral device control LSI. When the Mitaro processor accesses the peripheral device control LSI, it reads and writes control data via the control data buffer. When reading data from the peripheral device due to a DMA transfer request from the peripheral device control LSI, the peripheral device control LSI
The data is held in the data buffer via the SI control circuit, and when the data is held in the data buffer for the data width of the microprocessor bus, an address for the main memory circuit is generated by the address counter, and the data is stored in the data buffer via the microprocessor bus control circuit. and writes the data in the data buffer to the main memory.

Embodiment Next, two preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of an information processing system including a DMA transfer control circuit according to the present invention.

Referring to FIG. 1, a DMA transfer control circuit 4 according to the present invention includes a microprocessor bus control circuit 7 (hereinafter abbreviated as a bus control circuit) that controls a microprocessor bus 3 (hereinafter abbreviated as a bus). , an address counter 8 that generates the address of the main memory circuit 2 for DMA transfer.
, a data counter 9 that counts the number of data transfers by one, and data that temporarily holds data for data transfer and converts the data width between the bus 3 and the peripheral device control LSI 5 (hereinafter abbreviated as peripheral LSI). Buffer 10 and 1 peripheral LS
Control data buffer 1 that temporarily holds control data of I5
1 and a peripheral device control LSI control circuit 12 (hereinafter abbreviated as peripheral LSI control circuit). The microprocessor 1, main memory circuit 2, and DMA transfer control circuit 4 are interconnected via a bus 3.

The peripheral device 6 is connected to the DMA transfer control circuit 4 via one peripheral LSI 5. Normally, the data width of the first peripheral LSI 5 is smaller than that of the lotus 3, so by connecting the peripheral SI 5 to the lotus 3, the data width from the first peripheral LSI 5 is connected to the main memory circuit 2 via the bus 3. If this data transfer is performed, the performance of the bus 3 will be degraded.

In the process of reading data from the peripheral device 6 in response to a DMA transfer request from the peripheral LSI 5, data read from one peripheral device 6 is held in the data buffer 10 via the peripheral SI 5 and the peripheral LSI control circuit 12. When this data is held in the data buffer 10 by the data width of the bus 3, the address counter 8 generates an address for the main memory circuit 2, and the data in the data buffer 10 is transferred to the main memory circuit 2 via the bus control circuit 7. write to.

When the microprocessor 1 accesses the peripheral LSI 5, it reads and writes control data via the control data buffer 11.

DETAILED DESCRIPTION OF THE INVENTION As described above, the DMA transfer control circuit of the present invention minimizes the increase in heart rate and does not degrade the performance of the microprocessor bus.

It is possible to transfer data to and from peripheral devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing system including a DMA transfer control circuit according to the present invention. 100. Microprocessor, 209. Main memory circuit, 3
00. Microprocessor bus, 4. ,. IJMA transfer control circuit, 5310 peripheral device control L control,
6゜90 Peripheral equipment, 701. Microprocessor bus control circuit, 806. Address counter, 90. . data counter, io, , data buffer, 11
．． . , control data buffer, 12. , , peripheral device control L
SI control circuit

Claims (1)

[Claims] In an information processing system including a microprocessor, a main memory circuit, a microprocessor bus, a DMA transfer control circuit, a peripheral device control LSI, and a peripheral device, the microprocessor, the main memory circuit, and the DMA transfer control circuit connect to the microprocessor bus. The DMA transfer control circuit is connected to a microprocessor bus control circuit that controls the microprocessor bus, and a DMA transfer control circuit that controls the microprocessor bus.
an address counter that generates an address in the main memory circuit for transfer, a data counter that counts the number of data transfers, and a data counter that temporarily holds data for data transfer between the microprocessor bus and the peripheral device control LSI. The microprocessor includes a data buffer that performs width conversion, a control data buffer that temporarily holds control data for the peripheral device control LSI, and a peripheral device control LSI control circuit that controls the peripheral device control LSI. When accessing the peripheral device control LSI, read and write control data via the control data buffer,
When reading data from the peripheral device in response to a DMA transfer request from the peripheral device control LSI, the data is held in the data buffer via the peripheral device control LSI control circuit, and the data is read by the data width of the microprocessor bus. The address counter generates an address for the main memory circuit when the data is held in the data buffer, and the data in the data buffer is written to the main memory device via the microprocessor bus control circuit. DMA transfer control circuit.