JPH0334043A - Information processor including master and slave devices connected to each other via system bus - Google Patents

Abstract

PURPOSE:To ensure the free transfer of data between a device which handles data in the ascending order and a device which handles data in the descending order with the effective use of the width of a system bus by adding a circuit to a master device to output the ascending/descending order signal and adding an ascending/descending order signal line to the system bus. CONSTITUTION:A CPU 600 contains a bus control unit which drives an ascending/descending order signal line 40 at a high level during the use of a system bus 500 and then gives an access to the data in the ascending order. A CPU 700 contains a bus control unit which drives the line 40 at a low level during the use of the bus 500 and then gives an access to the data in the descending order. The bus 500 contains the line 40, and a memory device 800 contains a conversion circuit for arrangement of data as well as a bus control unit. In such a constitution, the mutual accesses of data are always secured between a device which handles data in the ascending order and a device which handles data in the descending order with the effective use of the width of the system bus.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the configuration of an information processing device, and particularly to a system having a means for interfacing a device that handles data in ascending order and a device that handles data in descending order in a mixed manner. The present invention relates to a new configuration of an information processing device that includes a master device, a slave device, and a system bus that transfer data between the devices via a bus.

Conventional technology First, data is arranged in "ascending order" and "descending order"
The meaning of each of the upper 8 bits of the 16-bit internal data bus is written into the even memory 410.

As explained above, when a device that handles data in ascending order and a device that handles data in descending order write the same internal data using 16-bit access as shown in FIG. There are differences in whether bits are written to even memory or odd memory, and whether the upper 8 bits of internal data are written to odd memory or even memory.

Therefore, for example, when the CPU 300 reads data written into the memory device 400 by word access by the CPU 200 by word access, the upper 8 bits and lower 8 bits of the data are swapped.

Note that when the CPUs 200 and 300 perform byte access, only the lower 8 bits of the internal data are always exchanged with the memory at the specified address. Therefore,
For example, if internal data as shown in FIG. 5(d) is
When U200 writes to an even address using byte access, it is stored as shown in FIG. 5(e), and the CP
The internal data similarly written by U300 is shown in Figure 5 (f
), and both are stored in even number memory 4.
10.

Similarly, the internal data as shown in FIG. 5(d) is
If U200 writes to an even address using byte access, it will be stored as shown in Figure 5.
The internal data similarly written by U300 is shown in Figure 5 (h).
Both are stored in the odd memory 42 as shown in FIG.
Stored at 0.

That is, in byte access, there is no difference between a device that handles data in ascending order and a device that handles data in descending order.

Problems to be Solved by the Invention As described above, in conventional information processing devices, when a CPU device that handles data in ascending order and a CPU device that handles data in descending order have a shared memory, ascending order data and descending order data are Because the meaning of the data is different, it is necessary to access the shared memory in short units that are not affected by the difference in the length of the data, whether it is ascending or descending data. Therefore, when designing a program that accesses shared memory, ascending/
Programs must be created taking care to access shared memory in units of data width that are not affected by descending order. Furthermore, since such an access method uses only a portion of the data bus, data transfer efficiency is significantly lower than when data is transferred using the entire data bus.

Therefore, the present invention solves the above-mentioned problems of the prior art, and provides a novel information processing system in which a device that handles data in ascending order and a device that handles data in descending order coexist and can efficiently transfer data to each other. Its purpose is to provide the configuration of the device.

Means for Solving the Problem, that is, according to the present invention, when processing data via a system bus, the system uses an ascending order/descending order signal to distinguish whether the data related to the processing is arranged in ascending order or descending order. A master device that is equipped with a circuit that outputs to the bus and has the right to use the system bus, and a data sequence that is the sequence of data indicated by the ascending/descending signals output by the master device when the master device requests data transfer. A slave device is provided with an ascending order/descending order data conversion circuit that outputs data in ascending order and does not have the right to use the system bus, and a system bus that includes an ascending order/descending order signal line for transmitting the ascending order/descending order signal. and a device that handles data in descending order, the master device and the slave device are optionally connected to the system bus to mutually transfer data. An information processing device is provided that includes a master device and a slave device connected by a system bus.

Nira J The information processing device according to the present invention includes a circuit that outputs a signal indicating that the data handled by the master device is in ascending order or descending order, while the slave device handles the data in ascending order or descending order as instructed via the system bus. Its main feature is that it is equipped with a circuit for converting output data.

That is, in the information processing according to the present invention, a device that handles data in ascending order and a device that handles data in descending order are always able to mutually access data by effectively using the bus width of the system bus.

Hereinafter, the information processing device according to the present invention will be explained in more detail with reference to the drawings, but the disclosure below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way. .

Embodiment 1 FIG. 1(a) is a block diagram showing a configuration example of an information processing apparatus according to the present invention.

As shown in the figure, this information processing device includes a CPU device 6
00 and 700, a memory device 800, and a system bus 500 that interconnects them.

Here, the CPU 600 is equipped with a bus control unit D610 (shown in FIG. On the other hand, the CPU 700 is equipped with a drive-through bus control unit (E710) (shown in Figure 11 (C)) which keeps the ascending/descending signal line 40 low while the system bus is in use, and outputs data in descending order. Access with . Further, the system bus 500 includes a data bus 10 and a near address bus 2.
0, a control/response signal bus 30, a bus access arbitration line 50, and an ascending/descending signal line 40. Furthermore, the memory device 800 includes a hash control unit F810 (see t in FIG. 1(d)) and a circuit for converting the data arrangement.

FIG. 1(b) is a block diagram showing an example of the configuration of the CPU unit W600 in the information processing apparatus shown in FIG. 1(a). As shown in FIG. 4, this CPU device also has a CPU device 210 (FIG.
b) Similarly, the bus control unit) D6
10 controls the buffers/drivers 61 to 63 according to the logic of the logic table shown in FIG. A signal indicating this is output to the ascending/descending signal line 40.

FIG. 1(C) is a block diagram showing a configuration example of the CPU device 700 in the information processing apparatus shown in FIG. 1(a). Similarly to the CPU 600, this CPU device 700 also uses the CPU device 310 in the conventional information processing device.
(See FIG. 4(C)), the bus control unit E710 controls the buffers/drivers 64 to 66 according to the logic of the logic table shown in FIG.
When the CPU device 700 becomes a master device and accesses data via the system bus, it outputs a signal indicating that data will be accessed in descending order to the ascending order/descending order signal line 40.

FIG. 1(d) is a block diagram showing a configuration example of the memory device 800 in the information processing apparatus shown in FIG. 1(a).

As shown in the figure, in this memory device 800,
The bus control unit F810 includes the memory device 80
When 0 is accessed, the buffers/drivers 67-70 are operated according to the logic as shown in the logic table of FIG. 6(d). That is, memory device 800 memory % 'J R min 4
10 Oyohi 420 is a bus control unit)F
810, the data is always written in ascending order, and when read, the bus control unit F810 outputs the data in the order indicated by the ascending/descending signal line 40.
It is a shared memory that can be accessed in 15 bits from any of the following.

FIG. 2 is a timing chart for explaining the operation when the CPU device accesses the memory via the system bus 500 in the information processing device configured as described above.

In FIG. 2, ADO~23 and both ears are signals indicating that the address and upper 8 bits output by the master device to the memory device are valid.

AE is a signal indicating that ADO~23 and 100HE are valid. ○RDER is a signal indicating whether the data is arranged in ascending order or descending order. The tile D (W″D) is a signal indicating read access or write access, and DO~7 and D8~15 indicate the lower 8 bits and upper 8 bits of data, respectively.X and π are signals from the memory device. This is the response signal.

Hereinafter, while following the transition of the above-mentioned signals, the CPU device 70
0 writes data to the memory 800 using 16-bit access, and further, the operation when the CPU device 600 reads the data using word access will be described.

First, after confirming that the bus access arbitration line 50 of the system bus 500 is low, the CPU device 700 drives the bus access arbitration line 50 to high and becomes the bus master. Next, the CPU device 700 sends a signal indicating address and word write access from the bus control unit 710 to the address bus 20, control/response signal line 30, and ascending/descending signal line 40 of the system bus 500. A signal indicating that it is data is output. Next, the signal on the signal line 81 in the CPU device 700 is outputted to the data bus 12 of the upper 8 bits, and the signal on the signal line 82 is outputted to the data bus 11 of the lower 8 bits.

The accessed memory device 800 is connected to the address bus 20
, recognizes that 16-bit descending data is to be written according to the contents indicated by the control/response signal line 30 and the ascending order/descending order signal line 40, and transfers the data on the data bus 10 to the address indicated by the address bus 20. write to memory. Here, since the bus control unit 710 and buffer/drivers 69 and 70 of the memory device 800 are opened, the data that was on the signal line 81 was stored in the even numbered memory U 410, and the data was stored on the signal line 82 of the odd numbered memory 420. Data is written respectively. In other words, even number notes! J4
10 and odd number memory 420 are written in the form of ascending order data.

Next, the operation when the CPU device 600 reads data at the same address in the memory device 800 will be described.

Here, bus control unit 710 of memory device 800 opens buffer/drivers 67 and 68 so that data in even memory 410 and odd memory 420 can be read in ascending order data. Therefore, the contents of the even memory 410 are 81 in the CPU device 600.
Then, the contents of the odd memory 420 are respectively read into 82 in the CPU device 600, and the CPU device 600 successfully reads the data that the CPtJ device 700 wrote to the memory device 800 by word access.

Next, as another example of the operation of this information processing device, an operation will be described in which the CPU device 600 writes data to the memory device 800 using word access, and the CPU device 700 reads the data using word access.

Even number memory 41 of the address output by the CPU device 600
When writing data to the 0 and odd memory 420,
It opens buffers/drivers 67 and 68, so the CPU
81 data in the device 600 are stored in the even memory 410, 8
2 data are respectively written into the odd number memory 420 in the form of ascending order data.

When the CPU device 700 reads data on the same address, the bus control unit (F810) of the memory device 800 opens the buffer/drivers 69 and 70, so that the ascending order data becomes descending order data and is transferred to the data bus of the system bus 500. 10 is output. Therefore, the data on the even memory 410 is written to 81 in the CPU device 700, the data on the odd memory 420 is written to 82 in the CPU device 700, and the CPU device 600 writes to the memory device 800 by word access. The CPU device 700 can normally read 16-bit data.

Embodiment 2 FIG. 3 is a block diagram showing another configuration example of the information processing apparatus according to the present invention.

As shown in the figure, this information processing device includes a pair of CPU devices 10 connected to each other via a system bus 900.
00 and 1100, and a memory device 1200.

Here, the system bus 900 of this information processing device is the system bus 500 of the information processing device of the first embodiment.
The RDER signal line 40 is connected to the ascending signal line 41 and the descending signal line 4.
2 and a pair of signal lines. Correspondingly, the CPU device tooo that handles data in ascending order is equipped with a circuit that drives the ascending order signal line 41 low while the system bus is in use.

Further, the CPU device 1100 that handles data in descending order includes a circuit that drives the descending order signal line 42 to low while the system bus is in use. Furthermore, the memory device 1200 is
A circuit is provided that returns an error to the master device if both the ascending signal line 41 and the descending signal line 42 are low or high when accessed.

In the information processing device configured as described above, by assigning dedicated signal lines to the ascending order signal and the descending order signal, respectively, when the slave device is accessed from the master device, the ascending order signal line 41 and the descending order signal line 42 are both low
Alternatively, in the case of the old gh, the slave device side can recognize that this access is not normal.

As described in detail about the invention, in the information processing device according to the present invention, the master device is provided with a circuit for outputting ascending order/descending order signals, and the system bus is provided with ascending order/descending signal lines. A device that handles data in ascending order and a device that handles data in descending order differ in the shared memory access method, and a device that handles data in ascending order and a device that handles data in descending order exchange data.The arrangement of data handled by each device is ascending order. This can be done by effectively utilizing the bus width of the system bus without being restricted by the difference in whether the order is in descending order or in descending order.

Therefore, when designing a program that accesses a shared memory, it is possible to design a program without paying attention to the unit of data width for accessing the shared memory, as in the past.

In addition, since it is possible to transfer data by effectively utilizing the bus width of the system bus, unlike conventional technology, which can only use a portion of the data bus width, the data transfer time becomes longer. There is also the effect that there is no

[Brief explanation of drawings]

FIG. 1(a) is a block diagram showing a configuration example of an information processing apparatus according to the present invention, and FIG. 1(b) is a block diagram showing a data processing apparatus used in the information processing apparatus shown in FIG. FIG. 1C is a block diagram showing the configuration of a device that accesses data in ascending order, and FIG.
FIG. 1(d) is a block diagram showing a configuration example of a common memory device that can be used in the information processing device shown in FIG. 1(a); FIG. FIG. 3 is a timing chart for explaining the operation of the information processing device shown in the figure; FIG. 3 is a block diagram showing another configuration example of the information processing device according to the present invention; FIG. , is a block diagram showing an example of a device connected to a system bus that handles data in ascending order in a conventional information processing device. FIG. 4C is a block diagram showing an example of a device that handles data in descending order; FIG. 4C is a block diagram showing an example of a memory device connected to a system bus in a conventional information processing device; FIG. (d) is a block diagram showing a configuration example of a conventional information processing device configured using each of the devices shown in FIGS. 4(a) to (C), and FIGS. 5(a) to 0-1. ) is a diagram showing data handled in ascending order or descending order in the conventional information processing apparatus shown in FIGS. 4(a) to (d); FIGS. 6(a), ('b), and (C) and (d) is a logic table showing the logic that defines the operation of each path control unit. [Main reference numbers and reference symbols] 10...Data bus, 11...Data bus from DO to D7, 12...Data bus from D8 to D15, 20...Address bus, 30...Control signal bus, 40... 41... Ascending signal line, 42, 50... Bus access arbitration line, 61-72... Driver/buffer, 81... Lower 8 bits of internal data bus, 82... Upper 8 bits of internal data bus, - Ascending order /Descending signal line, - Descending signal line, 91...Address generation unit, 92...Execution unit, 93...Instruction decoder unit, 94...Register unit, 100...System bus, 400.800.1200...Memory Device, 410...
Even number memo 'J, 420...odd number memory, 430...address decoder, 500...system bus with ascending/descending signal lines, 90
0...system bus,

Claims (1)

[Scope of Claims] A circuit that outputs an ascending order/descending order signal to the system bus to distinguish whether the data related to the processing is arranged in ascending order or descending order when processing data via the system bus, A master device that has the right to use the system bus, and an ascending/descending data conversion that outputs data in the order of data indicated by the ascending/descending signals output by the master device when the master device requests data transfer. A slave device that is equipped with a circuit and does not have the right to use the system bus, and a system bus that includes an ascending order/descending order signal line for transmitting the ascending order/descending order signal, and a device that handles data in ascending order and a device that handles data in descending order. A master device connected by a system bus, characterized in that the master device and the slave device, including a device that handles and information processing equipment including slave devices.