JPS6111873A - Accessing method to 8-bit and 16-bit peripheral devices by 16-bit microprocessor - Google Patents

Abstract

PURPOSE:To use a memory or an I/O in a 8-bit group as it is regarding an 8-bit peripheral device as a peripheral device provided with the data width of 16 bits when the 8-bit peripheral device is observed from a 16-bit MPU. CONSTITUTION:An address control part 11 sends 2n obtained by doubling address information (n) to an address information line 21. An R/W control part 5 reads out information in address 2n of an 8-bit peripheral device 13 on an 8-bit data bus 22 and controls a command line 16 to latch the read-out information in an 8-bit latch 8. The command control part 5 sends an R signl to a command line 19, reads out information in address (2n+1) of the 8-bit peripheral device 13 on the 8-bit data bus 22, turns a two-way buffer 9 from the 8-bit peripheral device 13 to the MPU4 through a command line 17, and transmits the information on the bus 22 to a bus 2. Then, the control part 5 releases the waiting state of the MPU4 to input the data of the latch 8 and the information on the bus 22 to the MPU4.

Description

Detailed Description of the Invention (Technical Field to which the Invention Pertains) The present invention relates to a microprocessor having a 16-bit data bus (hereinafter abbreviated as 16-bit MPU) and a 16-bit and 8-bit memory and input device controlled by the microprocessor (hereinafter abbreviated as 16-bit MPU). This relates to a method of accessing a memory or input/output device having different bits from a 16-bit MPU in an information processing device equipped with an output device (Ilo).

(Prior art) Conventionally, a 16-bit MPU has been used to process peripheral devices such as memory and Ilo (hereinafter referred to as 8-bit data bit width) by a 16-bit MPU.
When accessing the bit periphery), connect the 8-bit memory 24 or the 8-bit I10 to the lower 8-bit data bus of the 16-bit data bus included in the 16-bit MPU 4, as shown in Figure 2. It was only accessible through ,■. Therefore, access commands (
(hereinafter referred to as word instruction),
An instruction (hereinafter referred to as a byte instruction) that is accessed through only one word was issued twice to replace one word instruction.

For this reason, the instruction execution time is long and it is impossible to use commercially available programs that use word access instructions as they are.

Furthermore, it is impossible to perform the program fetch operation in word units, which is a condition required of the memory to store a 16-bit MPU program, by using two byte access instructions as described above. , the data bit width must be 16 bits. Therefore, the memory for MPU (8 pino) can be used as is\16 bit MPU
could not be used for. In addition, ■ and 2 in the figure
4 and 25 will be explained below.

The conventional access operation will now be supplemented by the more detailed conventional component diagram of FIG. The symbols in Figure 3 are the same as in Figure 2, but ■ is the lower 8-bit data bus, ■ is the upper 8-bit data bus, and 3 is the Read/Write.
(Read/Write, abbreviated as R/W) signal line, 4 is 16
Bit MPU, 5 is address decode/command control unit, 6 is address information line, 24 (Figure 2) is 8 bit memory, 25 (Figure 2) is 8 bit memory, 10.13 is 8 bit peripheral, 12 is 16 bit Peripheral, 26 is 8-bit peripheral 13
27 represents the R/W command signal for the 16-bit peripheral 12. In this configuration, the 16-bit MPU4 has 12 16-bit peripherals.
When accessing, specify the address using the address information line 6, specify R/W using the command line 27, and access in 16-bit units through both the lower and upper 8-bit data buses ■ and ■. . Next, when accessing the 8-bit periphery 13, the address is first specified in the same manner as described above, R/W is specified using the command line 26, and the access is made only through the lower 8-bit data bus (2). Therefore, it is necessary for the program to always recognize the allocated addresses around 16 bits and around 8 bits, and it is necessary to issue only byte instructions for around 8 bits.

(Specific Object of the Invention) The present invention is intended to eliminate the drawback that commercially available programs using word access instructions and peripheral device circuits made for 8-bin MPUs cannot be used in 16-bin MPUs. 16 for an 8-bit peripheral device.
7) When viewed from the MPU, it appears as a peripheral device with a 16-bit data width.

(Configuration of the Invention) FIG. 1 is a side view of a circuit configuration in which a 16-bit MPU accesses 16-bit b and 8-bit peripheral devices when the present invention is implemented. First, we will explain the names and functions of each part.

■ and ■ are data bus lines, each 16 piso) MFU
It is connected to the lower 8 bits and upper 8 bits of the 16-bit data bit terminals provided in the 16-bit data bit terminal.

3 is 16 bis) Read and Write generated when the MPU accesses external memory or peripheral devices
e signal (R/W) signal line.

4 is an MPU equipped with a 16-bit data bit terminal
.

5 decodes the address information sent from the MPU 4 (usually the upper few bits of the address information) and selects the corresponding 1.
MPU4 for 6-bit or 8-bit memory or Ilo
A control unit that controls transmission of the R/W command signal from the
It is called the command control section.

Reference numeral 6 denotes an address information line which specifies an address to be accessed when the MPU 4 accesses an external memory or peripheral device.

Reference numeral 7 denotes a bidirectional buffer, which transmits and receives data between the lower 8-bit data terminal of the MPU 4 and the 8-bit peripheral 13.

8 is an 8-bit latch that holds the data read from the 8-bit peripheral 13 and supplies it to the lower 8-bit data terminal of the MPU 4.

Reference numeral 9 denotes a bidirectional buffer, which transmits and receives data between the upper 8-bit data terminal of the MPU 4 and the B-bit peripheral 13.

10 is an 8-bit latch that holds data output from the upper 8-bit data terminal of the MPU 4 and supplies this to the 8-bit peripheral 13.

11 is an address control unit which receives address information (n address) sent from the MPU 4 through the address information line 6 and converts it to 2n.
It has the function of converting the address into two consecutive addresses, ie, the address and the next (2n+1) address, and providing it to the 8-bit peripheral 13.

12 and 13 are 1 each for memory and peripheral devices.
It has 6-bit and 8-bit data buses.

14 is an R/W signal line which is used by the command control unit 5 to access 12 as a result of analyzing 3 and 6 from the MPU 4.

15 is M when MPU 4 accesses 8-bit peripheral 13
A command signal line that controls the output and direction of the bidirectional buffer 7 placed between the lower 8-bit data terminal of the PU and 13.

16 is a command signal line that causes the 8-bit latch 8 to latch read data when the MPU 4 performs a read operation on the 13;

17 is M when MPU 4 accesses 8-bit peripheral 13
A command signal line that controls the output and direction of the bidirectional buffer 9 between the upper 8-bit data terminal of the PU and 13.

Reference numeral 18 denotes a command signal line for launching data to be written into the 8-bit 2 bits 10 when the MPU 4 performs a write operation on the 8-bit peripheral 13.

Reference numeral 19 is an R/W signal line, and the command control unit 5 sends a signal to access the 8-bit peripheral 13 as a result of analyzing 3 and 6 sent from the MPU.

20 converts address information n sent from MPU 4 to address control unit 11 through 6 and outputs it to 21;
An address signal line that determines whether to output n or (2n+1.).

21 is a 7-dress information line for 7-dressing (addressing) the 8-bit peripheral 13;

In FIG. 1, when a command (command) is issued from the 16-bit MPU 4 via the command line 3, the R/W control unit 5 analyzes this command, and if it is a command for the 16-bit peripheral 12, the command from the MPU is sent via the command line 3. 14, and the address information is conveyed directly to \1616 bit 12 by address line 6. In addition, if the command is for the 8-bit peripheral 13, the command line 19 accesses the 13, and at the same time the address control unit 11
The address information from the MPU is converted and transmitted to the 8-bit peripheral 13 via the address line 21. Furthermore, command lines 15,,16.

17 and 18 control the bidirectional buffer 7.9 and the latch 8.10 to connect the 8-bit bus 22 and the 16-bit buses ① and ②. These operations will be described in detail below, but it will be understood that in order to make it possible to use the 8-bit periphery, it is necessary to add each of the sections 5, 7 to 11, signal lines, and buses in the figure.

(Operation of the invention) Access to peripheral devices by a 16-bit MPU requires a Read operation to receive information from the peripheral device and a Write operation to transfer information to the peripheral device.
(write) operation. The operation of both according to the present invention will now be described.

(1) Read operation (abbreviated as R operation) a) From the MPU 4 as shown in FIG. 1 When a Read operation occurs, the R/W control unit 5 decodes the address information 6, and the R operation
If it is for the 6-bit peripheral 12, the control signal sent via the signal line 3 is directly applied to the 16-bit peripheral 12 via the command line 14, and at the same time, 7 to 10 bidirectional buffers and latches are inactive. accesses around 16 bits. The above part is nothing more than a normal access method to the 16-bit peripheral 12 by the 16-bit MPU.

b) As a result of decoding the address information n from the address information line 6 (the address for specifying the address when accessing the peripheral device) in the R/W control unit 5, it is determined that the R operation is for the 8-bit peripheral 13 and the word In the case of access, this is notified to the address control unit 11 through the command line 20, and at the same time, the MPU 4 is activated through the signal line 23.
af' to state.

C) The address control unit 11 doubles the address information n from the address information line 6 and sends 2n to the address information line 21 as address information for the 8-bit periphery 13.

d) The R/W control unit 5 sends an R signal to the 8th periphery 13 via the command line 19 (the information at address 2n in 13 is sent to the 8th
Read on bit data bus 22 and also command 1IJ
16 to latch the read information in latch 8, and at the same time stop outputting the R signal.

e") Next, in step K c), 1 is added to the address information output to the address information line 21 (2n+
1) Send the address to 21.

f) Send the R signal from the command control unit 5 to the command line 19 again, read out the information at address (2n+'l) of the 8-bit peripheral 13 onto the 8-bit data bus 22, and read out the information at address (2n+'l) of the 8-bit peripheral 13 onto the 8-bit data bus 22, and also read out the information from the address (2n+'l) of the 8-bit periphery 13 to the bidirectional buffer via the command line 17. 9 around 8 bits 13
In the direction from the MPU to the MPU, information on the bus 22 is transmitted onto the bus line ■.

g) After the operations from b) to f) are completed, a signal is sent from the command control unit 5 through the signal line 23, and the W of the MPU 4 is
Release the state of a i. Then, the information on the bus, that is, the information at address 2n of the 8-bit peripheral 13, and the bus ■
MP the above information, that is, the information at address 13 (2n+1)
UK is imported, and the read (R) operation in 16-bit units is completed. 7 and 10 are held in the non-operating state during the period from ) to g).

(2) Write operation (abbreviated as W operation) For the operations a) to C), the R operation in a) to C) of the R operation may be rewritten as a W operation.

d) The command control unit 5 controls the bidirectional buffer 77 through the command line 15 to transmit the write (W) information for the 8-bit peripheral 13 output from the MPU 4 onto the bus 2 onto the 8-bit data bus 22, and at the same time The command line 18 is controlled to latch the W information outputted onto the bus 1 to the latch 10. However, the latched data is only latched to 10, but the latched data is not output onto the bus 22. The reason for this is that the data on the bus 2 is passed through the bidirectional buffer 7 to the bus 22.
This is because if the data latched in the 8-bit latch 10 is output onto the bus 22 while the data is being output on the bus 22, the forces 7 and 10 will collide. Also, the difference between the above two W information is that the MPU has 13 KWordWrite around 8 bits.
(batch writing of 16-bit data), the W information output on the bus ■ is the lower 8 bits of the 16 pits, and the W information output on the bus ■ is the upper eight bits.
It means that it is broken with bits.

e) Next, output the W signal from the command control unit 5 to the signal line 19, and write the information on the bus 22 transmitted through the bidirectional buffer 7 to address 2n of the 8-bit peripheral 13.

f) When the writing to address 2n is completed, stop outputting the W signal, make the bidirectional buffer 7 inactive, and add 1 to the address information on the address information line 21 to write (2n+1).
) address on line 21.

g) Next, output the data latched in the 8-bit latch 10 onto the bus 22, output the W signal whose output was once stopped again to the 8-bit peripheral 13, and transfer the information on the bus 22 to 13 (2n+1'). Write to address.

h) When the above operations are completed, Wa i to MPU4
t is canceled to complete the W operation in 16-bit units.

During the operations from (a) to h), the 8-bit latch 8 and bidirectional buffer 9 are kept inactive.

The above is an explanation of the word access method for a peripheral device by a 16-bit MPU when the method of the present invention is implemented. However, since the MPU (16 bits) also has an instruction to access a peripheral device in units of 4 hbytes, the present invention also You can use this command. This is why 7 and 9 in FIG. 1 are made bidirectional buffers. M
The R/W operation when the PU 4 issues an instruction to access the 8-bit peripheral 13 in units of bytes is as follows.

(3) R operation a) When reading data to the lower 8-bit data terminal of the MPU 4, the data read onto the bus 22 is transferred to the bidirectional buffer 7 by controlling the command line 15.
Send it on the bus through.

b) When reading data to the upper 4-bit data terminal of the MPU 4, the data read onto the bus 22 is sent onto the bus 2 via the bidirectional buffer 9 by controlling the command line 17.

(4) W operation a) When writing the data output to the lower 8-bit data terminal of the MPU 4, the data output on the bus ■ is transferred onto the bus 22 through the bidirectional buffer 7 by controlling the command line 15. send.

b) When writing the data output to the upper 8-bit data terminal of the MPU 4, the data output on the bus 2 is sent onto the bus 22 through the bidirectional buffer 9 by controlling the command line 17.

(Effects of the Invention) (1) The present invention can be applied to personal computers, word processors, etc.16. If you apply it to equipment in a field where commercially available programs for Pitt CPUs are available (add the necessary circuits), you can use commercially available programs as is even if you use 8-bit memory, I10 devices, etc.

(2) The cost of 16-bit memory, I10 devices, etc. is higher than that of 8-bit memory. If high-speed access is required, it is connected to the 16-bit buses (1) and (2) shown in FIG. 1, and those that require low-speed access are connected to the 8-bit bus 22.A reasonable device can be obtained at a low cost.

As mentioned above, there is a tendency for KMPU application products to shift from 8-bit systems to 16-bit systems, but by applying the present invention, already developed 8-bit system memory and Ilo can be used as they are by 16-bit system MPUs. Being able to do this is a significant effect.

[Brief explanation of drawings]

FIG. 1 is an example of a circuit configuration showing a method of accessing 8-bit and 16-bit peripheral devices by a 16-bit MPU embodying the present invention, and FIGS. 2 and 3 are examples of circuit configurations of conventional access terminals. . ■...lower 8-bit data bus, ■...upper 8-bit data bus, 3...R/W signal line, 4...
16-bit MPU, s...R/W control section, 6.
...address information line, 7...lower 8 bit data bidirectional buffer, 8...lower 8 bits), Rea
d data latch, 9... Upper 8-bit data bidirectional buffer, 10... Upper 8-bit write data latch, 11... Address control section, 12... 16-bit peripheral device, 13... 8-bit peripheral Apparatus, 14-2
0...Control command line 1.21...Address information'[
L22...8-bit data bus, 23...Wa i
the signal line.

Claims (1)

[Claims] Byte and word instructions provided by a 16-bit microprocessor (MPU) are compatible with 16-bit peripherals and 8
In addition to the upper 8-bit data bus, lower 8-bit data bus, read/write signal line, and address information line of the 16-bit MPU, the read/write command control unit and A plurality of command lines that transmit the output, a wait signal line for the MPU, an address control section and address information line, a bidirectional buffer for each of the lower 8-bit data and upper 8-bit data, and a read data latch for the lower 8 bits. An additional circuit equipped with a write data latch for the upper 8 bits and an 8-bit data bus is provided, and a 16-bit MPU
The address control unit converts the address n specified by the MPU into addresses 2n and 2n+1 of the 8-bit peripheral device, and determines whether the instruction issued by the MPU is for a 16-bit peripheral device or an 8-bit peripheral device. If the control signal is for a 16-bit peripheral device, the control signal from the MPU is directly transmitted to the 16-bit peripheral device, and if it is for an 8-bit peripheral device, it is decoded and recognized by the command control unit. 16 characterized in that the address control unit accesses two consecutive addresses 2n and 2n+1 to the 8-bit peripheral device.
A method for accessing 8-bit and 16-bit peripheral devices by a bit microprocessor.