JP2976443B2 - Information processing device that exchanges data via system bus - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a configuration of an information processing apparatus, and in particular, to a system having a means capable of interfacing a device that handles data in ascending order and a device that handles data in descending order. The present invention relates to a novel configuration of an information processing device including a master device, a slave device, and a system bus that transfer data between the devices via a bus.

2. Description of the Related Art First, the meaning of "ascending order" and "descending order" of data arrangement will be described by taking a central processing unit (hereinafter, referred to as a CPU) having a 16-bit internal data bus and an external data bus as examples. explain.

FIG. 4A is a block diagram showing a configuration of a CPU 200 connected to the system bus 100 and handling data in ascending order. FIG. 4B is a block diagram showing the configuration of the CPU 300 connected to the system bus 100 and handling data in descending order.

Here, each of the CPUs 200 and 300 includes an execution unit 9 for executing an instruction.
2. An instruction decoding unit 93 for decoding instructions, an address generation unit 91 for generating an address, a registration unit 94, a lower 8 bits 81 and an upper 8 bits 82 of an internal data bus, and a bus for controlling exchange of data with the outside. -It shall consist of the control unit 210 and the buffers / drivers 61, 62, 63.

FIG. 4C is a block diagram showing a configuration of the memory device 400 connected to the system bus 100. The memory device 400 includes an even memory unit 410 and an odd memory unit.
420, a bus control unit 440 for controlling external access, and an address decoder unit 430.
And buffers / drivers 71, 72 and the like.

FIG. 4D shows that the CPUs 200 and 300 are connected to the system bus 1.
FIG. 14 is a block diagram in the case of configuring a system in which a memory device 400 is shared via 00.

Here, in the CPU 200, as shown in FIG.
The bus control unit A210 controls the buffers / drivers 61 to 63 using G1, G2, G3 and Gin / out. That is, in 16-bit access (hereinafter, 16-bit access is referred to as word access), the buffer /
Opening the drivers 61 and 62 connects the lower 8 bits 81 of the internal data bus of the device to the data bus 11 and the upper 8 bits 82 of the internal data bus to the data bus 12. The bus control unit A210 operates according to the logic shown in the logic table shown in FIG. In 8-bit access (hereinafter, 8-bit access is referred to as byte access), when the address is an even number, the buffer / driver 61 is opened and the lower 8 bits 81 of the internal data bus are set to the data bus D0 to D7 of the system bus. When the address is odd, the buffer / driver 63 is opened and the lower 8 bits 81 of the internal data bus are transferred to the data bus 1 of the system bus D8 to D15.
Works to connect to 2. The direction of data is controlled by a Gin / out signal line.

In the CPU 300, as shown in FIG. 4B, the bus control unit B310 includes a buffer / driver.
Control 64-66 using G4, G5, G6 and Gin / out.
Here, the bus control unit B310 operates according to a logic such as a logic table shown in FIG. 6 (b). That is, in word access, the buffer / driver 64 and
By opening 65, the lower 8 bits 81 of the internal data bus of the device are connected to the data bus 12 and the upper 8 bits 82
Is connected to the data bus 11. In the byte access, when the address is even, the buffer / driver 66 is opened and the lower 8 bits 81 of the internal data bus are set to the D0 of the system bus.
When the address is odd, the buffer / driver 64 is opened to connect the lower 8 bits 81 of the internal data bus to the data bus 12 of D8 to D15 of the system bus. The direction of data is controlled by Gin / out signal lines.

In the memory device 400, as shown in FIG. 4C, the bus controller unit C440
Buffers / drivers 71 and 7 using 1, G12, Gin / out
By controlling 2, it functions to connect the buses even memory 410 and odd memory 420 to the data buses 11 and 12, respectively. Where the bus controller unit
The C440 operates according to the logic of the logic table shown in FIG. The direction of data is controlled by Gin / out signal lines.

Here, the internal data as shown in FIG.
If U200 writes to memory by word access, the fifth
As shown in FIG. 7B, the lower 8 bits of the internal data are written to the even memory 410 and the upper 8 bits of the internal data are written to the odd memory 420.

When the CPU 300 writes data into the memory by word access, the lower 8 bits of the internal data are written into the odd memory 420 and the upper 8 bits of the internal data are written into the even memory 410 as shown in FIG. 5C.

As described above, between the device that handles ascending data and the device that handles data in descending order, when the same internal data as shown in FIG.
There is a difference between writing the lower 8 bits of the internal data to the even memory or the odd memory, and writing the upper 8 bits of the internal data to the odd memory or the even memory. Therefore, for example, the CPU 200 may access the memory device 400 by word access.
When the CPU 300 reads the data written in the data by word access, the upper 8 bits and the lower 8 bits of the data are interchanged.

When the CPUs 200 and 300 perform byte access, only the lower 8 bits of the internal data exchange data with the memory at the designated address. Therefore, for example, when the CPU 200 writes the internal data as shown in FIG. 5 (d) to an even address by byte access, it is stored as shown in FIG. 5 (e), and the CPU 300 similarly writes the data. The internal data is stored as shown in FIG. 5 (f), and both are stored in the even memory 410.

Similarly, the internal data as shown in FIG.
If U200 writes to an even address by byte access,
The internal data similarly written by the CPU 300 is stored as shown in FIG. 5G, and both are stored in the odd memory 420 as shown in FIG. 5H.

That is, in byte access, there is no difference between a device that handles data in ascending order and a device that handles data in descending order.

Problems to be Solved by the Invention As described above, in the conventional information processing apparatus, when a CPU device that handles data in ascending order and a CPU device that handles data in descending order have a shared memory, ascending data and descending data are Therefore, it is necessary to access the shared memory in a short unit which is not affected by the difference between the data length of ascending data and descending data because the meaning of the data is different. Therefore, when designing a program that accesses the shared memory, the program must be created with care taken to access the shared memory in units of data width that are not affected by ascending / descending order. Further, since such an access method uses only a part of the data bus, the data transfer efficiency is significantly reduced as compared with the case where data is transferred using the entire data bus.

Therefore, the present invention solves the above-mentioned problems of the prior art,
It is an object of the present invention to provide a configuration of a novel information processing apparatus in which a device that handles data in ascending order and a device that handles data in descending order are mixed, and the data can be efficiently transferred to each other.

Means for Solving the Problems According to the present invention, when data is processed via a system bus, an ascending / descending signal for discriminating whether an arrangement of data related to the processing is ascending or descending. A master device having a circuit for outputting to the bus and having a right to use the system bus; and a data sequence comprising data indicated by ascending / descending order signals output by the master device when the master device requests data transfer. Output in ascending order /
A device that includes a descending data conversion circuit and does not have the right to use the system bus, and a device that includes a system bus including an ascending / descending signal line for transmitting the ascending / descending signal and handles data in ascending order; The master device and the slave device including a device that handles data in descending order are arbitrarily connected to the system bus, so that data can be mutually transferred. Provided is an information processing device including a master device and a slave device.

The information processing device according to the present invention includes a circuit that outputs a signal indicating that data handled by the master device is in ascending or descending order, while the slave device is in ascending or descending order instructed via the system bus. And a circuit for converting the output data.

That is, in the information processing according to the present invention, a device that handles data in ascending order and a device that handles data in descending order can always mutually access data by effectively using the bus width of the system bus.

Hereinafter, the information processing apparatus according to the present invention will be described more specifically with reference to the drawings. However, the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention. .

Embodiment 1 FIG. 1A is a block diagram showing a configuration example of an information processing apparatus according to the present invention.

As shown in FIG.
And 700, a memory device 800, and a system bus 500 interconnecting them.

Here, the CPU 600 uses the system bus in ascending order /
A bus control unit D610 (shown in FIG. 1 (b)) that drives the descending signal line 40 to high is provided, and is configured to access data in ascending order. On the other hand, CP
The U700 uses ascending / descending signal lines 40 while using the system bus.
Bus control unit E710 to drive low
(Shown in FIG. 1 (c)) to access data in descending order. The system bus 500 includes an ascending / descending signal line 40 in addition to the data bus 10: the address bus 20, the control / response signal bus 30, and the bus access arbitration line 50. Further, the memory device 800 includes a bus control unit F
810 (shown in FIG. 1 (d)) and a circuit for converting the arrangement of data.

FIG. 1B is a block diagram showing a configuration example of the CPU device 600 in the information processing device shown in FIG. 1A.
As shown in the figure, in this CPU device, similarly to the CPU device 210 (see FIG. 4 (b)) in the conventional information processing device, the bus control unit D610 uses the logic shown in FIG. 6 (a). Buffer / driver according to table logic
When the CPU device 600 becomes the master device and accesses data via the system bus, the CPU device 600 outputs to the ascending / descending signal line 40 a signal indicating that data is accessed in ascending order.

FIG. 1C is a block diagram showing a configuration example of the CPU 700 in the information processing apparatus shown in FIG. 1A.
In this CPU device 700, similarly to the CPU 600, similarly to the CPU device 310 (see FIG. 4 (c)) in the conventional information processing device, the bus control unit E710 is provided with a logical table shown in FIG. 6 (b). In accordance with the logic, the buffer / drivers 64 to 66 are controlled, and when the CPU device 700 becomes a master device and accesses data via the system bus, a signal indicating that data is to be accessed in descending order is sent to the ascending / descending signal line 40. Output to

FIG. 1D is a block diagram showing a configuration example of the memory device 800 in the information processing device shown in FIG. 1A.

As shown in the figure, in this memory device 800,
When the memory device 800 is accessed, the bus control unit F810 operates the buffers / drivers 67 to 70 according to the ethics shown in the logic table of FIG. 6D. That is, the memory portions 410 and 420 of the memory device 800 always write data in ascending order by the operation of the bus control unit F810, and when the data is read, output the data in the order of data indicated by the ascending / descending signal line 40 by the bus control unit F810. By doing so, the CPU device 600 and
It is a shared memory that can be accessed with 15 bits from any of the 700s.

FIG. 2 is a timing chart for explaining the operation when the CPU device accesses the memory via the system bus 500 in the information processing apparatus configured as described above.

In FIG. 2, AD0 to 23 and AD0 to 23 are signals indicating that the address output by the master device to the memory device and the upper bits are valid. Is a signal indicating that AD0 to AD23 are valid. ORDER is a signal indicating whether the data is arranged in ascending order or descending order. () Is a signal indicating read access or write access, and D 0-7 and D 8-15 are the lower 8 bits of data.
Bits and upper 8 bits, respectively. Is a response signal from the memory device.

Hereinafter, while following the above signal transition, the CPU 700
However, an operation in which data is written to the memory 800 by 16-bit access, and the data is read by the CPU device 600 by word access will be described.

First, after the CPU device 700 confirms that the bus access arbitration line 50 of the system bus 500 is low, the CPU device 700 drives the bus access arbitration line 50 high to become a bus master. Next, the CPU device 700 is connected to the address bus 2 of the system bus 500.
0, the bus control unit 710 outputs a signal indicating address and word write access and a signal indicating descending data to the control / response signal line 30 and the ascending / descending signal line 40. Next, the signal on the signal line 81 in the CPU device 700 is output to the upper 8-bit data bus 12, and the signal on the signal line 82 is output to the lower 8-bit data bus 11.

The accessed memory device 800 has the address bus 20,
Recognizing that 16-bit descending data is about to be written in accordance with the contents indicated by the control / response signal line 30 and the ascending / descending signal line 40, the data on the data bus 10 is stored in the memory at the address indicated by the address bus 20. Write to. here,
Since the bus control unit F810 of the memory device 800 opens the buffers / drivers 69 and 70, the even memory 41
Data that was on the signal line 81 is written to 0, and data that was on the signal line 82 is written to the odd memory 420.
That is, data is written in the even memory 410 and the odd memory 420 in the form of ascending data.

Next, an operation when the CPU device 600 reads data on the same address of the memory device 800 will be described.

Here, since the bus control unit F810 of the memory device 800 opens the buffers / drivers 67 and 68,
The data of the even memory 410 and the odd memory 420 can be read in the form of ascending data. Therefore, even memory
The content of 410 is read into 81 in the CPU device 600, and the content of the odd memory 420 is read into 82 in the CPU device 600, and the data written by the CPU device 700 by word access to the memory device 800 is written into the CPU device 600. Has been read successfully.

Next, as another operation example of the information processing apparatus, an operation in a case where the CPU device 600 writes data to the memory device 800 by word access and the CPU device 700 reads the data by word access will be described.

When writing data to the even-numbered memory 410 and the odd-numbered memory 420 at the address output by the CPU device 600, the buffers / drivers 67 and 68 are opened, so that 81 data in the CPU device 600 is stored in the even-numbered memory 410 and 82 data in the CPU device 600. Odd memory 420
Are written in the form of ascending data.

If the CPU device 700 reads data at the same address, the bus control unit F810 of the memory device 800
However, since the buffers / drivers 69 and 70 are opened, the ascending data is output to the data bus 10 of the system bus 500 as the descending data. Therefore, the data on the even memory 410 is written to 81 in the CPU 700, and the data on the odd memory 420 is written to 82 in the CPU 700.
The CPU device 700 can normally read the 16-bit data written in the memory device 800 by word access in 00.

Embodiment 2 FIG. 3 is a block diagram showing another configuration example of the information processing apparatus according to the present invention.

As shown in the figure, the information processing apparatus includes a pair of CPU devices 1000 and 1100 interconnected via a system bus 900, and a memory device 1200.

Here, the system bus 900 of the information processing apparatus is an ORDER of the system bus 500 in the information processing apparatus of the first embodiment.
The signal line 40 is configured by a pair of signal lines of an ascending signal line 41 and a descending signal line 42. Corresponding to this, the CPU device 1000 that handles data in ascending order includes a circuit that drives the ascending signal line 41 to low while the system bus is in use. The CPU device 1100 that handles data in descending order includes a circuit that drives the descending signal line 42 to low while the system bus is in use. Also, the memory device 1200 includes a circuit that returns an error to the master device when both the ascending signal line 41 and the descending signal line 42 are low or high when accessed.

In the information processing apparatus configured as described above, by assigning dedicated signal lines to the ascending signal and the descending signal, respectively, when the master device accesses the slave device, the ascending signal line 41 and the descending signal line 42 When both are low or high, the slave device can recognize that this access is not normal.

As described above, in the information processing apparatus according to the present invention, the master device is provided with a circuit for outputting ascending / descending signals, and the system bus is provided with ascending / descending signal lines. The device that handles data in ascending order and the device that handles data in descending order access the shared memory, and the device that handles data in ascending order and the device that handles data in descending order handle data exchange in ascending order. It is possible to carry out the process effectively by using the bus width of the system bus without being restricted by the difference between the order and the descending order.

Therefore, a program can be designed without paying attention to the unit of the data width for accessing the shared memory when designing the program for accessing the shared memory as in the related art.

In addition, since data transfer can be performed by effectively utilizing the bus width of the system bus, only a part of the data bus width can be used as in the related art, so that the data transfer time becomes longer. There is also an effect that there is no.

[Brief description of the drawings]

FIG. 1A is a block diagram showing a configuration example of an information processing apparatus according to the present invention, and FIG. 1B is a block diagram showing data used in the information processing apparatus shown in FIG. 1A. FIG. 1 (c) is a block diagram showing a configuration of a device for accessing data in descending order, which is used in the information processing device shown in FIG. 1 (a). FIG. 1D is a block diagram showing a configuration example of a common memory device that can be used in the information processing device shown in FIG. 1A, and FIG. 2 is a block diagram showing the configuration of the common memory device shown in FIG. FIG. 3 is a timing chart for explaining the operation of the information processing apparatus, and FIG. 3 is a block diagram showing another example of the configuration of the information processing apparatus according to the present invention. In the information processing device, in ascending order connected to the system bus FIG. 4 (b) is a block diagram illustrating an example of a device that handles data in a descending order connected to a system bus in a conventional information processing device; FIG. 4 (c) is a block diagram showing an example of a memory device connected to a system bus in a conventional information processing device, and FIG. 4 (d) is a diagram showing FIGS. 4 (a) to 4 (c). 5 (a) to 5 (h) are block diagrams showing a configuration example of a conventional information processing apparatus configured by using each of the devices shown in FIGS. 4 (a) to 4 (d). FIG. 6 is a diagram showing data handled in ascending order or descending order in a conventional information processing apparatus. FIGS. 6 (a), (b), (c) and (d) specify the operation of each bus control unit. It is a logic table showing logic. [Main reference numbers and reference symbols] 10: Data bus, 11: Data bus of D0 to D7, 12: Data bus of D8 to D15, 20: Address bus, 30: Control signal bus, 40: ... ascending / descending signal line, 41 ... ascending signal line, 42 ... descending signal line, 50 ... bus access arbitration line, 61-72 ... driver / buffer, 81 ... lower 8 bits of internal data bus, 82 ... upper 8 bits of internal data bus, 91 ... address generator, 92 ... execution unit, 93 ... instruction decoder unit, 94 ... register unit, 100 ... system bus, 200, 600, 1000 ... data CPU, 210, 310, 440, 610, 710, 810 …… Bus control unit, 300, 700, 1100 …… CPU to access data in descending order, 400, 800, 1200 …… Memory device , 410: Even memory, 420: Odd memory, 430: Address decoder, 500: Ascending order System bus with descending signal lines, 900 ...... system bus, G1 to G12, Gin / out ...... control line

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 5/00 G06F 12/04 G06F 15/16-15/177

Claims (2)

(57) [Claims] 1. A system comprising: a system bus; and a circuit for outputting, to an ascending signal line of the system bus, a signal indicating that the arrangement of the data is in ascending order when writing and reading data via the system bus. A first master device that obtains a right to use the bus by outputting a signal to a bus access arbitration line of the system bus, and a sequence of the data in a descending order when writing and reading data via the system bus A second master device comprising a circuit for outputting a signal indicating the following to a descending signal line of the system bus, and obtaining a right to use the system bus by outputting a signal to the bus access arbitration line; and the first master device. Alternatively, when a data write is requested from the second master device, the data indicated by the signal of the ascending signal line or the signal of the descending signal line is output. The data is written to the memory in a predetermined ascending or descending order of data according to the sequence, and when the first master device or the second master device requests reading of the written data, the ascending signal line Or an ascending / descending data conversion circuit for rearranging the data for outputting the written data in an arrangement of the data indicated by the signal of the descending signal line or the data indicated by the signal of the descending signal line, and having the right to use the system bus. A slave device, wherein the slave device has the signal indicating the ascending order and the signal indicating the descending order on both the ascending signal line and the descending signal line, and the first Information for exchanging data via a system bus, which returns an error signal to a master device and the second master device. Management apparatus. 2. A first CPU device comprising: a circuit for outputting a signal indicating that the data arrangement is in ascending order to an ascending signal line of the system bus when writing and reading data via a system bus; A second CPU device comprising: a circuit that outputs a signal indicating that the arrangement of the data is in descending order to a descending signal line of the system bus when writing and reading data via the system bus; and When a data write is requested from the CPU device or the second CPU device, a predetermined ascending or descending data sequence is stored in the memory in accordance with the sequence of the data indicated by the signal of the ascending signal line or the signal of the descending signal line. When the data is written and the first CPU device or the second CPU device requests reading of the written data, the signal of the ascending signal line or the descending signal is output. A memory device including an ascending / descending data conversion circuit for rearranging data for outputting the written data in an arrangement of data indicated by line signals, wherein the memory device includes the ascending signal If both the signal indicating the ascending order and the signal indicating the descending order are present on both the line and the descending signal line, an error signal is returned to the first CPU device and the second CPU device. An information processing apparatus for exchanging data via a system bus.