JPS593665A - Multiaccessible memory system - Google Patents

Abstract

PURPOSE:To shift the right to use a memory on every access operation and to utilize the memory effectively by inputting an access control signal directly to a control circuit and carrying out switching every time word access unit is attained. CONSTITUTION:An arithmetic processor 1A when reading data out of a memory device 4 inputs the access control signal CTRL#A of a signal READ to a control circuit 3. The control circuit 3 sends back an acknowledge signal ACK#A if the output Q of a flip-flop 13 is (1). Switches 5, 6, and 7 are driven through a selection signal line 20A to connect a control signal line 16A, address signal line 18A, and data signal line 19A to the memory device 4. The calculating processor 1A once reading data stops sending the control signal CTRL#A and the transmission of the acknoweldge signal ACK#A is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention provides a multi-accessor pull memory system, in particular a memory device shared by a plurality of arithmetic processing units, without having the right to use it occupied in advance by a request signal. ,
■Multi-accessor pull that can be changed for each access.
It concerns memory systems.

(2) Conventional technology and problems When a plurality of arithmetic processing units that perform data processing exchange data between the arithmetic processing units, the conventional technology.

For example, DMA
(Direct Metnory Accgss)
Data was exchanged using methods such as Also.

Now instead of using techniques such as DMA.

Multiple processing units share one memory device.

FIG. 1 shows an example of a conventional method, and FIG. 2 shows a time chart illustrating the operation of the example of the conventional method shown in FIG. 1.

In the figure, 1"A and IB are arithmetic processing units, 2A and 2B are buses, 3 is a control circuit, and 4 is a storage device.

5 to 7 represent switches.

The two arithmetic processing units IA and IB each have a bus 2A,
The memory device 4 is shared via 2B. To access the /1 memory device 4, a request signal REQ is sent to the preliminary control circuit 3, the right to use is confirmed by an acknowledge signal ACK from the control circuit 3, and then a READ signal is issued. access control signals such as the 1iWRITE signal CTRL and the memory device 4
Sends an address signal ADDRESS indicating the address of.

Data is read and written using the data signal DATA.

That is, as shown in FIG.
When using the memory device 4, first, a request signal REQsA is sent out. At this time, if the memory device 4 is empty, an acknowledge signal ACKsA is returned by the control circuit 3. After that, the request signal R
While EQsA is on, the memory device 4 is connected to the arithmetic processing unit IA.
The :I control signal CTRL#A enables data transmission and reception using the data signal DATASA. During this time, the arithmetic processing unit IB cannot use the memory device 4, and the request signal REQsB
requests will be made to wait. Arithmetic processing unit IA stops sending request signal REQ#A.

Only after disconnecting the memory device 4 does the acknowledge signal A
CKsB is returned and the arithmetic processing unit IB is transferred to the memory device 4.
will be able to use it.

According to the above-mentioned conventional system, a sequence of sending the request signal REQ for exchanging the right to use the memory is required, which not only makes the control complicated.

While one arithmetic processing unit exclusively uses the memory device 4,
There is a problem in that the other arithmetic processing unit cannot access the memory device 4 even if data is not actually being exchanged.

(3) Purpose and Structure of the Invention The present invention aims to solve the above-mentioned problems, and aims to enable effective use of memory by making it possible to change the right to use memory for each access with a simple audience. I'm here. Therefore, the present invention focuses on inputting access control signals such as READ signals and WRITE signals directly to the control circuit instead of request signals, and making it possible to switch by the access control signal in word access units. be. In other words, the multi-accessible memory system of the present invention is a system having a memory device that can be accessed from a plurality of buses corresponding to a plurality of arithmetic processing units. a control section that sends an acknowledge signal when no acknowledge signal is sent to another bus and also outputs a select signal for selecting a bus; and a bus to which the acknowledge signal is sent in response to a select signal from the control section. control signal line.

The memory device is characterized in that it includes a select section that connects address signal lines and data signal lines to the memory device. This will be explained below with reference to the drawings.

(4) Embodiment of the Invention FIG. 3 shows a configuration of an embodiment of the present invention, and FIG. 4 shows a time chart for explaining the operation of the configuration shown in FIG.

In the figure, symbols IA, IB to 7 correspond to those in FIG. 1, 8 is a select section, and 9 to 12 are AND circuits.

13 is a flip-flop, 14 and 15 are knockout circuits, 16A and 16B are access control signal lines,
17A, 17B are acknowledge signal lines, 18A, 18B
is the address signal line, 19A.

19B represents a data signal line, and 20A and 20B represent select signal lines.

Arithmetic processing t [access control signal line 1 from IA
6A is connected to the AND circuit 9 of the control circuit 3 and the switch 5 of the select section 8.

Similarly, access control signal line 16B from arithmetic processing unit IB is connected to AND circuit 10 and switch 5. Flip flop 13.

It is an R-8 type 7 lip-flop, and the output Q is "1".
When , a select signal for selecting bus 2A is sent to the select section 8, and when output Q is rlJ, a select signal for selecting bus 2B is sent. The select signal is switch 5
, 6.7 and driving switch 5.6.7,
Memory device 4, control signal lines 16A, 16B, address signal lines 18A, 18B, data signal lines 19A, 1
Switch the connection with 9B.

Acknowledge signal ACKs on acknowledge signal line 17A
A is output when the AND circuit 11 outputs the control signal CTRL*A and the output Q of the flip-flop 13 is rIJ. Also, the acknowledge signal ACK#B is output to the acknowledge signal line 17B.

The control signal CTRLsB is output, and the output Q
is "1".

The flip-flop 13 confirms that the control signal CTRL#A is sent by the output of the AND circuit 9, and that the acknowledge signal ACKsB is rOJ.
The reset state is set to the set state on the condition that the output Q of the flip-flop 13 is rIJ. Also, under the conditions that the control signals CTR and LsB are being sent, that the acknowledge signal ACK*A is rOJ, and that the output Q of the flip-flop 13 is rlJ, it is switched to the reset state and the output Q is rlJ.

The operation during memory access is as shown in the time chart shown in FIG. 4, for example. For example, when the arithmetic processing unit IA reads data from the memory device 4, the access control signal CTRLsA of the READ signal is sent to the control circuit 3. Control signal CTRL#A
is normally output for each access unit of one word. If the output Q of the flip-flop 13 is rlJ, the control circuit 3 immediately returns an acknowledge signal ACKsA. Further, if the output ◇ is "1" and the acknowledge signal ACKsB is not output to the arithmetic processing unit IB, a set signal is output to the flip-flop 13 so that the output Q becomes rlJ, The acknowledge signal ACK#A is output. At this time, the switches 5, 6.7 are driven via the select signal line 20A, and the control signal line 16A and address signal line 18 are driven.
A.

The data signal line 19A is connected to the memory device 4.

Thereafter, data is transferred from the memory device 4 via the data signal line 19A. When the arithmetic processing unit IA reads the data, it stops sending out the control signal CTRL#A, and stops sending out the acknowledge signal ACKaA. This is one access cycle.

When the control signal CTRLsB is sent from the arithmetic processing unit IB while the acknowledge signal ACKsA is being sent to the arithmetic processing unit IA.

The access request is made to wait until sending of the acknowledge signal ACK*A is stopped. but.

Since the transmission of the acknowledge signal A CK s A is stopped at the end of the access, the access request from the arithmetic processing unit IB does not have to wait for a long time.

Arithmetic processing bag [After accessing one word of IA.

Acknowledge signals A, CK, and B are immediately sent.

Data transfer becomes possible. In other words, the right to use the memory can be changed for each access.

Above, we have explained the case where there are two arithmetic processing units, but
The same applies to the case of three or more units. Furthermore, by adding a mechanism to the control circuit 3 that prohibits access to specific addresses from specific arithmetic processing units, it is also possible to construct a system in which the memory space occupied by each unit changes over a period of two hours. can.

(5) As described in detail of the invention, according to the present invention, even if there is a time when a certain processing unit does not access memory while it is monopolizing the memory by a request signal, other processing units cannot access the memory. , the problem of not being able to utilize that time is resolved, and.

Complex transfer control procedures are no longer necessary, and the time required for transfer and the load on software for transfer control can be reduced.

[Brief explanation of the drawing]

Fig. 1 is an example of the conventional method, Fig. 2 is a time chart illustrating the operation of the example of the conventional method. A time chart illustrating the operation of the illustrated configuration is shown. In the figure, LA and IB are arithmetic processing units, 2A and 2B are buses,
3 is a control circuit, and 4 is a memory device. 8 represents a selection section. Patent applicant Fujitsu Limited

Claims (1)

[Claims] In a system having a memory device accessible from a plurality of /(s) corresponding to a plurality of arithmetic processing units,
a control section that sends out an acknowledge signal for each access control signal from the one bus when no acknowledge signal is sent to the other seven buses, and also outputs a select signal for selecting a bus; A control signal line of a bus to which the acknowledge signal is sent in response to a select signal from a control unit.A multi-access pull memory characterized by comprising a select unit that connects an address signal line and a data signal line to the memory device. ·system.