JPH0351943A - Sharing system for high/low speed bus lines - Google Patents

Abstract

PURPOSE:To attain the mixed use of both high and low speed slave devices with use of a single bus by dividing an access given to a slave device like a magnetic disk device, for example, having a comparatively long access time into the address transfer and the data transfer. CONSTITUTION:An access slave 4 usually serves as a main storage like a high speed access device, etc., and a divided access slave 5 usually serves as an I/O device of a low speed access like a magnetic disk device, etc., respectively. For a low speed I/O device 5, a split access is carried out to use a data bus 15 and an address bus 14 with division carried out between the address and data states. Therefore an address is outputted first and the bus 14 is once released for an access given to the device 5. Thus other devices can use the bus 14 and the bus 15 is used again when the data are outputted. As a result, a high speed access device like a main storage and a low speed access device like an I/O device can be used via a common bus.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 7) Means for solving the problems to be solved by the invention (Figure 1) Working examples (Figure 2) ~Figure 6) Effects of the invention [Summary] Regarding the bus line sharing method for high-speed buses and low-speed buses, high-speed normal access devices such as main memory and low-speed access devices such as I/O are used on a common bus. In a data processing system that has a high-speed normal access slave, a low-speed divided access slave, and a master that accesses each slave, the normal access slave is
A common address bus and data bus are provided for the slave and the divided access slave, and when accessing the divided access slave, the address is first transferred, the bus is released once, and the normal access slave is made accessible, and then It is characterized by data transfer.

[Industrial application field]

The present invention relates to a bus line sharing method for sharing a high-speed system bus and a low-speed I/O bus. Large-scale information processing systems often have a high-speed system bus and a low-speed I/O bus. A high-speed system bus is used for data transfer between a processor, a channel device, and a main memory, and the data transfer efficiency determines the performance of the system. Also, the low speed I/O bus is much slower than the high speed system bus. This is based on the fact that since I/O access usually involves mechanical operations, the access time is very long, and even low speeds are sufficient.

In recent years, due to the technological trend towards higher performance microprocessors and smaller size as typified by laptop-type personal computers, it is becoming increasingly important to improve the performance, size, and cost of information processing systems to ensure superiority over other companies' products. It is greatly closed asap on the scale.

From this point of view, it is important to reduce the size and cost of a small information processing device by using the two bus structures of a large information processing system, such as a high-speed system bus and a low-speed I/O bus. There is a need for an architecture that can achieve smaller size and lower cost.

[Conventional technology]

FIG. 7 shows a typical example of a system constructed using a conventional high-speed system bus and low-speed ■/○ buses. In FIG. 7, 101 is a low-speed bus, 102 is a high-speed system bus,
103 and 104 are I/O devices such as a magnetic disk device, a magnetic tape device, and a printer, which are equipped with DMACs (direct memory access control units) 110 and 111, respectively; 105 is a processor; and 106 is a channel. device, 107 is a processor;
108 and 109 are main storage devices, respectively.

The I/O devices 103 and 104 have master and slave functions. Processor 105 performs master operations on main storage devices 108 and 109. The processor 107 not only performs master operations on the main memories 108 and 109, but also performs master operations on the I/O devices 108 and 109.
3, 104 performs master operation. Channel device 106 connects D from I/0 1 0 3, 104
Converts the MA from a low-speed bus to a high-speed bus, main memory 108,
Master operation is performed for 109.

In FIG. 7, arrows A and D indicate DMA (direct memory access) from the I/O device 103 to the main storage device 108. On the low-speed bus 101, I/
The O device 103 becomes the master of the low-speed bus 101, acquires the right to use the bus after bus arbitration, and performs bus transfer. The slave at this time is the channel device 106. When the channel device 106 is accessed from the low-speed bus 101 in this way, it starts as the master of the high-speed bus 102, and after arbitration of the high-speed bus 102, the high-speed bus 10
2 and transfers data to and from the main storage device 108. Channel device lO6 is connected to low speed bus 101
The high-speed bus 102 functions as a buffer to fill the speed difference between the high-speed bus 102 and the high-speed bus 102, and serves to minimize the bus occupation time on the high-speed bus 102.

Further, arrows C and E indicate access to the main storage devices 108 and 109 of the processors 105 and 107.

Processors 105 and 107 start as bus masters,
After arbitration, data transfer is performed. This access time greatly influences system performance, so the smaller the waiting state due to other accesses and the faster the access response, the better.

Arrow B in FIG. 7 is an access for the processor 107 to instruct the I/O device 104 to perform transfers such as arrows A and D. The DMAC of the I/O device 104 is
As a result, similar to arrows A and D, DMA is performed on the main memory 108 or 109 via the channel device 106. The processor 107 starts as a master for the low-speed bus 101 and performs data transfer after arbitration. [Problem to be Solved by the Invention] In the conventional system shown in FIG. Since this method requires several buses, there is a problem in that the device becomes large and costly.

Therefore, it is an object of the present invention to provide a bus line for a high-speed bus and a low-speed bus, in which a high-speed processor, main memory, etc. and a plurality of low-speed I/O devices share a bus line while performing bus arbitration for each bus. The purpose is to provide a sharing method.

[Means to solve the problem]

In order to achieve the above object, in the present invention, as shown in FIG. 1(A), a first master 1, a second master 2, a third master 3
, the normal access slave 4, the divided access slave 5, etc. are connected on a common bus.

Here, the first master 1 to the third master 3 are composed of, for example, a processor, a channel device, and the like. The normal access slave 4 is, for example, a main storage device that is a high-speed access device, and the divided access slave 5 is a low-speed access I/O device such as a magnetic disk device, magnetic tape device, printer, etc.
It is a device. The bus also includes access request signal lines 10 to 12 output by the first master 1 to third master 3, a busy signal line 13 indicating that this bus is in use, and an address line (multiple bit width) 14. , data line (multiple bits)
(width) 15 and normal access for access requests.
It is equipped with a response signal line 16 from the slave 4, a response signal line 17 from the split access slave 5 in response to a split access request (described later), and a sprint busy signal line 18 indicating that split access is in progress. .

In the present invention, for low-speed I/O devices and the like, subrift access is performed using a data bus and an address bus by dividing address time and data time. Therefore, when accessing an r/O device, first output the address, then release the address bus to make it available for use by other devices, and when the data of the previously accessed I/O device is sent out, the data is re-entered. Use the bus.

For example, when the first master 1 makes an access request to the divided access slave 5, which is a low-speed I/O device, at time T2 shown in FIG. When a divided access is not being performed, that is, when the SBUSY signal is not at L level (active), a master adjustment circuit (not shown) performs bus arbitration and starts access. In this case, when reading, the address is valid, and when writing, the address and write data are valid, and REQI is negative (H level).
Make it. Furthermore, the bus is released after the divided access slave 5 waits for the divided access response signal SACK to become active (L level). That is, -BUSY is returned to H level. At this time, the first master 1 holds the SBUSY signal at L level and prohibits divided access by other masters.

If this divided access is a read, the selected divided access slave 5 causes the bus request code R to be read at time T4.
EQI (L level) is output, bus arbitration is performed, and when the bus becomes usable, the divided access slave 5 makes the divided access response signal SACK active again, and at this time, the data output to the data vA15 is transferred to the first Master 1 samples and reads. and time T
At a', the divided access prohibited state is released. Furthermore, in the case of writing, the divided access slave 5 will take in the data being output to the data line 15 when SACK is made active again.

On the other hand, an access to the normal access slave 4 is performed by the third master 3 at time T1, and the bus request signal RF. When outputting Q3 (L level), a master adjustment circuit (not shown) performs bus arbitration, and when the right to use is obtained, the BUSY signal is made active (L level).

At this time, the normal access slave 4 receives the response signal ACK.
It responds by making it active (L level). This normal access differs from the divided access in that addresses and data are transferred during the bus cycle.

In FIG. 1(B), -BUSY indicates that the master is using the bus for another master. ADH is an address signal for a master to select a slave. That is, by decoding the address, it is possible to identify whether the access destination is the normal access slave 4 or the divided access slave 5.

DATA is data transferred between the master and slave, -ACK is a normal response signal in normal access, -
SACK is an address response signal and an access end response signal for divided access. -SBUSY is a signal indicating that the master in the process of dividing access is in the process of dividing access, and indicates to other masters that the divided access is prohibited.

[Effect]

In the present invention, access to a slave with a long access time such as an I/O device is divided into address transfer and data transfer, thereby avoiding long-term bus occupation and effectively utilizing the bus of other masters. can be measured. By performing bus control in this manner, two low-speed and high-speed buses can be shared by one bus, thereby making it possible to reduce the size and cost of the information processing system. Furthermore, the reduction in transfer efficiency as a high-speed bus can be minimized.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 2 to 6.

FIG. 2 is a schematic configuration diagram of an embodiment of the present invention, FIG. 3 is an example of a master adjustment circuit provided in each master, and FIG. 4 is an example of a split access slave arbitration circuit provided in a split access slave. , FIG. 5 is an example of a normal access/slave response circuit provided in a normal access slave.
The figure is a time chart for explaining the operation of the present invention.

In Figure 2, the system is configured with three masters: first master 1 to third master 3, one normal access slave 4, and one divided access slave 5. . In Figure 2, to simplify the explanation, Figure 1 (A
) The address bus, data bus, etc. shown in ) are omitted. In FIG. 2, the same symbols as in FIG. 1(A) indicate the same parts, and 19 is a start signal line to which a start signal START is applied. The first master 1 is provided with a master arbitration circuit II that performs bus arbitration based on predetermined priorities when access requests from each master conflict. Also, the second master 2
, the third master 3 also has a similar master arbitration circuit Fr1.
2 and 13 are provided. In this embodiment, the priority order is defined as the third master, the second master, and the first master in descending order of priority. The normal access slave 4 is provided with a response circuit 14, and the divided access slave 5 is provided with a slave arbitration circuit 15.

An example of the master arbitration circuit will be explained with reference to FIG.

In FIG. 3, 2l and 22 are flip-flops (hereinafter referred to as FF), 23 is a NAND gate, 24 is an AND gate, 25 is an OR gate, 26 is a three-man AND gate, 27 is an inperter, and 28 , 29, 30 are FF
, 31, 32, 33, 34 are tri-state, 35,
36, 37, and 38 are AND gates, and 39 is an FF.

FF21 outputs rlJ when this master accesses normal access slave 4, and FF22 outputs rlJ when this master accesses divided access slave 5.
This outputs the following. That is, masters l to 3 (hereinafter simply referred to as masters) decode the access destination address,
A normal access space signal or a split access space signal is applied to FF21 or FF22 depending on whether the access destination is normal access slave 4 or split access slave 5.

The AND gate 26 receives an access request signal REQH and a busy signal BU from a master with higher priority than its own master.
When both SYs are H, that is, when there is no access request from a master with a higher priority and when the master is not in a busy state, it is in the on state.

Therefore, in order for a master to access the normal access slave 4, there is no access request from a master with higher priority than the master (-REQH → "1"), and the master is not in a busy state (-BUSY → rlJ). Outputs the address to normal access slave 4. Normal access/
When access is made to slave 4, the master decodes this address and sets the normal access space signal to "1" and applies it to FF21, and FF21 outputs "1".
Since the OR gate 25 also outputs "1" and the inverter 27 outputs "0", the tristate 3l outputs the request signal -REQ to instruct an access request. At this time, if there is no access request from a master with higher priority than itself, and if another master is not using the bus, REQH is rlJ and -BUSY is also "1", so from OR gate 25 When the rN is output, the AND gate 26 also outputs rlJ, and FF2
The tri-state 32 is turned on by the Q output of 8, and -S
Outputs TART signal "0".

At the same time, +MY-START signal becomes "1" and FF21
is reset, and as a result, the -REQ signal is turned off. The "1" output from the AND gate 26 is also applied to the FF 29, and the access end timing is set to the FF 29.
When applied to terminal K of 29, its d output turns on tristate 33, indicating that the bus is in use.
Outputs Y signal rOJ.

Further, when the master accesses the divided access slave 5, the master decodes the address destination and sets the divided access space signal to "1", and the FF 22 outputs "1".

At this time, if REQH is "IJ" and -BUSY is "1", the AND gate 24 outputs "1", the OR gate 25 outputs "1", and the AND gate 26 outputs rlJ, and similarly -REQ , -START, and -BUSY each become "0". At this time, the divided address space signal "1" is also input to the AND gate 35, and "1" is output, and the -MYSBUSY signal on the Q side of the FF 30 becomes r.
Since it becomes OJ, the tristate 34 turns on, indicating that the divided access slave 5 is being accessed.
Set SBUSY to rOJ.

An example of the divided access slave arbitration circuit 15 is shown in FIG.

In Fig. 4, 40 is a decoder, 4l is an AND gate operated by three people, 42 to 44 are AND gates, and 45 to 47
is FF, 48-50 is AND gate, 51-53 is F
F, 54 to 56 are tri-state, 57 is OR gate, 58 is FF1, 59 is tri-state, 60 is FF,
61 is a tristate, and 62, 63, and 64 are AND gates.

When the divided access/slave arbitration circuit 15 decodes the address on the address bus (not shown in FIG. 2) using the decoder 40 and recognizes that the access destination is itself, the divided access/slave arbitration circuit 15 outputs "1".
Output. At this time, "1" is output from the AND gate 41, and the AND gates 42 to 44 selected by the REQ signal REQI-REQ3 are turned on, and the corresponding tristates 54 to 56 are turned on, and -REQI~
3 is output. At this time, there is no REQI~3 with higher priority than the output -REQI~3, and -BUSY
Wait until the FF is turned off, and when it reaches the above state, the tristate 59 is also turned on, -BUSY is output, and the FF
Tri-state 6l is also turned on by 5B and 60 -S
ACK is output.

An example of the normal access/slave response circuit 14 is shown in FIG.

In FIG. 5, 7l is a decoder, 72 is an AND gate, 73 is an FF, and 74 is a tristate.

The normal access/slave response circuit 14 decodes the address on the address bus (not shown in FIG.
Output. At this time, if the START signal is "1", rlJ is output from the AND gate 72, the tristate 74 is turned on, and the -ACK signal "0" is output.

Next, the operation of the present invention will be explained with reference to the time chart shown in FIG.

(1) At time TI in FIG. 6, there are requests -REQI to -REQ3 from the first master 1 to third master 3 shown in FIG.
3 has the highest priority, the third master 3 performs normal access and outputs one BUSY and one START.

(2) When the access by the third master ends at time T2, -REQI and -REQ2 exist, but since their priority is high, the second master 2 obtains the right to use them. At this time, it is assumed that the second master 2 performs divided access to the divided access slave 5. For this reason, -SBUSY is output at time T3, and an address is output at the same time. As a result, the divided access slave 5 recognizes that it has been accessed by its decoder 40, and outputs -SACK at time T4. Further, the second master 2 sets -BUSY to "1" at time T4 to release the busy state. But - SBUSY continues as it is,
Prohibit sprint access to other masters.

(3) At time T5, the access request to the normal access slave 4 is granted to the third master 3, and at time Ta, the normal access slave outputs -ACK and normal access is performed.

(4) At time T6, the divided access slave 5 determines that the timing is such that data can be read or written to the second master 2, and outputs -REQ2. Then, at time T7, the divided access slave outputs -SBUSY, and at time T8, the divided access slave 5 outputs -SACK. At time T8, the divided access slave sends data onto a data bus (not shown) in the case of data access, that is, read, and takes in the data on the data bus in the case of write.

(5) At time T9, -SACK becomes "1" and -SBUSY from the second master 2 also returns to rN, so
Partial access is possible again.

Note that although the above description has been made for the case where the number of masters is three, the present invention is of course not limited to this number.
It can be carried out in the same way whether it is 3 or more or 3 or less.

Although an example in which each master is provided with a master arbitration circuit has been described, the present invention is of course not limited to this, and the present invention can be implemented even when a common master arbitration circuit is provided.

〔Effect of the invention〕

In the present invention, by dividing access to a slave such as a magnetic disk device, which has a relatively long access time, into address transfer and data transfer, it is possible to prevent the bus from being occupied for a long time. During the division, a normal access slave such as main memory can be accessed.

Therefore, instead of the conventional two-bus configuration in which low-speed slaves such as magnetic disks are accessed separately by a low-speed bus, and normal access slaves are accessed separately by a high-speed bus, one bus configuration is used. The bus makes it possible to use such high-speed slaves and low-speed slaves in a mixed manner, making it possible to use the bus efficiently.

In addition, since the number of buses can be reduced to one, it is also possible to reduce the size and cost.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, Fig. 3 is an example of a master arbitration circuit, Fig. 4 is an example of a divided access slave arbitration circuit, FIG. 5 shows an example of a normal access slave response circuit, FIG. 6 shows a time chart explaining the operation of the present invention, and FIG. 7 shows a conventional example. l 1 1 - First master 2 - Second master 3 - Third master 4 - Normal access slave 5 - Split access slave

Claims (1)

[Claims] In a data processing method that includes a high-speed normal access slave, a low-speed divided access slave, and a master that accesses each slave, the normal access slave (4) and the divided access slave (4) A common address bus (14) and a data bus (15) are provided for the slave (5), and when accessing the divided access slave (5), an address transfer is first performed, and then the bus is released and the normal access slave is accessed. (4) A bus line sharing method for a high-speed bus and a low-speed bus, characterized in that the bus line is made accessible and then data transfer is performed.