JPH07160655A - Memory access system - Google Patents

Abstract

PURPOSE:To provide a memory access technique capable of reducing access standby and suppressing the frequency increase of the access standby especially for the enlargement of a shared area while maintaining the identity of data for respective processors as a shared memory. CONSTITUTION:In an information processor for which symmetrically constituted controllers 1 and 2 provided with the shared memories 8 and 8A provided with 2-port memories 12 and 12A and memory control parts 11 and '11A, host processors 6 and 6A and device processors 7 and 7A mutually access the shared memories 8A and 8 of each other through an inter-memory interface 9 composed of a data bus line 13 and a control line 14 and maintain the identity of the contents of the shared memories 8 and 8A at all times, access requests generated in the respective memory control parts 11 and 11A and the memory addresses are transferred between the memory control parts 11 and 11A and access to the other addresses is processed independently by the respective memory control parts 11 and 11A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access technique, and more particularly to a technique effective when applied to an information processing device having a structure in which a plurality of processing devices share a memory.

[0002]

2. Description of the Related Art When a plurality of processing devices share data in a memory, it is necessary to perform exclusive control for access from the processing devices in order to guarantee the sameness of the shared data with each device. There is. However, the access wait that occurs due to this exclusive control deteriorates the processing speed of each processing device and reduces the efficiency of the entire system.

Various methods have been proposed in order to minimize such an access wait. As one method, the technique disclosed in Japanese Patent Laid-Open No. 61-138359 discloses that a memory is provided for each processing device. After allocating it, it is further divided into a shared area and a non-shared area, and only the write to the shared area is simultaneously written to all the memory by using exclusive control, and other access is proposed independently. .

[0004]

Although such a prior art method is effective in reducing the frequency of waiting for access by limiting the access requiring exclusive control,
Even in this case, an access wait occurs each time each processing device accesses the shared area, and the frequency of the access wait increases due to the expansion of the shared area and the increase in the number of processing devices as the system grows in size. However, the efficiency decrease becomes remarkable as the shared area increases.

An object of the present invention is to reduce access wait while maintaining the sameness of data to each processing device as a shared memory, and particularly to suppress increase in access wait frequency as the shared area is expanded. It is to provide a memory access technology capable of performing the above.

Another object of the present invention is to generally minimize the occupied area in a memory occupied state required for each processing unit when using a shared memory and wait for access from another processing unit. It is to provide a memory access technology capable of reducing the number of times.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

That is, the present invention includes a plurality of memories, a plurality of processing devices that access the memories, and a plurality of memory control units that control the access for each of the memories. In the information processing device in which the information in the memory can be shared by all the processing devices by always matching the contents of the
The access request and the memory address of the access request are passed, and accesses to other addresses are processed by each memory control unit independently.

For example, the memory shared by a plurality of processing devices may be a multi-port memory that has a plurality of ports and is accessible from each port. Further, writing and occupation of the memory can be controlled for each address.

[0011]

In the memory access method of the present invention described above, for example, a multiport is used as the memory, and this is arranged for each processing device. This memory can simultaneously read and write from a plurality of ports, but its contents are not guaranteed if the same address is simultaneously written to from a plurality of ports.

When a write or memory occupancy request is generated in a certain processing device, the corresponding memory control sends the address together with the write or occupancy request to another memory control unit. The other memory control unit returns a request permission to the request source unless the received address is being read / written or occupied by its own processing device. The request source waits until this permission is returned, and when it receives the permission, it writes the data in its own memory at the same time as writing, and at the same time sends the data to another memory control unit, and when occupying it, it sends it to the processing device.
Report occupancy complete. The control unit that has returned the request permission waits for the write data from the request source and also holds the access request from its own processing device to this address until there is no request. At this time, all access to the area other than the request-permitted address is executed.

Thus, for writing to the memory,
Since data is always written to all memories at the same time,
As a shared memory, the identity of data to all processing devices is guaranteed. Moreover, since the access wait occurs only when writing or occupying the same address, the access wait frequency does not increase due to the expansion of the shared area.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a main part of an information processing apparatus in which a memory access system according to an embodiment of the present invention is implemented, and FIG. 2 shows an example of the overall configuration. It is a block diagram.

In this embodiment, as an example of an information processing apparatus, an example applied to a control device of an external storage device will be described. The external storage device mentioned here refers to a computer peripheral device such as a magnetic disk device or a magnetic tape device, and the control device controls the external storage device.

As illustrated in FIG. 2, a plurality of control devices 1 and 2 having completely equivalent configurations to each other are
It is interposed between the storage device 10 and a host device (not shown).

The control device 1 is composed of the following parts. The host interface 3 is a part that controls an interface with a higher-level device, and also controls data transfer in addition to protocol control. The device interface 4 is
In the part that controls the interface with the storage device 10,
Like the host interface 3, it controls protocol control and data transfer. Data can be directly transferred between the host interface 3 and the device interface 4, but can also be transferred via the cache memory 5. When passing through the cache memory 5, the data transfer on the host side and the data transfer on the device side are asynchronous, so that these are independently controlled by the two host processors 6 and the device processors 7. That is,
The host processor 6 controls the host interface 3, and the device processor 7 controls the device interface 4.

The shared memory 8 is a shared memory for storing control information commonly required by the host processor 6 and the device processor 7. The shared memory 8 is writable by both the host processor 6 and the device processor 7, and at the same time, One processor occupies a specific address and also has a function of inhibiting reading and writing from the other.

The control device 2 is the same as the control device 1, and the inside of the control device 2 is completely symmetrical to the control device 1. In addition,
In the following description, an uppercase letter "A" is added to the reference numeral of a component on the control device 1 side for a component equivalent to the control device 1 in the control device 2.

The shared memory 8 of the controller 1 and the controller 2
Shared memory 8A is connected by a memory-to-memory interface 9, whereby two shared memories 8 and 8A are connected.
Operates logically as one shared memory. That is,
It is possible to share the data from the two processors of the control device 1 and the two processors of the control device 2 and to occupy the data from any one of the processors.

Next, the operation of the two shared memories 8 and 8A will be described with reference to FIG.

FIG. 1 is a block diagram showing the internal structure of the shared memories 8 and 8A extracted from each of the control devices 1 and 2.

The 2-port memory 12 is a memory which can be read and written independently from the two ports, and data is input to and output from the respective ports by the data bus line 17 and the data bus line 13.

The memory control unit 11 includes a 2-port memory 12
The control line 18 and the control line 19 instruct the memory address, write / read switching, and write timing to the port. At the same time, the memory control unit 11 is connected to the memory control unit 11A of the other control device 2 by the control line 14, and controls the two-port memory 12 and the two-port memory 12A to be displayed as one memory together.

Next, the operation of the entire shared memory centering on the memory control unit 11 will be described.

Access to the shared memory 8 from the host processor 6 (device processor 7) is performed by the control line 1
5 (control line 16) and data bus line 17. The control line 15 (control line 16) includes a read / write request, an occupancy request, an occupancy release request, and a memory address from the host processor 6 (device processor 7) to the memory control unit 11, and the memory control unit 11 to the host processor 6 ( A read / write request to the device processor 7) and an occupancy permission are included.

When reading from the shared memory 8, the host processor 6 sends a read address and a read request to the memory control unit 11 through the control line 15. Upon receiving the read request, the memory control unit 11 confirms that there is no access request from the device processor 7, the specified memory address is occupied by another portion, and that the other control device 2 is not writing data. Control line 19
After instructing the memory address and the read using, the read permission is returned to the host processor 6. The host processor 6 that has received this permission receives the data bus line 17
Read the above read data and cancel the request.

If there is either an access request from the device processor 7, an occupied state for the designated memory, or a write request from the other processor, the read request from the host processor 6 is as described above. Execution is suspended until the end.

When writing from the host processor 6 to the shared memory 8, a write address and a write request are sent to the memory control unit 11 via the control line 15. Upon receiving the write request, the memory control unit 11 confirms that there is no access request from the device processor 7, and the instructed memory address is neither occupied by another portion nor being written by the other control device 2. After confirmation, the write address and the write request are sent to the memory control unit 11A of the other control device 2 through the control line 14.

Memory controller 11A of the other controller 2
Sends a request permission to the memory control unit 11 of the control device 1 if there is no write request to the address designated by the host processor 6A and the device processor 7A in the same device. Upon receiving the request permission, the memory control unit 11 on the side of the control device 1 uses the control line 19 to operate the 2-port memory 12
Address to the host processor 6 and send a request permission to the host processor 6 via the control line 15. Upon receiving this request permission, the host processor 6 sends write data to the data bus line 17 and cancels the write request. The memory control unit 11 controls so that the data on the data bus line 17 immediately before the cancellation of the write request is written to the 2-port memory 12, puts this data on the data bus line 13, and the memory control unit 11A of the other control device 2 is controlled. Release write request to. The memory control unit 11A of the other control device 2 writes the contents of the data bus line 13 immediately before the request is released to the designated address of the memory.

At this time, in the memory control unit 11, when there is either an access request from the device processor 7, an occupied state from another portion for the designated address, or a write request from the other control unit 2. The write request from the host processor 6 is suspended until the above is completed.

When the host processor 6 occupies the shared memory 8, the address to be occupied and the occupancy request are sent to the memory control unit 11 via the control line 15.

When the memory control unit 11 receives the occupation request, it confirms that the instructed address is neither occupied nor being written from another portion, and then the memory control unit 11A of the other control unit 2 is notified. An address to be occupied and an occupation request are sent via the control line 14.

If the memory control unit 11A of the other control unit 2 is not reading from the host processor 6A and the device processor 7A in the same device, the memory control unit 11A of the control unit 1 returns the occupancy permission and its address. It is held as an occupied state from the control device 1 for.
The memory control unit 1 of the control device 1 that has received this occupation permission
1 holds that the designated address is in the occupied state from the host processor 6, and returns the occupation permission to the host processor 6 via the control line 15. The host processor 6 which has received the occupation permission cancels the occupation request.

If the designated address is either occupied or written in the control device 1 or is being read in the control device 2, execution of the occupancy request is suspended.

When the exclusive release is performed, the host processor 6
Sends an occupancy release request to the memory control unit 11 via the control line 15. When the memory control unit 11 receives the occupancy cancellation request, it is in the occupancy state from the host processor 6,
After confirming that there is no access from the memory control unit 11A of the other control device 2, the exclusive release request and the memory address to be released are sent to the memory control unit 11A of the other control device 2 via the control line 14.

Memory controller 11A of the other controller 2
When the exclusive release request is received, the controller 1 confirms that the corresponding address is in the exclusive state, releases the exclusive state, and sends an exclusive release permission to the memory control unit 11 of the controller 1. The memory control unit 11, which has received the occupation permission, releases the occupation state from the host processor 6 and sends the occupation release permission to the host processor 6 through the control line 15. The host processor 6 releases the exclusive release request by the exclusive release permission.

If the memory control unit 11 is being accessed by the other control unit 2, the occupancy release is suspended until the end.

Although the case where the shared memory is accessed from the host processor 6 has been described above, the access from the device processor 7 and the access to the host processor 6A and the device processor 7A in the other control unit 2 operate similarly. .

The memory control unit 11 of the control device 1 and the memory control unit 11A of the control device 2 simultaneously avoid the conflict when a request to the other memory control unit 11A (11) occurs. It can be realized by a known means such as controlling division.

According to the present embodiment, since the writing and occupation states can be limited to a specific address, it is possible to freely access other addresses, and the number of times of waiting for access due to competition for access to the shared memory, It is possible to reduce the time.

Further, by using the 2-port memory 12, the memory access in the own control device and the access from the other connected control device can be independently controlled, and further conflict avoidance is possible. is there.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0045]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the memory access method of the present invention, by exchanging the address and the access request between the memory control units, the exclusive control can be limited to a specific address, and the memory access waiting time can be reduced. You can get the effect.

Further, by using a multi-port memory as the memory, it is possible to further reduce the waiting time for access.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a configuration of a main part of an information processing device in which a memory access method according to an embodiment of the present invention is implemented.

FIG. 2 is a block diagram showing an example of the overall configuration.

[Explanation of symbols]

 1 Control Device 2 Control Device 3 Host Interface 4 Device Interface 5 Cache Memory 6 Host Processor 6A Host Processor 7 Device Processor 7A Device Processor 8 Shared Memory 8A Shared Memory 9 Memory Interface 10 Storage Device 11 Memory Control Unit 11A Memory Control Unit 12 2 Port memory 12A 2 Port memory 13 Data bus line 14 Control line 15 Control line 15A Control line 16 Control line 16A Control line 17 Data bus line 17A Data bus line 18 Control line 18A Control line 19 Control line 19A Control line

Claims (1)

[Claims] 1. A plurality of memories, a plurality of processing devices for accessing the respective memories, and a plurality of memory control units for controlling the access for each of the memories, the contents of the plurality of memories. In the information processing device in which the information in the memory can be shared by all the processing devices by always matching the above, between the memory control units,
A memory access method in which an access request and a memory address of the access request are passed, and accesses to other addresses are individually processed by each memory control unit.