KR100874169B1 - Dual port memory for direct transfer of commands between processors and method for performing them - Google Patents

Abstract

A dual port memory for directly transferring processor-to-processor commands and a method for performing the same. The present invention provides a memory array having a shared memory area; A first memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided through a first port from a first processor; A second memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided from a second processor through a second port; And a command transfer processor configured to directly transfer a command output by any one of the first processor and the second processor through one of the first memory interface and the second memory interface to the counterpart processor. According to the present invention, there is an advantage in that a command can be transferred between processors in a dual port memory system without obtaining authority.

Description

Dual Port Memory for directly transferring command between processors and Method of Performing the Same}

1 is a block diagram of a dual port memory system according to the prior art.

2 is a block diagram of a general semaphore processing unit.

3 is a flowchart illustrating a command transfer process from a first processor to a second processor according to the prior art.

4 is a block diagram of a dual port memory system in accordance with a preferred embodiment of the present invention.

5 is a block diagram showing a detailed configuration of a command delivery processing unit according to an embodiment of the present invention.

6 is a flowchart illustrating a command transfer process of a processor according to the present invention.

7 is a flowchart illustrating a command delivery process of a command transfer processing unit and a command execution process of a processor according to the present invention.

The present invention relates to a dual port memory for directly transferring commands between processors and a method for performing the same. More particularly, the present invention relates to a dual port memory capable of transferring commands to each processor without obtaining permission to use a shared memory area. It is about the system.

Recently, portable terminals such as mobile phones and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video phones, and multimedia data playback in addition to mobile communication functions such as voice calls.

The portable terminal is provided with a modem processor for processing the original functions of the mobile communication and an application processor for processing various applications.

In addition, in general, a portable terminal having two processors performs data transmission and reception between the two processors at a high speed, thereby improving the processing performance of the system and reducing the memory footprint of the dual port memory (particularly dual port SDRAM). ) Is used.

In other words, when two processors use dual port memory, each processor can use its own port to access the shared memory area to read and write data, so that the two processors are connected to different memory to each other. Sending and receiving processing data through the host porcessor interface (HPI) is faster and speeds up the data transfer, which improves the overall performance of the system.

1 is a block diagram of a dual port memory system according to the prior art.

Referring to FIG. 1, each processor 100, 104 is connected to a dual port memory (Dual Port Synchronous Dynamic Random Access Memory, 108) via each external bus interface 102, 106.

The dual port SDRAM 108 includes a shared memory area in which two processors jointly access and perform a write or read operation.

Each processor 100, 104 accesses the shared memory area after obtaining rights from the dual port SDRAM 108 if it wishes to access the shared memory area.

The dual port SDRAM 108 utilizes a semaphore 110 to ensure mutual exclusive access of each processor to the shared memory area and to ensure synchronized work between each processor.

FIG. 2 is a block diagram of a general semaphore processing unit. As shown in FIG. 2, the general semaphore processing unit 110 includes a first semaphore request register 200, a second semaphore request register 202, a state controller 204, It consists of a first semaphore register 206 and a second semaphore register 208.

In the first semaphore request register 200, when there is an access right request of the first processor 100, data DQ1 (eg, a logical value '0') for the right request is written, and the second semaphore request register is written. In 202, data DQ2 according to the authority request of the second processor 104 is written.

When there is a request for access right from each processor 100 or 104 as described above, the state controller 204 determines the state of the requested shared memory area, and the first semaphore register corresponding to each processor includes data according to the determined state. 206 or the second semaphore register 208.

For example, when the shared memory area is available when the authority request of the first processor 100 is enabled, the state controller 204 causes the logical value '0' to be written in the first semaphore register 206 and cannot be used. In this case, the logical value '1' is written.

The first processor 100 reads the data written in the first semaphore register 206 and checks whether the right has been acquired, and the second processor 104 has the right through the data read out from the second semaphore register 208. It will check whether it is acquired.

 As such, the semaphore processing unit 110 determines whether or not access to a predetermined shared memory area (permission or not) is based on a binary logic value (for example, '0' or '1') according to a current state of the predetermined shared memory area. By mutually exclusively providing the processors 100 and 104 to each processor, each processor mutually exclusively accesses a predetermined shared memory area.

However, in the related art, since the first processor 100 and the second processor 104 are connected through the dual port memory 108, there is a problem in that even when a command is transmitted between the processors 100 and 104, access rights must be obtained. .

3 is a diagram illustrating a command transfer process according to the related art, in which the first processor 100 transmits a command to the second processor 104.

Referring to FIG. 3, when the first processor 100 intends to transmit a command to the second processor 104, the first processor 100 may authorize the first semaphore request register 200 of the semaphore processing unit 110. Write data for acquisition (step 300).

Thereafter, the first processor 100 reads data provided to the first semaphore register 206 under the control of the state controller 204 (step 302).

It is determined whether the authority is acquired through the read data (step 304), and if the authority is obtained, the first processor 100 transmits to the second processor 104 in the shared memory area of the dual port memory 108. The first command is written (step 306).

After the command is written, the second processor 104 performs the right acquisition process as in steps 200 to 204 (step 308), and reads the first command from the shared memory area after the access right to the shared memory area is obtained. (Step 310).

As described above, the dual port memory system according to the related art delays command transfer because the processor 100 and 104 require the acquisition of authority not only for executing a necessary command but also for transferring a command to a counterpart processor. There was a problem that other processors cannot use the shared memory area during the transfer time.

In the present invention, in order to solve the problems of the prior art as described above, in a dual port memory system, a dual port memory for directly transferring commands between processors that can directly transfer commands from the semaphore processor without obtaining permission from each processor and the same. It relates to a method for carrying out.

In order to achieve the above object, according to a preferred embodiment of the present invention, a memory array having a shared memory region; A first memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided through a first port from a first processor; A second memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided from a second processor through a second port; And a command transfer processor configured to directly transfer a command output by any one of the first processor and the second processor through one of the first memory interface and the second memory interface to a counterpart processor. Dual port memory is provided.

According to another aspect of the invention, the first processor; A second processor; A memory array having a shared memory area, a first memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided through a first port from the first processor, and from the second processor; A second memory interface configured to perform a write or read operation in the shared memory area based on an address and a control signal provided through a second port; and the first memory in any one of the first processor and the second processor. A dual port memory system is provided that includes a command transfer processor for directly transferring a command output through one of an interface and a second memory interface to a counterpart processor.

According to another aspect of the invention, a method for processing command transfer in a dual port memory coupled to a first processor via a first external bus interface and coupled to a second processor via a second external bus interface, comprising: (a) Receiving an address, a control signal, and command data for direct command transfer from the first processor, wherein the address is an address corresponding to a command transfer processor for direct command transfer; (b) decoding the address and control signal and writing the command data to the command transfer processor; (c) outputting an interrupt signal according to the writing of the command data to the second processor; And (d) outputting the command data to the second processor according to the command transfer processor address and the control signal received from the second processor receiving the interrupt signal. Is provided.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first, second, A, and B may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, the same reference numerals will be used for the same means regardless of the reference numerals in order to facilitate the overall understanding.

4 is a block diagram of a dual port memory system according to an exemplary embodiment of the present invention.

As shown in FIG. 4, the dual port memory system according to the present invention includes a first processor 400, a first external bus interface 402 (EBI), a second processor 404, and a second external bus. It may include an interface 406 and a dual port memory 408.

The first and second processors 400 and 404 are units for decoding and executing instructions. The first processor 400 may be a modem processor used in a portable terminal such as a mobile phone, and the second processor 404 may be a portable terminal. It may be an application processor for performing an application such as a video processor, a multimedia processor used in the.

The first external bus interface 402 and the second external bus interface 406 serve as a kind of memory controller. The dual port memory 408 according to the present invention may be configured as an SDRAM. Accordingly, the first and second external bus interfaces 402 and 406 may use an external bus interface of a synchronous DRAM (SDRAM).

Hereinafter, in an embodiment of the present invention, the first external bus interface 402 and the second external bus interface 406 are described as SDRAM external bus interfaces, but are not necessarily limited thereto.

The dual port memory 408 is connected to the first processor 400 having the first external bus interface 402 through the first port 410, and the second external bus interface 406 through the second port 412. Is connected to a second processor 404 having

As shown in FIG. 4, the dual port memory 408 according to the present invention includes a first memory interface 414, a second memory interface 416, a memory array 418, a semaphore processor 420, and a command transfer processor. 422 may be included.

The first memory interface 414 may be configured as an SDRAM memory interface. The first memory interface 414 receives the address control signal CTR1 and the data DQ1 from the first processor 400 through the first port 410, and decodes the address ADD1 into a row address and a column address. After that, the data DQ1 is read from the memory array 210 or written to the memory array 210 according to a predetermined operation timing based on the decoded address.

The writing and reading may be performed in synchronization with a clock signal provided by the first processor 400.

To this end, the first memory interface 414 may include a control signal decoder (not shown), a row decoder (not shown), a column decoder (not shown), and an input / output buffer (not shown) used in a general SDRAM interface. C) and the like.

The second memory interface 416 may be configured as an SDRAM memory interface. After receiving the address ADD2, the control signal CTR2 and the data DQ2 from the second processor 404 through the second port 412, decoding the address ADD2 into a row address and a column address, and then operating timing. As a result, data DQ2 is read from or written to memory array 418.

The second memory interface 416 may include a control signal decoder (not shown), a row decoder (not shown), a column decoder (not shown), and an input / output buffer (not shown) corresponding to the received address and control signal. have.

The memory array 418 has a unit memory cell structure of DRAM and includes a first memory area 424 dedicated to the first processor 400, a shared memory area 426 and a second processor 404 shared by each processor. The second memory area 428 may be dedicated. Each of the memory areas 424 to 428 may be formed in a bank unit having a predetermined size. In addition, each shared memory area may be configured in units of blocks having a predetermined size in one bank.

4 illustrates that one shared memory area 426 exists in the dual port memory system. However, the present invention is not limited thereto, and it will be apparent to those skilled in the art that a larger number of shared memory areas may be provided.

In addition, in the above description, two processors are connected to the dual port memory according to the present invention. However, the present invention is not limited thereto and may be applied to the present invention even when more processors are connected.

The semaphore processor 420 controls mutually exclusive access to the shared memory area 426.

The semaphore processing unit 420 corresponds to each processor, and includes a semaphore request register that stores data related to an authorization request, so that the data for acquiring the authorization (for example, a logical value '0) corresponds to each processor 400 and 404. To the semaphore request register.

When the data for acquiring the authority is stored in the semaphore request register, the semaphore processing unit 420 writes information on whether the shared memory area requested by the first processor is used in the semaphore register.

Here, when the shared memory area 426 is accessible, the logic value '1' may be stored when the logic value '0' is not accessible in the semaphore register.

According to an exemplary embodiment of the present invention, each of the first processor 400 and the second processor 404 connected to the individual ports 410 and 412 obtains the authority from the semaphore processing unit 420 through the command transfer processing unit 422. Commands can be passed to the other processor, whether or not.

The command may be task execution information for allowing one of the processors connected to the dual port memory 408 to access the shared memory area 426 to execute a predetermined task.

For example, when the first processor 400 is the main processor and the second processor 404 is the multimedia processor, the command transmitted by the first processor 400 to the second processor 404 may be requested by a user or in advance. It may be 'sound source reproduction execution information' according to the set algorithm.

According to the present invention, when the first or second processor 400 or 404 transmits a predetermined command to the counterpart processor, the processor to which the command is to be delivered includes the addresses ADD1 and ADD2 for direct command transfer, and the control signals CTR1, CTR2) and command data DQ1 and DQ2 are output.

In FIG. 4, the command to be transmitted is represented by a first command Command1 and a second command Command2, respectively, where the first command corresponds to a first data bus corresponding to a data transfer line of the first processor, and the second command corresponds to a second command. The data may be transferred to the counterpart processor through a second data bus corresponding to the data transfer line of the processor.

In this case, the command delivered by each processor may be stored in a preset register of the command transfer processor.

The address for direct command transfer is an address (address corresponding to a preset register) of the command transfer processor 422. In general, since the highest row address of the shared memory area 426 is assigned to the address of the semaphore processing unit 420, the address of the command transfer processing unit 422 is an upper row address (for example, the highest level) for the shared memory area 426. (The next bit of the row address).

However, the present invention is not limited thereto, and if the dual port memory 408 is distinguishable, the address of the command transfer processor 422 may be variously assigned.

The control signal for direct command transfer may include a control signal (eg, a write control signal, for activating the command transfer processor 422 and writing the output command data Command1 and CMD to the command transfer processor 422). / WE).

For example, when the first processor 400 transmits a predetermined command (first command) to the second processor 404, the first memory interface 414 decodes the received address and control signal and then delivers the command. The enable signal is output to the processor 422 so that the received first command is written to the command transfer processor 422.

At this time, since the decoded address is the address of the command transfer processor 422, the first memory interface 414 may prevent the semaphore processor 420 from acquiring the authority.

On the other hand, when the enable signal for writing the first command is received in the command transfer processor 422, the command transfer processor 422 may output an interrupt signal (first interrupt signal).

When the first interrupt signal is received, the second processor 404 recognizes that there is a command transfer from the first processor 400, and the address of the command transfer processor 422 through the second external bus interface 406. The control signal for reading the first command is output.

Accordingly, the second processor 404 reads the first command from the command transfer processor 422 and executes a job corresponding to the first command.

The same process may be applied to the case where the command is transmitted from the second processor 404 to the first processor 400.

According to the present invention, command transfer is efficiently performed since each processor 400, 404 does not need to acquire authority from the dual port memory 408 while transferring commands between the first processor 400 and the second processor 404. Do it.

Hereinafter, the command delivery processor 422 according to the present invention will be described in detail with reference to FIG. 5.

5 is a block diagram showing a detailed configuration of a command delivery processing unit according to an embodiment of the present invention.

As shown in FIG. 5, the command transfer processing unit according to the present invention includes a first command register 500, a second command register 502, a first buffer 504, a second buffer 506, and a third buffer ( 508 and a fourth buffer 510.

The first command output from the first processor 400 is written in the first command register 500.

The enable signal is input to the first command register 500 by the control signal CTR1 received by the first memory interface 414, whereby the first command is written to the first command register 500.

Meanwhile, the first interrupt signal Interrup1 may be generated according to the enable signal and output to the second processor 404.

The first command written in the first command register 500 is temporarily stored in the first buffer 504 corresponding to the second processor 404.

The second processor 404 receives the first interrupt signal when the first command is written in the first command register 500, and generates an address and a control signal of the command transfer processor 422 according to the first interrupt signal. The first command temporarily stored in the first buffer 504 may be read.

The second command output from the second processor 404 is written in the second command register 502.

As described above, the storing of the second command may be performed according to the enable signal, and when the second command is written in the second command register 502, the second interrupt signal according to the command transfer to the first processor 400 side. (Interrupt2) is output.

The second command is temporarily stored in the second buffer 506 corresponding to the first processor 400. The first processor 400 may read data temporarily stored in the second buffer 506 through the second interrupt signal.

After the second command is read, the first processor 400 requests an access right from the dual port memory 408 to execute the read second command, and when the access right is obtained, the first processor 400 dualizes the address and the control signal. Output to the port memory 408.

Meanwhile, the second processor 404 performs the same process as the first processor 400 after reading the first command temporarily stored in the first buffer 504.

According to the present invention, in order to transfer the first command of the first processor 400 and the second command of the second processor 404 to the counterpart processor, it is not necessary to acquire the authority from the dual port memory 408, thereby speeding up the command transfer. Can be done.

Meanwhile, according to an exemplary embodiment of the present invention, the command transfer processor 422 may include a third buffer 508 connected to the first command register 500 and a fourth buffer connected to the second command register 502. 510.

When the first command is written to the first command register 500 by the enable signal, the first command is temporarily stored in the third buffer 508.

When the first interrupt signal is received, the first processor 400 reads the first command from the third buffer 508.

On the other hand, when the second command is written in the second command register 502 by the enable signal, the second command is temporarily stored in the fourth buffer 510.

When the second interrupt signal is received, the second processor 404 reads the second command from the fourth buffer 510.

When one of the processors connected to the dual port memory 408 executes a predetermined task in a multi-task environment in which a plurality of tasks are executed, it is necessary to check the tasks processed in each task.

This means that the first task transfers a predetermined command to the second processor 404, and thus data corresponding to the command is written or read in the shared memory area, and the second task does not recognize the command transfer of the first task. This is because an error may occur when the second task performs the same operation on the same shared memory area.

According to the present invention, since the command transfer processing unit 422 transfers not only the command of the counterpart processor but also its own command, it is possible to prevent an operation error of each of the processors 400 and 404.

6 is a flowchart illustrating a command transfer process of a processor according to the present invention.

FIG. 6 illustrates a process in which the first processor 400 transmits a command to the second processor 404, receives a command from the second processor 404, and executes a predetermined task.

Referring to FIG. 6, when an event occurs in the first processor (step 600), it is determined whether a command (first command) corresponding to the event is a command to be transmitted to the second processor 404.

Here, the event may be an event for executing a specific task according to a user's request or a preset algorithm, and may be, for example, a sound source reproduction request signal. In addition, the command corresponding to the event may be corresponding task execution information, for example, sound source reproduction task information for sound source reproduction.

The first processor 400 determines whether the first command is a command to be transmitted to the second processor 404 (step 602).

In the case of a command to be delivered to the second processor 404, the first processor 400 extracts an address of the command delivery processor (step 604) and outputs an address, a control signal, and data for the first command delivery (step 604). Step 606).

As described above, the address may be an address of the command transfer processor 422, the control signal may be a signal for writing a first command to the command transfer processor 422, and the data may be a first command.

The first command may be directly transmitted to the second processor 404 through the address and control signal generated in operation 606.

On the other hand, when the first processor 400 receives the interrupt signal according to the transfer of the second command from the second processor 404 (step 608), the first processor 400 stops the previous operation (step 610), The task corresponding to the second command is executed (step 612).

7 is a flowchart illustrating a command delivery process and a command execution process of a processor in the command transfer processing unit according to the present invention, and illustrates a process in which the first processor 400 delivers a first command.

Referring to FIG. 7, when the first processor 400 outputs an address, a control signal, and data for delivering a first command, the command transfer processor 422 receives an enable signal from the first memory interface 414. (Step 700).

Upon receiving the enable signal, the command transfer processor 422 outputs an interrupt signal to the second processor 404 (step 702).

On the other hand, the first command is written to the first command register 500 in accordance with the above enable signal (step 704).

According to the present invention, the first command written in the first command register 500 is temporarily stored in the second buffer 506 corresponding to the second processor 404 (step 706), and at the same time the first processor 400 Is entered into a third buffer 508 (step 708).

Meanwhile, steps 710 to 716 are processes performed by the second processor 404. When the second processor 404 receives the interrupt signal, the second processor 404 reads the first command input to the second buffer 504. An address and a control signal for outputting are output (step 710).

The address for reading the first command may be an address of the command transfer processor 422, and the control signal is a control signal for reading the first command input to the second buffer 504.

Upon receiving the first command, the second processor 404 outputs an address, a control signal, and data for permission acquisition to the dual port memory 408 to execute the first command (step 712).

The address is an address corresponding to the semaphore processing unit 420 for accessing the shared memory area, and the control signal corresponds to a signal for writing or reading data for authority acquisition in the semaphore request register of the semaphore processing unit 420.

The second processor 404 determines whether the right is acquired through the information read from the semaphore register of the semaphore processing unit 420 (step 714), and if the right is obtained, accesses the shared memory area and executes the first command. (Step 716)

Preferred embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, and additions within the spirit and scope of the present invention. Additions should be considered to be within the scope of the following claims.

As described above, according to the present invention, a command can be transferred between processors connected to the dual port memory without obtaining a privilege, thereby reducing the dual port memory occupancy time of the processor.

In addition, according to the present invention, there is an advantage that can prevent the error of the job execution by re-checking the command transmitted to each processor by the processor.

Claims (18)

A memory array having a shared memory area; A first memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided through a first port from a first processor; A second memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided from a second processor through a second port; A semaphore processor configured to control access rights to the shared memory areas of the first processor and the second processor; And And one or more command registers to which the commands transmitted from the first processor or the second processor are written, and a buffer for temporarily storing the commands so that the corresponding processors can read the command processor. Dual port memory, characterized in that it comprises a. The method of claim 1, And the command transfer processor directly transfers a command transmitted through a first data bus of one of the first processor and the second processor through a second data bus of the counterpart processor. The method of claim 1, And the command is job execution information for causing the counterpart processor to access the shared memory area to execute a predetermined job. The method of claim 1, And the address of the command transfer processing unit is allocated to an upper row address for the shared memory area. delete The method of claim 1, The command register may include a first command register to which a command output from the first processor is written; And And a second command register to which a command output from the second processor is written. The method of claim 1, And the command is written to the command register in response to an enable signal output from either the first or second memory interface corresponding to the processor. The method of claim 7, wherein And the command transfer processor outputs an interrupt signal to the counter processor when the enable signal is received. The method of claim 8, And the counter processor reads a command stored in the command transfer processor when the interrupt signal is received. The method of claim 1, The command delivery processing unit, And a buffer for temporarily storing the command so that the processor can read the command transmitted to the counterpart processor. The method of claim 1, The processor that delivers the command determines whether a command corresponding to the event generation is a command to be transmitted to the counterpart processor when an event occurs. The method of claim 11, And the processor for transmitting the command outputs an address of the command transfer processing unit and a control signal for writing the command to the command transfer processing unit to a corresponding first or second memory interface. delete A first processor; A second processor; And A memory array having a shared memory area, a first memory interface configured to perform a write or read operation on the shared memory area based on an address and a control signal provided through a first port from a first processor, and a second memory from a second processor; A second memory interface configured to perform a write or read operation to the shared memory area based on an address and a control signal provided through a second port, and to control access rights of the first processor and the second processor to the shared memory area; And a semaphore processing unit, one or more command registers to which the commands transmitted from the first processor or the second processor are written, and a buffer for temporarily storing the commands so that the corresponding processors can read them. Include command delivery processing for Dual-port memory system, characterized in that the. A method for processing command transfer between a first processor and a second processor in a dual port memory, the method comprising: (a) receiving a first control signal and command data for direct command transfer from the first processor; (b) decoding the first control signal and writing the command data to a preset register in the dual port memory; (c) outputting an interrupt signal according to the writing of the command data to the second processor; (d) temporarily storing a command stored in the preset register in a buffer corresponding to the second processor; And and (e) transferring the command data to the second processor in accordance with a second control signal of the second processor receiving the interrupt signal. The method of claim 15, And the step (a) receives an address corresponding to the preset register from the first processor. delete The method of claim 15, Temporarily storing a command stored in the preset register in a buffer corresponding to the first processor; And And transmitting the command data to the first processor according to a third control signal of the first processor.

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