KR101103619B1 - Multi-port memory system and access control method thereof - Google Patents

Abstract

A multi-port memory and its access control method are disclosed. The multi-port memory device includes a first data transfer block allocated such that a first device has only data write authority and a second device has only data read authority, and the second device has only data write authority and the first device reads data. A storage area including a second data transfer block allocated to have rights only; And a memory controller managing access state information of the first and second devices with respect to the first and second data transfer blocks. According to the present invention, it is possible to maximize the efficiency of the memory shared by a plurality of devices, and to minimize the data transfer time between each device.

Memory, share, port

Description

Multi-port memory system and access control method

The present invention relates to a memory, and more particularly to a multi-port memory and its access control method.

Recently, portable terminals such as mobile communication terminals and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video phones, and playback of multimedia data in addition to mobile communication functions such as voice calls.

The portable terminal is provided with a baseband processor for processing essential functions such as a mobile communication function and an application processor for processing various applications.

In general, in a portable terminal having two or more processors, dual port memory is used to improve the processing speed of the system and to reduce the mounting area of the memory system by performing data transmission and reception between the processors at a high speed.

In other words, when two processors use dual port memory, each processor uses each port to access and read data from and write data to the memory area, so the two processors are connected to different memory to send and receive data. The transfer and processing speeds are fast and this improves the overall performance of the system.

1 is a diagram illustrating a memory area of a dual port memory according to the related art.

Referring to FIG. 1, two processors are respectively connected to a first port of a dual port memory 10 to access a memory area, and a second processor connected to a second port to access a memory area. Shown at 30.

The memory area of the dual port memory 10 is a dedicated memory area in which the first processor 20 and the second processor 30 independently access each other to perform a read or write operation (that is, access only to the first processor 20). The first processor-only area 14 and the second processor-only area 16 to which only the second processor 30 is allowed to access, and the first processor 20 and the second processor 30 approach each other. It includes a shared memory area 12 that performs a read or write operation.

This dual port memory 10 may use hardware semaphores (not shown) to ensure mutually exclusive access of each device to the shared memory area 12 and to ensure synchronized operation between each device. .

As described above, the dedicated memory area among the memory areas of the dual port memory 10 is an area allocated only to a specific processor and cannot be shared among a plurality of memories, and the shared memory area 12 may be shared by a plurality of processors. It cannot be accessed at the same time.

Therefore, while one processor accesses the shared memory area 12, the other processor cannot access the shared memory area 12.

As a result, when one processor occupies the shared memory area 12 for read or write operations, another processor cannot access the area and perform read or write operations. It takes a lot of time and memory utilization is inefficient.

The background art described above is technical information possessed by the inventors for the derivation of the present invention or acquired during the derivation process of the present invention, and is not necessarily a publicly known technique disclosed to the general public before the application of the present invention.

The present invention is to provide a multi-port memory and its access control method to maximize the efficiency of the memory shared by a plurality of devices, and to minimize the data transfer time between each device.

The present invention divides a shared memory area shared by a plurality of devices into a plurality of blocks, and sets a processing permission operation of each device for each block, thereby maximizing the efficiency of the shared memory area and access control thereof. It is to provide a method.

The present invention is to provide a multi-port memory and its access control method by dividing the shared memory area into a plurality of blocks, thereby ensuring effective access to the shared memory area between devices.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a memory device shared by a first device and a second device, wherein the first data transfer is allocated such that the first device has only data write authority and the second device has only data read authority. A storage area including a block and a second data transfer block allocated such that the second device has only data write rights and the first device has only data read rights; And a memory controller managing access state information of the first and second devices with respect to the first and second data transfer blocks.

The storage area may further include one or more shared blocks allocated separately to the first and second data transfer blocks so that the first and second devices may be individually connected for a time that does not overlap.

The memory device may further include a semaphore manager having a hardware semaphore cell for notifying information about whether any device has access to the shared block.

The storage area may further include one or more dedicated areas each allocated to allow connection of only a preset device.

The first and second devices may each be any one of a baseband chip, an application processor chip, and a display device.

The memory device may be a DRAM or SDRAM dual port memory. The storage area may have a DRAM cell structure.

According to another aspect of the invention, a digital processing apparatus, comprising: a first device; A second device; And a shared memory connected with a first device through a first port, and connected with a second device through a second port, wherein the shared memory is configured such that the second device has only data writing authority. A storage area including a first data transfer block allocated only to have data read rights and a second data transfer block allocated so that the second device has only data read rights and the first device has only data read rights; And a memory controller managing access state information of the first and second devices with respect to the first and second data transfer blocks.

The storage area may further include one or more shared blocks allocated separately to the first and second data transfer blocks so that the first and second devices may be individually connected for a time that does not overlap.

The shared memory may further include a semaphore manager having a hardware semaphore cell to inform information about whether any device has access to the shared block.

The storage area may further include one or more dedicated areas each allocated to allow connection of only a preset device.

The first and second devices may each be any one of a baseband chip, an application processor chip, and a display device.

The memory device may be a DRAM or SDRAM dual port memory. The storage area may have a DRAM cell structure.

According to yet another aspect of the present invention, an access control method for a plurality of processors of a memory device, the method comprising: receiving an access request for a first data transfer block from a first device; Determining whether access to the first data transfer block is possible; And transmitting information on whether to allow access according to the determination to the first device, wherein the storage area of the memory device includes only the data writing authority of the first device and only the data reading authority of the second device. The first data transfer block allocated to have a second data transfer block allocated to have the data read right only and the first device have only data read right. And / or a recording medium having recorded thereon a program for executing the method.

The storage area may further include one or more shared blocks allocated separately to the first and second data transfer blocks so that the first and second devices may be individually connected for a time that does not overlap.

A hardware semaphore cell may be used to inform information about whether any device has access to the shared block.

Other aspects, features, and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, there is an effect of maximizing the efficiency of the memory shared by a plurality of devices, and to minimize the data transfer time between each device.

In addition, there is an effect of maximizing the efficiency of the shared memory area by dividing the shared memory area shared by the plurality of devices into a plurality of blocks and setting the processing permission operation of each device for each block.

In addition, by dividing the shared memory area into a plurality of blocks, effective access to the shared memory area between devices can be ensured.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described on the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In addition, the terms “… unit”, “… unit”, “module”, etc. that may be described in the specification mean a unit for processing at least one function or operation, which is hardware or software or a combination of hardware and software. Can be implemented.

In the present specification, the multi-port memory is a memory having two or more port interface units, which can be operated by being coupled to two or more devices. However, in the present specification, as an embodiment of the multi-port memory, a case of the dual-port memory having two memory interface units will be described. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram schematically illustrating a configuration of a dual port memory according to an embodiment of the present invention, and FIG. 3 is a diagram illustrating a divided form of a shared memory area according to an embodiment of the present invention.

Referring to FIG. 2, the dual port memory 100 may include a first memory interface unit 110, a first device dedicated region 120, a second memory interface unit 130, a second device dedicated region 140, and a memory. The controller 150 includes, but is not limited to, a semaphore manager 160 and a shared memory area 180. Each device connected to the dual port memory 100 through each port may be, for example, one or more of a baseband chip, an application processor chip, and a display device.

The first memory interface unit 110 allows the first device 102 to be connected to the dual port memory 100, and the first device 102 connected through the first port may be the first device-only area 120 or /. And an interface for accessing the shared memory area 180. The first memory interface unit 110 receives one or more of an address ADD1, a control signal CTR1, a clock CLK1, data DQ1, and the like from the first device 102, and writes / reads and refreshes ( Input / output of data with a memory array (not shown) may be performed according to an operation timing such as refresh. The first memory interface unit 110 may include, for example, one or more of a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

The first device dedicated area 120 is a storage area configured to be dedicated only to the first device 102 connected through the first port. Data to be written or read by the first device 102 may be stored in the first device-only area 120.

The second memory interface unit 130 allows the second device 104 to be connected to the dual port memory 100, and the second device 104 connected through the second port may be the second device-only area 140 or /. And an interface for accessing the shared memory area 180. The second memory interface unit 130 receives one or more of an address ADD2, a control signal CTR2, a clock CLK2, and data DQ2 from the second device 104, and writes / reads and refreshes the data. Input / output of data with a memory array (not shown) may be performed according to an operation timing such as refresh. The second memory interface unit 130 may include, for example, one or more of a command decoder, a row decoder, a column decoder, an input / output buffer, and the like.

The second device dedicated area 140 is a storage area configured to be dedicated only to the second device 104 connected through the second port. Data to be written or read by the second device 104 may be stored in the second device-only area 140.

Through this, the dual port memory 100 in which the first device 102 and the second device 104 are combined may be a general host processor interface, a serial / parallel interface, or an I2C. Data can be input and output faster than the interface.

The memory controller 150 manages which device has access to any block in the shared memory area 180 and which processing is performed. The memory controller 150 performs a control function for allowing each device to perform access and processing without managing semaphores for the data transfer blocks 310 and 320 to be described later. In order to enable each device to access the data transfer blocks 310 and 320 without a semaphore, the memory controller 150 may perform status information on the data transfer blocks 310 and 320, for example, whether or not the access operation is performed. You can manage pointer information to manage one or more of the types, and so on. For example, the memory controller 150 may provide the status information to any device attempting to access the data, or if the device attempts to access the data when the status information is written in the form of data, the memory controller 150 may read the status information to read any data transfer block. Make sure that is accessible.

The semaphore manager 160 is connected to the first memory interface unit 110, the second memory interface unit 130, the first device 102, and the second device 104 to share a shared block of the shared memory area 180. By notifying the first device 100 and the second device 104 when the contents of the access rights of the fields 330 and 340 are changed, the shared blocks 330 and 340 are not conflicted with the first device 102. And allow the second device 104 to access it. As the notification method, for example, an interrupt signal or a ready or busy signal may be used.

The shared memory area 180 is a storage area shared between each device connected to the dual port memory 100. The shared memory area 180 may be partitioned including, for example, one or more of a data transfer block set for data transfer between devices, a shared block for free sharing of devices, and the like.

3 illustrates a divided form of a shared memory area according to an embodiment of the present invention.

In FIG. 3, two data transfer blocks and two shared blocks are illustrated. However, the number of blocks according to each use may be variously changed according to the purpose. For example, the shared memory area 180 may be set to only one of the data transfer block and the shared block. In addition, the dual port memory 100 may be set to the shared memory area 180 only. In addition, the plurality of dual port memories may be embodied as one shared memory shared by each device.

Referring to FIG. 3, the shared memory area 180 includes two data transfer blocks 310 and 320 and two shared blocks 330 and 340.

The two data transfer blocks 310 and 320 are set to block 12 310 in which the second device 104 accesses and reads data when the first device 102 accesses and writes data. And block 21 (320) configured to access and read data when the second device 104 accesses and writes data. That is, for block 12 310, the first device 102 has only data write rights, and the second device 104 has only data read rights. In contrast, for block 21 320, the first device 102 has only data read rights, and the first device 102 has only data write rights.

When the first device 102 and the second device 104 access a data transfer block for writing or reading data, the first device 102 and the second device 104 provide information about the block to be accessed to the dual port memory 100. In this case, the memory controller 150 of the dual port memory 100 determines that the device is accessible to the access request block as state information for managing whether the device is accessible, and then provides information on whether the device can be accessed by the device. Allows access or standby.

For example, while the first device 102 has written data for block 12 310 but the second device 104 has not yet read, the first device 102 has written new data already. In the case of an access attempt to change to data, the memory controller 150 may disallow access of the first device 102. In another case, if the access request for the second device 104 to read the data is received while the first device 102 accesses the block 12 310 and writes the data, then the memory controller 150 generates the second controller. If the request of device 104 is a request for an area in which first device 102 has already written data, it may allow access of the second device.

Meanwhile, the state information managed by the memory controller 150 may be recorded and managed in a data form in an arbitrary storage area, and any device that attempts to access reads the state information recorded in the corresponding area and transfers arbitrary data. You can also check that the block is accessible. In this case, the memory controller 150 may not need to provide status information to the device as a separate procedure.

In addition, each of the two shared blocks 330 and 340 included in the shared memory area 180, that is, the block A 330 and the block B 340, is free to each device according to the information managed by the semaphore manager 160. It is an area that can be accessed to perform data recording and / or reading.

The semaphore manager 160 may be composed of one or more hardware semaphore cells, and one or more hardware semaphore cells may exist for each shared block 330 and 340. As illustrated in FIG. 3, when the shared block consists of two or more blocks (or banks), the semaphore manager 160 may consist of two or more hardware semaphore cells.

A semaphore is usually a technique for coordinating or synchronizing behavior in multiple processes that competitively use operating system resources. Each semaphore is a value within a specified storage of the operating system or kernel. You can change it. Depending on the value of the semaphore that is identified, if the process finds that the resource is immediately available or already in use by another process, it must wait some time before retrying. Semaphores use binary numbers (0 or 1), or may have additional values. The semaphore cell for applying the semaphore or semaphore technology is obvious to those skilled in the art, and thus a detailed description thereof will be omitted.

If the first device 102 occupies a hardware semaphore for any one of the shared blocks 330, 340, the second device 104 enters an access wait state for the block, and the first device ( When 102 releases the hardware semaphore, the second device 104 may access two resources exclusively from one resource (ie, a shared area) in such a manner that an access wait state for the corresponding block is released.

Referring to the shared block access process by the semaphore manager 160 as follows.

When the first device 102 or the second device 104 wants to access a shared block, data is read from the semaphore manager 160. At this time, it may be known whether the shared block is accessible depending on whether the read data value is 0 or 1. That is, if 0, the shared block is recognized as being accessible, and if 1, the shared block is recognized as being occupied by another device. When the first device finishes accessing the shared block, it immediately writes data 0 (Zero) to the semaphore manager so that the second device can directly access it. While the first device 102 occupies a hardware semaphore, the second device 104 is in a state of waiting for access to the shared block, so that another data processing operation such as using the second device-only area 140 is performed. Can be done.

After the first device 102 or the second device 104 has finished accessing the shared block, the two devices can access the shared block exclusively by writing data one (one) to the semaphore manager 160. Make sure

4 is a flowchart illustrating an access control method for a shared memory area according to an embodiment of the present invention.

Referring to FIG. 4, in step 410, the device attempts to access any storage area for data writing or reading.

In operation 420, the device determines whether access to the storage area to be accessed is possible.

If the device attempts to access the data transfer block of the shared memory area 180, the device receives information on accessibility from the memory controller 150 or refers to the state information stored in an arbitrary area to the corresponding area. It is possible to determine immediately whether or not access is possible.

In addition, if the corresponding device intends to access the shared block of the shared memory area 180, it may be determined whether access to the corresponding area is possible by referring to the hardware semaphore managed by the semaphore manager 160.

If access to the storage area is possible, the device performs an operation to access and process the storage area in step 430. The operation to be processed may be, for example, one or more of data recording, data reading, and the like.

However, if access to the storage area is not available, the device remains idle until access is possible. Of course, at this time, the device may perform an operation using a dedicated area of the dual port memory 100 or perform other necessary operations.

It is apparent that the above-described access control method of the multi-port memory may be performed by an automated procedure according to a time series sequence by a software program or the like embedded in the digital processing apparatus. The codes and code segments that make up the program can be easily deduced by a computer programmer in the field. The program is also stored in a computer readable media that can be read by a digital processing device, and read and executed by the digital processing device to implement the method. The information storage medium includes a magnetic recording medium, an optical recording medium, and a carrier wave medium.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

1 shows a memory region of a dual port memory according to the prior art;

2 is a diagram schematically illustrating a configuration of a dual port memory according to an embodiment of the present invention.

3 illustrates a partitioned form of a shared memory area according to an embodiment of the present invention.

4 is a flowchart illustrating an access control method for a shared memory area according to an embodiment of the present invention.

Claims (18)

A memory device shared by a first device and a second device, the A first dedicated storage area dedicated by the first device, a second dedicated storage area dedicated by the second device, and a data transfer block and a shared block shared by the first device and the second device; A storage area consisting of a shared storage area; And A memory controller managing access state information of the first and second devices for the data transfer block; The data transfer block may include a first data transfer block allocated such that the first device has only data write authority and the second device has only data read authority, and the second device has only data write authority. A second data delivery block allocated to have only data read rights, If a device with data write authority for any data transfer block has written data, but a device with data read authority for the data transfer block has not yet read the recorded data, the device with data write authority has new data. The memory controller does not allow the connection of the device when attempting to connect to the corresponding data transfer block to write the data. The method of claim 1, And the shared block is a storage area allocated to be individually accessible for a time when the first and second devices do not overlap. 3. The method of claim 2, And a semaphore manager having a hardware semaphore cell for notifying information on whether any device has access to the shared block. The method of claim 1, The memory controller writes data when a device having a data read right for a data transfer block requests a connection while a device having a data write right for a data transfer block requests a connection. And a device having a data read right only in the case of a connection request for data read of the area where the data is read. The method of claim 1, And the first and second devices are any one of a baseband chip, an application processor chip, and a display device. The method of claim 1, And the memory device is DRAM or SDRAM dual port memory. The method of claim 1, And the storage area has a DRAM cell structure. In the digital processing device, A first device; A second device; And A shared memory connected with the first device through the first port and connected with the second device through the second port, The shared memory, A first dedicated storage area dedicated by the first device, a second dedicated storage area dedicated by the second device, and a data transfer block and a shared block shared by the first device and the second device; A storage area consisting of a shared storage area; And A memory controller managing access state information of the first and second devices for the data transfer block; The data transfer block may include a first data transfer block allocated such that the first device has only data write authority and the second device has only data read authority, and the second device has only data write authority. A second data delivery block allocated to have only data read rights, If a device with data write authority for any data transfer block has written data, but a device with data read authority for the data transfer block has not yet read the recorded data, the device with data write authority has new data. And the memory controller does not allow the connection of the device when attempting to connect to the corresponding data transfer block to record the data. The method of claim 8, And wherein the shared block is a storage area allocated to be individually accessible for a time when the first and second devices do not overlap. 10. The method of claim 9, The shared memory further comprises a semaphore manager having a hardware semaphore cell for notifying information on whether any device has access to the shared block. The method of claim 8, The memory controller writes data when a device having a data read right for a data transfer block requests a connection while a device having a data write right for a data transfer block requests a connection. And a device having a data reading authority only in the case of a connection request for data reading of a region of which the data has been completed. The method of claim 8, And the first and second devices are any one of a baseband chip, an application processor chip, and a display device. The method of claim 8, And the shared memory is SDRAM or DRAM dual port memory. The method of claim 8, And said storage region has a DRAM cell structure. An access control method for a plurality of processors of a memory device, Receiving an access request for a first data transfer block from a first device; Determining whether access to the first data transfer block is possible; And And transmitting information on whether to allow access to the first device according to the determination. The memory device, A first dedicated storage area dedicated by the first device, a second dedicated storage area dedicated by a second device, and shared by the first device and the second device and including a data transfer block and a shared block. A storage area consisting of a shared storage area; And A memory controller managing access state information of the first and second devices for the data transfer block; The data transfer block includes the first data transfer block assigned such that the first device has only data write authority and the second device has only data read authority, and the second device has only data write authority. Includes a second data delivery block allocated to have only data read rights, If a device with data write authority for any data transfer block has written data, but a device with data read authority for the data transfer block has not yet read the recorded data, the device with data write authority has new data. The memory controller does not allow the connection of the device when attempting to access the corresponding data transfer block to write the data. The method of claim 15, And wherein the shared block is a storage area allocated to be individually accessible for a time when the first and second devices do not overlap. The method of claim 16, And a hardware semaphore cell is used to notify information on whether any device has access to the shared block. A recording medium on which a program of instructions that can be executed by a memory device is tangibly implemented to perform the access control method according to any one of claims 15 to 17, and records a program that can be read by the memory device.

Images