KR100816038B1 - Method for accessing shared memory in multi-processor system - Google Patents

Abstract

A method for accessing a shared memory in a multi-processor system is provided to increase processing performance of the multi-processor system without additional hardware by reducing access delay to a first processor having lower processing performance and a bigger data processing unit than a second processor. A second processor accesses a shared memory area in a predetermined access time, which is the time dividing a shared memory area accessing time of the second memory by a predetermined time gap(305). The second processor waits to access to the shared memory area for a predetermined waiting time after the access time is terminated(311). A first processor accesses the shared memory area in the waiting time. The second processor accesses the shared memory area by repeating stages for accessing the shared memory area in the predetermined access time and waiting the access to the shared memory area in the predetermined waiting time after the access time is terminated.

Description

Method for Accessing Shared Memory in Multi-Processor System

1 is a conceptual diagram illustrating a method in which two processors access a shared memory area in a general multiprocessor system.

2 is a block diagram illustrating a configuration of a multiprocessor system according to an exemplary embodiment of the present invention.

3 is a conceptual diagram illustrating a method of accessing a shared memory area by two processors in a multiprocessor system according to an embodiment of the present invention.

4 is a flowchart illustrating a method of accessing a shared memory area of a second processor in a multiprocessor system according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: first processor 120: second processor

130: first external bus interface 140: second external bus interface

200: dual port memory 210: memory cell array

220: access control unit 230: first memory interface

240: second memory interface

The present invention relates to a multiprocessor system, and more particularly, to a shared memory access method of a multiprocessor system applicable to a portable terminal having at least one processor.

Recently, portable terminals such as mobile phones and PDAs (Personal Digital Assistants) include various additional functions such as digital cameras, video communications, and multimedia data playback in addition to wireless communication functions such as voice calls.

A portable terminal is a multiprocessor system having a plurality of processors, such as a main processor for processing the original functions of mobile communication, such as a modem processor and a baseband processor, and an additional processor for processing an application program by a multimedia function or instructions of the main processor. It consists of.

In addition, in general, in a portable terminal having the multiprocessor system, dual port memory is used to perform data transmission and reception between two processors at high speed and to reduce a mounting area of the memory.

In other words, when two processors use dual-port memory, each processor can access its memory area using its own port to read and write data, so that the two processors are connected to different memory to interface between host processors. Data transfer and processing is faster than processing data sent and received via Host Porcessor Interface (HPI), which improves the overall performance of the system.

The dual port memory includes a dedicated memory area in which two processors independently perform read or write operations, and a shared memory area in which two processors collectively access a read or write operation.

In a multiprocessor system with dual-port memory, if each processor accesses the same shared memory area through its port at the same time, a conflict will occur and both processors will not be able to access the memory, resulting in poor overall system performance. There is a problem.

In addition, if one processor of the two processors accesses the shared memory area and reads or writes the data while another processor accesses the same shared memory area and writes the data, the data stored in the memory area becomes inaccurate. Or there is a problem that an error may occur in the processing result.

Accordingly, in order to solve the above problems, a multiprocessor system needs a method and apparatus for controlling mutual exclusive access of each processor to a shared memory area.

1 is a conceptual diagram illustrating a method in which two processors access a shared memory area in a general multiprocessor system.

Referring to FIG. 1, the second processor starts an access to a predetermined shared memory area at time t0 to read or write data. At time t0, access to the predetermined shared memory area is locked in hardware to prevent access to the first processor.

The first processor attempts to access the predetermined shared memory area at time t1. However, since the second processor has already accessed the predetermined shared memory area and the access to the predetermined shared memory area is locked, the first processor is not granted access to the predetermined shared memory area at time t1. It remains in an idle state until it is accessible.

Thereafter, when the second processor terminates the access to the predetermined shared memory area at time t2 and the access state to the predetermined shared memory area is unlocked, the first processor is in the waiting state for accessing the predetermined share. Access to memory is performed to read or write data.

At this time, the access to the predetermined shared memory area accessed by the first processor is locked, and the second processor cannot access the predetermined shared memory area.

In the multi-processor system shown in FIG. 1, the total access latency time of the second processor is from time t0 to t2, and the total access delay time of the first processor is time t1 at time t1 when the first processor attempts access for the first time. It becomes until.

The shared memory access method of the general multiprocessor system shown in FIG. 1 ensures mutually exclusive access of a first processor and a second processor to a predetermined shared memory area, and the first processor and the second processor provide a predetermined shared memory. By trying to access the domain fairly, it is possible to prevent any processor from starvation.

However, in the shared memory access method of the general multiprocessor system illustrated in FIG. 1, it is assumed that a first processor is a main processor provided in a portable terminal, and a second processor is an additional processor for processing an application or a multimedia function in the portable terminal. Since the main processor has a large unit of data that accesses the shared memory area and performs operations such as reading or writing, and the processing power of the processor itself is inferior to that of the additional processor, the first processor as shown in FIG. The longer the access delay time of the main processor, the lower the processing performance of the overall multiprocessor system.

Accordingly, an object of the present invention is to provide a shared memory access method of a multiprocessor system capable of improving processing performance of a multiprocessor system without additional hardware.

Shared memory access method of a multi-processor system according to an aspect of the present invention for achieving the above object of the present invention is a shared memory access control method of a multi-processor system including a first processor, a second processor, a shared memory and an access controller The method of claim 1, wherein the second processor accesses the shared memory area for a preset access time, and the second processor waits for access to the shared memory area for a preset waiting time after the access time ends. And accessing the shared memory at the waiting time by the first processor, wherein the second processor accesses the shared memory area for the preset access time and after the access time is over. Wait for access to the shared memory area for a preset waiting time. Repeat steps to perform access to the shared memory. The access time may be obtained by dividing a time when the second processor accesses the shared memory at predetermined time intervals. The accessing of the shared memory area by the second processor for a preset access time may include: requesting the second processor to access the shared memory area, and accessing the shared memory area by the second processor; The method may further include determining whether to allow. Requesting Access to the Shared Memory Region The second processor may request access to the shared memory region by transmitting an access request signal having a first logic value to the access controller. In the determining of whether to allow access to the shared memory area, the second processor may determine whether to allow access to the shared memory area by determining a logic value of an access permission signal provided from the access controller. Waiting for the second processor to access the shared memory area for a preset waiting time after the access time ends, determining whether the access time ends, and when the access time ends, The second processor may include notifying the end of the access time, and the second processor waiting for access to the shared memory area for a preset waiting time. In the notifying of the end of the access time, the second processor may notify the end of the access time by transmitting a second logic value to the access controller. In the shared memory access method of the multi-processor system, when the first processor is approaching the shared memory area after the preset waiting time ends, the access is performed during the access time after the access of the first processor is terminated. The method may further include accessing the memory. The first processor may be a main processor of the portable terminal, and the second processor may be an additional processor of the portable terminal.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for similar elements.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. The term and / or includes a combination of a plurality of related items or any item of a plurality of related items.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

In describing the drawings, similar reference numerals are used for similar components.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

2 is a block diagram illustrating a configuration of a multiprocessor system according to an exemplary embodiment of the present invention.

2, a multiprocessor system according to an embodiment of the present invention may include a first processor 110, a second processor 120, a first external bus interface 130 (EBI), and a second processor. The external bus interface 140 and the dual port memory 200 are configured.

The dual port memory 200 may include a memory cell array 210, an access controller 220, a first memory interface 230, and a second memory interface 240, and the memory cell array 210 may include a first memory cell array 210. A dedicated memory area 211, a second dedicated memory area 213, a third dedicated memory area 215, and a plurality of shared memory areas 217 are included.

The first processor 110 may be a main processor for processing a mobile communication original function such as a voice call in a portable terminal such as a mobile phone, and the second processor 120 may be an application by a command of the main processor in the portable terminal. It may be an additional processor for executing a program or processing a multimedia function. The main processor may be a modem processor or a baseband processor.

The first external bus interface 130 and the second external bus interface 140 serve as a kind of memory controller, and an external bus interface of a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) may be used. Hereinafter, in an embodiment of the present invention, it is assumed that the first external bus interface 130 and the second external bus interface 140 are SDRAM external bus interfaces.

The dual port memory 200 is connected to the first processor 110 having the first external bus interface 130 through the first port 250, and the second external bus interface 140 through the second port 260. It is connected to the second processor 120 having a).

The first processor 110 provides the address ADD1, the plurality of control signals CTR1, and the clock CLK1 to the dual port memory 200 through the first port 250 of the dual port memory 200. The dual port memory 200 performs input / output of the first processor 110 and the data DQ1 using the first port 250 and the first external bus interface 130.

In addition, the second processor 120 transmits the address ADD2, the plurality of control signals CTR2, and the clock CLK2 to the dual port memory 200 through the second port 260 of the dual port memory 200. The dual port memory 200 performs input / output of the second processor 120 and the data DQ2 using the second port 260 and the second external bus interface 140.

The memory cell array 210 has a unit memory cell structure of a DRAM and includes first to third dedicated memory areas 211 to 215 and a plurality of shared memory areas 217. The first dedicated memory area 211 may be a dedicated memory area of the first processor 110 to which the first processor 110 independently accesses to perform a read or write operation, and the second and third dedicated memory areas. Reference numerals 213 and 215 may be dedicated memory regions of the second processor 120 to which the second processor 120 independently accesses and performs a read or write operation. Each of the first to third dedicated memory areas 211 to 215 may be formed in a bank unit having a predetermined size.

The plurality of shared memory regions 217 may be formed in a bank unit having a predetermined size, and the plurality of shared memory regions 217 may be formed in a block unit having a predetermined size in one bank. It may be. In FIG. 2, the plurality of shared memory areas 217 is illustrated as including four shared memory areas.

The first memory interface 230 is configured as an SDRAM memory interface, and includes an address ADD1, a control signal CTR1, a clock CLK1, and data DQ1 from the first processor 110 through the first port 250. , Decodes the address ADD1 into a row address and a column address, and outputs the decoded address I_AD1 to the memory cell array 210 and at an operation timing such as reading, writing, and refreshing the memory cell array 210. Accordingly, the data I_DQ1 is read from the memory cell array 210 or written to the memory cell array 210.

To this end, the first memory interface 230 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and input / output used in a general SDRAM interface. And a buffer (not shown).

The second memory interface 240 is configured as an SDRAM memory interface, and has an address ADD2, a control signal CTR2, a clock CLK2, and data DQ2 from the second processor 120 through the second port 260. , ADD2 is decoded into a row address and a column address, and the decoded address I_AD2 is output to the memory cell array 210 and the operation timing of reading, writing, and refreshing the memory cell array 210 is performed. Accordingly, the data I_DQ2 is read from the memory cell array 210 or written to the memory cell array 210.

To this end, the second memory interface 240 may include a command decoder (not shown), a row decoder (not shown), a column decoder (not shown), and an input / output buffer (not shown) used in a general SDRAM interface. .

The access controller 220 guarantees mutually exclusive access of the first processor 110 and the second processor 120 to each of the plurality of shared memory regions 217.

That is, the access request signal SEM for each of the predetermined shared memory areas is input from the first processor 110 and the second processor 120 through the first memory interface 230 and the second memory interface 240, respectively. The first processor for each of the predetermined shared memory areas by providing an access permission signal READY to the first processor 110 and the second processor 120 according to the current access state of the requested shared memory area. The mutually exclusive access of the 110 and the second processor 120 is guaranteed. Here, the first processor 110 transmits an access request signal SEM through the first memory interface 230 and the second processor 120. ) Transmits an access request signal SEM through the second memory interface 240.

The access request signal SEM may have a logic value of '0' or '1', and when the first processor 110 and the second processor 120 request access to a predetermined shared memory area, the access request The signal SEM may be a logic value '0', and when the first processor 110 and the second processor 120 finish the operation in a predetermined shared memory area, the access request signal SEM may be a logic value '. Can be 1 '.

In addition, in another embodiment of the present invention, when the first processor 110 and the second processor 120 makes an access request for a predetermined shared memory area, the access request signal SEM becomes a logic value '1'. When the first processor 110 and the second processor 120 finish the work in the predetermined shared memory area, the access request signal SEM may configure the access request signal SEM such that the access request signal SEM becomes a logic value '0'. have.

The access controller 220 receives a logic value '0' from the first processor 110 and the second processor 120 when requesting access to a predetermined shared memory area, and applies the current value to the current access state of the requested shared memory area. Therefore, if the access is possible, the logic value '0' is output as the access permission signal READY, and if the access is not possible, the logic value '1' is output as the access permission signal READY.

3 is a conceptual diagram illustrating a method in which two processors access a shared memory area in a multiprocessor system according to an embodiment of the present invention.

Referring to FIG. 3, the second processor 120 starts an access to a predetermined shared memory area at time t0 to read or write data. When the second processor 120 accesses the predetermined shared memory area at time t0, the predetermined shared memory area is locked and the first processor 110 may not be accessible.

Then, at time t1, the second processor 120 temporarily terminates access to the predetermined shared memory area and the predetermined shared memory area is unlocked. In addition, the second processor 120 maintains the standby state until the time t2, thereby providing a time for the first processor 110 to access the predetermined shared memory area.

Since the first processor 110 did not attempt to access the predetermined shared memory area between the times t1 and t2, the second processor 120 attempts to access the predetermined shared memory area again at a time t2. Continue reading or writing.

While the second processor 120 is accessing a predetermined shared memory area and performing a task, the first processor 110 attempts to access the predetermined shared memory area at time t3. However, since the second processor 120 has already accessed the predetermined shared memory area and the access to the predetermined shared memory area has been locked, the first processor 110 has the predetermined shared memory area at time t3. You are not granted access to, and are in an idle state until you have access.

Thereafter, when the second processor 120 temporarily terminates the access to the predetermined shared memory area at time t4, and the access to the predetermined shared memory area is unlocked, the first processor ( 110 performs an access to the predetermined shared memory to read or write data.

In this case, the predetermined shared memory area is locked because the first processor 110 has approached, and thus the second processor 120 cannot access the predetermined shared memory area.

When the first processor 110 terminates the access to the predetermined shared memory area at time t5, the predetermined shared memory area is unlocked so that the second processor 120 approaches and performs a task at time t6. After the operation is temporarily terminated, the first processor 110 is accessible by unlocking the access to the predetermined shared memory area and maintaining the access wait state until the time t7. Then, at time t7, the predetermined shared memory area is accessed to perform a task, and at time t8, the access to the predetermined shared memory area is terminated.

In the shared memory access method of the multi-processor system shown in FIG. 3, the total access delay time of the first processor 110 is from t3 to t5, where the first processor 110 waits for access. The time is from t3 to t4. In addition, the total access delay time of the second processor 120 is from t0 to t8.

As shown in FIG. 3, in the shared memory access method of the multi-processor system according to an exemplary embodiment of the present invention, the first processor 110, that is, the second processor 120, that is, the additional processor having better processing performance than the main processor, may be used. By dividing the access time for the shared memory area into small time units having a predetermined size, and providing an access wait time between the divided access time units, the first processor 110 provides a predetermined shared memory area at the access wait time. By accessing the access wait time of the first processor 110 can be reduced.

In FIG. 3, the access time unit (AT) and the access wait time (IT) for the shared memory area of the second processor 120 are the performance of the first processor 110 or the job data mainly processed by the second processor 120. It can be set in predetermined time units according to the type of.

In addition, each of the access time units AT and the access wait time IT for the shared memory area of the second processor 120 may be set in a predetermined time unit or may be set in different time units. For example, the access time unit AT of the predetermined shared memory area of the second processor 120 is set to less than half the average access time of the first processor 110, thereby sharing the first processor 110. The maximum access wait time for the memory area may be reduced to less than or equal to the access time unit of the second processor 120.

In addition, the division of the access time of the second processor 120 to the shared memory area lowers access to the shared memory area of the second processor 120 by using an application programming interface (API). -level) can be implemented in software without additional hardware.

4 is a flowchart illustrating a method of accessing a shared memory area of a second processor in a multiprocessor system according to an embodiment of the present invention.

Referring to FIG. 4, first, the second processor 120 requests an access to the access controller 220 to access a predetermined shared memory area (step 301). That is, the second processor 120 transmits a logical value '0' to the access controller 220 as an access request signal SEM to request access to a predetermined shared memory area.

Thereafter, the second processor 120 reads the access permission signal READY from the access controller 220 and determines whether to allow access to the predetermined shared memory area (step 303).

That is, when the access permission signal READY output from the access control unit 220 has a logic value of '0', the second processor 120 determines that access to the predetermined shared area is allowed, and the access control unit ( When the access permission signal READY outputted from 220 is a logic value '1', it is determined that access to the predetermined shared area is not allowed. Here, when the access permission signal READY is a logic value '1', it means that the first processor 110 is approaching the predetermined shared memory area.

If it is determined in step 303 that the access is permitted, the second processor 120 accesses the predetermined shared memory area to read or write data (step 305).

The second processor 120 determines whether a predetermined access time for the predetermined shared memory area has ended (step 307), and if it is determined that the access time for the predetermined shared memory area has not ended, step Returning to 305, continue reading or writing to the predetermined shared memory area.

If it is determined in step 307 that the access time has ended, the second processor 120 temporarily terminates the access to the predetermined shared memory area and notifies the access controller 220 of the end of access to the first processor 110. Allows access to the predetermined shared memory area (step 309) and enters a wait state for access to the shared memory area (step 311). Here, the second processor 120 notifies the end of the access to the predetermined shared memory area by transmitting a logic value '1' to the access controller 220.

Thereafter, the second processor 120 determines whether the preset access wait time has ended (step 313), and if it is determined that the access wait time has not ended, returns to step 311 to access the predetermined shared memory area. If it is determined that the access wait time has ended, it is determined whether an event corresponding to the end of the access to the shared memory area has occurred (step 315).

If it is determined in step 315 that an event corresponding to the end of the access to the predetermined shared memory area has occurred, the access to the predetermined shared memory area is terminated, and if it is determined that an event corresponding to the end of the access has not occurred, step By returning to 301 and sequentially performing subsequent steps, the first processor 110 performs access to the predetermined shared memory area according to a preset access time unit AT and an access wait time unit IT. By performing the access to the predetermined shared memory area in the access wait time, the overall access delay time of the first processor 110 is reduced.

In addition, the access method to the shared memory area according to the embodiment of the present invention illustrated in FIG. 4 may be applied to each of the plurality of shared memory areas.

According to the shared memory access method of the multi-processor system as described above, the first processor divides the access of the second processor to a predetermined shared memory area by a predetermined time unit, and prepares an access waiting time between the divided access time units. Allow a processor to access the predetermined shared memory area.

 Accordingly, the access delay time of the first processor (main processor) having lower processing performance than that of the second processor (additional processor) and having a larger data processing unit can be reduced, thereby improving the processing speed of the entire multiprocessor system.

In addition, by dividing the access time of the second processor to a predetermined shared memory area by a software method without adding additional hardware, the performance of the multiprocessor system can be improved at a low cost.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (9)

In the shared memory access control method of a multi-processor system including a first processor, a second processor and shared memory, Accessing the shared memory area by the second processor for a preset access time; Waiting, by the second processor, to access the shared memory area for a preset waiting time after the access time expires; And Accessing the shared memory at the waiting time by the first processor, wherein the second processor accesses the shared memory area during the preset access time, and preset waiting after the access time is terminated. And accessing the shared memory by repeating the step of waiting for access to the shared memory area for a period of time. The method of claim 1, wherein the access time is divided by a predetermined time interval by which the second processor accesses the shared memory. The method of claim 1, wherein the second processor accesses the shared memory area for a preset access time. Requesting access to the shared memory area by the second processor; And determining, by the second processor, whether to allow access to the shared memory area. The method of claim 3, wherein the request for access to the shared memory area is performed by the second processor to request access to the shared memory area by transmitting an access request signal having a first logic value to an access controller. Shared memory approach in a multiprocessor system. The method of claim 3, wherein determining whether to allow access to the shared memory area comprises determining whether to allow access to the shared memory area by determining, by the second processor, a logical value of an access permission signal provided from an access controller. Shared memory access method of a multiprocessor system. The method of claim 1, wherein the second processor waits for access to the shared memory area for a preset waiting time after the access time ends. Determining whether the access time ends; Notifying the end of the access time by the second processor when the access time ends; And waiting for access by the second processor to the shared memory area for a preset waiting time. The multi-processor system of claim 6, wherein the notifying the end of the access time by the second processor comprises notifying the end of the access time by transmitting a second logic value to the access controller. Shared memory approach. The method of claim 1, wherein the method of accessing the shared memory of the multiprocessor system comprises: after the preset processor is approaching the shared memory area after the preset waiting time is over, after the access of the first processor is terminated. And accessing the shared memory during the access time. Claim 9 was abandoned upon payment of a set-up fee. The method of claim 1, wherein the first processor is a main processor of the portable terminal, and the second processor is an additional processor of the portable terminal.

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