JP2002123420A - Memory access device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory access device by which lowering in the performance of a CPU is suppressed to a minimum by shortening data access waiting time caused by the competition of memory access in a shared memory access device in which the CPU and a memory access means share a memory means. SOLUTION: The memory access request of a memory access means 4 is divided by an access dividing means 7, and the divided memory access instructions is interrupted by a memory access request from a CPU 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared memory access device in which a plurality of memory access units including a CPU share the same memory unit.

[0002]

2. Description of the Related Art In recent years, memories typified by DRAMs are:
It is mainly used for main storage of personal computers, and its capacity has been increased with the progress of semiconductor technology. On the other hand, home appliances also require memory along with the trend of digitization, but the absolute required memory capacity is smaller than that of personal computers.

[0003] Further, with the yearly progress of semiconductor technology and the large demand for personal computers, relatively small-capacity memories required by home electric appliances are disappearing from the market. Under such circumstances, a shared memory system in which a single large-capacity memory is shared by a plurality of LSIs including a CPU is required for home electric appliances from the viewpoint of efficient use of memory and cost reduction by sharing memory. It has been.
Hereinafter, a conventional shared memory access device will be described.

FIG. 5 is a block diagram of a conventional shared memory access device. In FIG.
Is the CPU 100 or 101 and the other CPU
Are accessing the shared memory 102, the access request flag set when the shared memory 102 cannot be accessed.
A semaphore 01 is set when the shared memory 102 is being accessed (see Japanese Patent Application Laid-Open No. 9-6735).

[0005] The operation of the shared memory access device configured as described above will be described.

When the CPU 100 accesses the shared memory 102, the CPU 100 checks the semaphore 104 and checks whether the other CPU 101 uses the shared memory 102.

When used, the CPU 100
After the memory access of PU 101 is completed, shared memory 1
The access request flag 103 is set in order to notify the CPU 101 of the use of “02”.

The CPU 101 accesses the shared memory so that the access to the shared memory 102 is completed within a predetermined time. When the memory access is completed, the CPU 101 checks the access request flag 103 and checks the other CPU.
(In this case, the CPU 100) confirms whether an access request has been issued, and if there is an access request, releases the semaphore and gives the CPU 100 access to the shared memory.

As described above, by setting the time during which the CPU 100 and the CPU 101 access the shared memory within a certain time, the time that the CPU 100 and the CPU 101 wait due to contention for memory access can be shortened.

[0010]

However, in the above-mentioned conventional memory access method, the CPU checks the presence or absence of the other memory access request every time the memory access for a certain time is completed. There is a problem that access to the memory is temporarily interrupted and the performance of the memory cannot be fully utilized.

When the memory access is transferred to the other CPU, the CPU issues a memory access request again after a lapse of a predetermined time. At that time, the memory access of the other CPU is completed in a shorter time than the predetermined time. If either C
The PU also has a period during which no access is made to the memory, which causes problems such as a reduction in memory use efficiency and an increase in CPU wait time.

SUMMARY OF THE INVENTION In view of the foregoing, it is an object of the present invention to reduce the data waiting time of a CPU and improve the memory use efficiency in a system using a shared memory.

[0013]

In order to achieve this object, a memory access device according to the present invention comprises a memory means for storing data, and a CPU for accessing the memory means.
A memory access unit that accesses the memory unit; an arbitration unit that arbitrates a memory access request from the CPU and the memory access unit; and a memory access request arbitrated by the arbitration unit that accesses data of a predetermined length. An access division unit for dividing the data into a plurality of data access instructions, and a memory control unit for controlling the memory unit based on the memory access instructions divided by the access division unit.

With this configuration, the access dividing means can
The memory access request from the memory access unit is divided into a plurality of memory access instructions for accessing data of a fixed length, and the divided individual memory access instructions are issued to the memory control unit in synchronization with the request from the CPU. The CPU access request storage means for storing the memory access request is checked, and when there is a valid access request from the CPU, the memory access instruction from the CPU is interrupted between the divided memory access instructions, thereby enabling the memory access from the CPU to be performed. Data access time to the means can be processed in a short time.

The arbitration means preferentially processes the memory access from the CPU.
By storing the memory access request from the CPU in the CPU access request storage means, the CPU does not need to issue the same access to the memory means a plurality of times to the arbitration means by re-access, thereby reducing the overhead associated with the memory access of the CPU. be able to.

The access dividing means divides each of the memory access from the CPU and the memory access from the memory accessing means into a plurality of memory access instructions for accessing data of a fixed length, and issues them to the memory controlling means alternately. By doing so, the memory access waiting time between the CPU and the memory access means can be reduced,
And the processing efficiency of the memory access means can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described below with reference to the drawings.

In this embodiment, one CP is used for explanation.
Consider a case where U and one memory access unit share a shared memory.

FIG. 1 is a block diagram showing a shared memory access device according to the first embodiment of the present invention.

In FIG. 1, 1 is a memory means for storing data, 2 is a memory control means for controlling the memory means 1,
3 is a CP for performing data access to the memory means 1
U and 4 denote memory access means for performing indefinite-length data access to the memory means 1; 5 arbitration means for arbitrating access to the memory means 1 from the CPU 3 and the memory access means 4; The CPU access request storage means 7 for storing the memory access information of the memory device divides the memory access request arbitrated by the arbitration means 5 into a plurality of memory access instructions for accessing data of a fixed length. This is an access dividing unit that issues an access instruction.

FIG. 2 is a diagram showing the relationship between a memory access request and a memory access instruction. In the figure, reference numeral 10 denotes a 256-byte memory access request requested by the memory access unit 7, and reference numerals 11 and 12 denote the first half of the access division unit 7 dividing the 256-byte memory access request 10 and issuing it to the memory control unit 2. These are a 128-byte memory access instruction and a latter-half 128-byte memory access instruction.

FIG. 3 is a diagram showing the structure of a memory access instruction divided and outputted by the access dividing means 7. In the figure, reference numeral 13 denotes a CPU memory access instruction obtained by converting a memory access request issued from the CPU 3 by the access dividing means 7.

The operation of the shared memory access device according to the present embodiment configured as described above will be described.

First, for the memory means 1, the CPU 3,
From the state where the memory access means 4 is not accessing,
A case where the memory access unit 4 writes 256 bytes of data into the memory unit 1 will be described.

The memory access unit 4 issues a 256 byte memory access request 10 to the arbitration unit 5.
The arbitration unit 5 accepts a 256 byte memory access request 10 from the memory access unit 4 because there is no memory access request from the CPU 3.

The access dividing means 7 converts the 256-byte memory access request 10 arbitrated by the arbitrating means 5 into the first half 128-byte memory access instruction 11 and the second half 1
It is divided into 28-byte memory access instructions 12 and the first half 128-byte memory access instructions 1
Issue 1.

Next, the access dividing means 7 checks whether or not valid memory access request information from the CPU 3 is stored in the CPU access request storage means 6. Of 1
After the 28-byte memory access instruction 11 has been processed,
A memory access instruction 12 of the latter 128 bytes is issued to the memory control means 2.

The memory control means 2 includes an access division means 7
The memory unit 1 is controlled based on the memory access instructions 11 and 12 from the CPU 1 and actual data access is performed on the memory unit 1. After all the memory access requests from the memory access unit 4 have been processed, the arbitration unit 5 notifies the memory access unit 4 that the writing has been completed.

Next, for the memory means 1, the CPU 3,
From the state where the memory access means 4 is not accessing,
A case where the CPU 3 writes data to the memory means 1 will be described.

The CPU 3 issues a memory write request to the arbitration means 5. The arbitration unit 5 is configured so that the access division unit 7 does not process another memory access request.
A memory access request from the CPU 3 is accepted.

The access dividing means 7 issues the memory access request arbitrated by the arbitrating means 5 to the memory control means 2 as a CPU memory access instruction 13, and the memory control means 2
Write request data from the CPU 3 is written into the memory means 1. After the data is written in the memory means 1, the arbitration means 5 notifies the CPU 3 that the writing has been completed.

Further, a case where an access request is issued from the CPU 3 while the access dividing means 7 is dividing the write request from the memory access means 4 will be described.

When the arbitration unit 5 receives the memory access request from the CPU 3 and confirms that the access division unit 7 is processing the memory access request from the memory access unit 4, the arbitration unit 5 stores the CPU access request in the CPU access request storage unit 6.
Is stored.

After issuing the first-half 128-byte memory access instruction 11 to the memory control means 2, the access division means 7 checks the CPU access request storage means 6 for valid memory access information. Since the CPU access request storage means 6 has valid memory access information,
Before issuing the memory access instruction 12 of the latter half 128 bytes to the memory control means 2, the access dividing means 7
The memory access request stored in the U access request storage means 6 is issued to the memory control means 2 as a CPU memory access instruction 13.

After that, after issuing the CPU memory access instruction 13, the access dividing means 7 checks the CPU access request storage means 6 for valid memory access information. If there is a valid memory access, the CPU
A memory access request is issued to the memory control means 2. If there is no valid memory access request, a memory access instruction 12 of the latter half 128 bytes is issued to the memory control means 2.
The memory access request of 256 bytes requested by the memory access means 4 is completed.

As described above, according to the present embodiment, the access dividing means 7 divides the memory access request from the memory access means 4 and
12 between memory access instructions 11 and 12
By inserting the CPU memory access command from the PU 3, the CPU 3 can access data from the memory means 1 in a short period of time.

The arbitration means 5 preferentially processes a memory access request from the CPU 3, and if it cannot be processed, C
By storing the memory access information from the PU 3 in the CPU access request storage means 6, the memory access time from the CPU 1 can be further reduced.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.

In the present embodiment, for the sake of explanation, a case is considered where one CPU and one memory access unit share a shared memory, as in the first embodiment.

FIG. 4 is a diagram showing the order of memory access instructions output from the access dividing means 7. 14,
Reference numerals 15 and 16 denote first, second and third memory access commands divided by the access division means 7 based on a memory access request from the memory access means 4, respectively.
Reference numerals 18 denote first and second CPU memory access commands, respectively, divided by the access dividing means 7 based on a memory access request from the CPU 3.

The operation of the shared memory access device according to the present embodiment configured as described above will be described.

The arbitration unit 5 receiving the memory access request from the memory access unit 4 issues a memory access request to the access division unit. The access dividing means 7
It is divided into first to third memory access instructions 14, 15 and 16, and the first memory access instruction is first issued to the memory control means 2.

The access dividing means 7 then checks whether there is a valid memory access request in the CPU access storage means 6, and if there is a valid memory access request, it divides the memory access request into the first and second CPUs. It is divided into memory access instructions 17 and 18.

The access dividing means 7 thereafter transmits the second and third memory access commands 15 and 16 and the first and second CPs.
U memory accesses 17 and 18 alternately
Issue for

As described above, according to the present embodiment, the CP
The memory access request from U3 and the memory access request from memory access means 4 are each divided into a plurality of memory access instructions for accessing data of a fixed length by access dividing means 7, and each is alternately transmitted to memory control means 2. By issuing the command, the waiting time for memory access from the CPU 3 and the memory access unit 4 can be reduced.

In the first embodiment and the second embodiment, the number of the CPU 3 and the number of the memory access means 4 are each one, but the same effect is obtained even if there are a plurality of the CPUs 3 and the memory access means 4. There is.

Further, in the first embodiment, an example has been described in which the memory access means 4 transfers 256 bytes of data. However, a similar effect can be obtained even if the transfer length is longer or shorter.

[0048]

As described above, according to the present invention, a memory access request from a memory access unit is divided into a plurality of memory access instructions for accessing data of a fixed length by an access dividing unit. For example, an excellent shared memory access device can be realized in which a memory access instruction from a CPU is interrupted between memory access instructions, thereby shortening a memory access time from a CPU to a memory unit.

The arbitration means preferentially processes memory access from the CPU.
By storing the memory access request from the CPU in the CPU access request storage means, the CPU does not need to issue the same access to the memory means a plurality of times to the arbitration means by re-access, thereby reducing the overhead associated with the memory access of the CPU. The present invention realizes an excellent shared memory access device that can perform the above operations.

The access dividing means divides each of the memory access from the CPU and the memory access from the memory accessing means into a plurality of memory access instructions for accessing data of a fixed length, and issues them alternately to the memory controlling means. By doing so, the memory access waiting time between the CPU and the memory access means can be reduced,
The processing efficiency of U and the memory access means can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a shared memory access device according to a first embodiment of the present invention;

FIG. 2 is a relationship diagram between a memory access request and a memory access instruction in FIG. 1;

FIG. 3 is a diagram showing memory access division by the access division means of FIG. 1;

FIG. 4 is a diagram showing memory access division by an access division unit according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration of a conventional memory access device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory means 2 Memory control means 3 CPU 4 Memory access means 5 Arbitration means 6 CPU access request storage means 7 Access division means

Claims (5)

[Claims] 1. A memory means for storing data, a memory control means for controlling said memory means, one or more CPUs for accessing data to said memory means,
One or more memory access means for accessing data to the memory means, and one or more CPs
U and an arbitration unit for arbitrating a memory access request from the one or more memory access units; a CPU access request storage unit connected to the arbitration unit and storing a memory access request from the one or more CPUs; An access division unit divides the memory access arbitrated by the arbitration unit into a plurality of memory access instructions for accessing data of a fixed length, and issues a memory access instruction to the memory control unit in units of the divided memory access instructions. A memory access device. 2. The arbitration means according to claim 1, wherein said access division means divides the memory access by one or more CPs.
U. The access request from U is preferentially received, and the memory access request from the one or more CPUs is stored in an access request storage unit. 2. The memory access device according to claim 1, wherein a memory access request from a plurality of CPUs is notified to a memory dividing unit with priority. 3. The access dividing means divides the memory access request arbitrated by the arbitrating means into a plurality of memory access instructions for accessing data of a fixed length, and issues the divided memory access instructions to the memory control means. In synchronization with the above, a memory access request from one or more CPUs stored in the CPU access request storage means is confirmed, and when there is an access request from the one or more CPUs, 2. The memory access device according to claim 1, wherein a memory access request from the CPU is interrupted next to the currently issued memory access instruction, and is issued to the memory control means as a memory access instruction. 4. A memory means for storing data, a memory control means for controlling said memory means, a CPU for accessing data to said memory means, and a memory access means for accessing data to said memory means. When,
The memory access request from the CPU and the access request from the memory access unit are divided into a plurality of memory access instructions for accessing data of a fixed length, and the divided memory access instructions are alternately transmitted to the memory control unit. A memory access device, comprising: an access dividing unit for issuing the access division unit. 5. When a CPU and a memory access unit share a memory unit, a memory access request of the memory access unit is divided, and a memory access request from the CPU is interrupted between the divided memory accesses. Characteristic memory access method.