JPH07101411B2 - Extended storage access controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a plurality of independently operable main storage devices, a plurality of access request source devices that access the main storage devices, and expansion of the main storage devices as auxiliary storage. An extended storage access control device for performing data transfer to and from an extended storage device of a multiprocessor system including a storage device and a storage control device for controlling data transfer between them, and to an extended storage device For the purpose of high-speed and efficient data transfer of each storage controller, each storage controller is equipped with a buffer for transferring data to and from the extended storage device connected to itself, and is used for data transfer between the main storage device and the extended storage device. The access request source issues an access request to the main storage device, and based on the access request, data transfer between the buffer and the main storage device is performed. Data transfer between the extended storage device and the buffer according to the amount of data in the buffer,
An extended storage device is connected in data transfer from an access request source device connected to one storage control device to the main storage device using an extended storage control device connected to the other storage control device. Data transfer from the storage control device to the other storage control device uses the time when there is no main storage read data transfer on the main storage read data bus, and the storage control device to which the extended storage device is connected stores the transfer data from the buffer in the main storage. The storage controller connected to the access request source sets the data on the read data bus and sends the data valid signal. The storage controller, which sees the data valid signal, sets the data in the buffer and follows the main memory write request issued by the access request source. It is configured to set the buffer data on the write data bus corresponding to the device.

[Industrial application field]

The present invention relates to an extended storage access control device, and more particularly, an access is made between an access request source device and a main storage control device and an extended storage device via the storage control device, and the storage control device is connected to another storage control device. The present invention relates to data transfer between a main storage device and an expansion storage device in a multiprocessor system connected via an interface line.

[Problems to be Solved by Prior Art and Invention]

As computer systems have become larger and faster in recent years, some of the pages in main memory that are not needed for immediate execution are saved in auxiliary memory,
A paging operation is performed to load the saved contents into the main storage device again when the page becomes necessary. Conventionally, a relatively high-speed direct access such as a magnetic disk or a magnetic drum has been used as a storage device for saving paging. DASD (Direct Access Storage Device) is used. An extended storage device using a large capacity RAM has also been proposed as a means for further speeding up the paging operation.

Generally, the operating speed of an extended storage device using a large-capacity RAM is about a fraction of the operating speed of a CPU, and the data transfer capability is about a fraction of that of a main storage device directly accessed by the CPU, which is a high speed. However, since the extended storage device is usually farther from the CPU than the main storage device, a rise time until a data transfer start instruction is sent to the extended storage device and data is obtained, and a stop instruction is issued. It takes a long time to transmit and stop the
For the sake of convenience, doing finely will reduce the efficiency.

On the other hand, a plurality of independently operable main storage devices and a plurality of access request source devices that access the main storage device are connected to the storage control device, and access from each access request source device to the main storage device must be storage controlled. From the access request source device connected to one storage control device of a multiprocessor system in which a plurality of storage control devices are connected to each other, to a main storage device connected to another storage control device. Access is always performed via an interface line including a read data bus between storage controls commonly used by a plurality of access request source devices connected to the storage control device to which the access request source device is connected. Access to the main storage device connected to the storage control device, the extension storage device connects the interface line between the storage control devices, especially the read data bus. Such as data transfer from the extended storage unit to another storage control device one of the storage controller access request source is connected from and to be occupied by another access performance may decrease to.

Therefore, in the extended storage access of the multiprocessor system, while the bus is shared with the bus used by the access request source device to access the main storage device, the data between the extended storage device and the extended storage device using the large capacity RAM are used. It is necessary to perform the transfer at high speed and efficiently, while controlling so as not to interfere with the main memory access request of the access request source device.

An object of the present invention is to provide an extended storage access using a large capacity RAM while commonly using a bus used by an access request source device to access a main storage device in an extended storage access of a multiprocessor system. Another object of the present invention is to provide a control method for executing the above data transfer at high speed and efficiently, while minimizing the interference with the main memory access request of the access request source device.

[Means and Actions for Solving Problems]

In order to achieve this object, according to the present invention, the means includes a plurality of independently operable main storage devices, a plurality of access request source devices that access the main storage devices, and unnecessary areas of the main storage devices. An extended storage device that temporarily saves data is connected to the storage control device, and each access request source device always accesses the main storage device through the storage control device, and more than one storage control device is connected. In this multiprocessor system, access from the access request source device connected to one storage control device to the main storage device connected to another storage post-production device is always performed via the interface line between the storage control devices. Each storage controller is provided with a buffer for transmitting and receiving data to and from the expansion storage device connected to itself, and the data transfer between the main storage device and the expansion storage device is not permitted. An access request is issued from the access request source to the main storage device, data transfer between the buffer and main storage device is performed based on the access request, and data transfer between the extended storage device and the buffer is performed according to the amount of data in the buffer. The extended storage device is connected in the data transfer from the extended storage device to the main storage device using the extended storage device connected to the other storage control device from the access request source device connected to one storage control device. Data transfer from one storage controller to the other storage controller uses the time when there is no main memory read data transfer on the main memory read data bus, and the storage controller to which the extended storage device is connected transfers the transfer data from the buffer. The storage controller to which the access request source is connected while setting the main memory read data bus and sending the data valid signal Watching over data valid signal, characterized in that so as to set the buffer data of the write data bus for the access requesting device according to a main memory write request access request source emitted to set data in the buffer.

〔Example〕

FIG. 1 is a configuration diagram of a multiprocessor system to which an extended storage access control device according to the present invention is applied. In the figure, MSU is a plurality of independently operable main storage devices, CPU and CHP are a plurality of access request source devices that access this MSU, ESU is an extended storage device that temporarily saves unnecessary areas of the MSU, and The MCU is a storage controller that controls access from each CPU, CHP to MSU, ESU. Further, in the MCU, a plurality of MCUs are further connected via an interface line, and a CPU connected to one MCU always accesses the MSU connected to another MCU via the interface line.

In such a configuration, each storage controller MCU 0, MCU 1
Has a buffer that is commonly used to receive and write data to the ESU connected to itself, and in the case of data transfer from MSU to ESU, a read request is issued from the CPU to the MSU and the read data is The data is transferred to the ESU by storing it in the buffer and checking the existence of the data in the buffer independently of the operation. ESU
In the case of data transfer from the MPU to the MSU, the CPU issues a write request to the MSU, sets the write data from the buffer to the write data bus PORT0 WD or PORT1 WD of the CPU, and from the ESU independently of the operation. The data transfer to the buffer is controlled to be performed.

Further, data transfer of the extended storage device across the two storage control devices, for example, an ES connected from the CPU 0 connected to one storage control device MCU 0 to the other storage control device MCU 1.
For data transfer from ESU 1 using M 1 to MSU 2 or MSU 3, the main unit connected to storage controller MCU 1 from the access request source device connected to storage controller MCU 0 to which ESU 1 is connected The main memory read data bus from the MCU 1 to the other MCU 0 by the read request from the memory device is used during the time when there is no main memory read data transfer, and the MCU 1 to which the ESU 1 is connected mainly transfers the transfer data from the buffer. The MCU 0 connected to CPU 0 is connected to the memory read data bus and sends the data valid signal. MCU 0 sees the data valid signal, sets the data in the buffer, and responds to CPU 0 according to the main memory write request issued by CPU 0. Write data bus POP
Set buffer data in T0 WD or PORT1 WD. Further, the MCU 0 is provided with means for performing an operation of ensuring a buffer of the MCU 1 in advance for access using the ESU 1 connected to the MCU 1.

2 (a) and 2 (b) are block diagrams of the control unit in the MCU shown in FIG. 1, and FIG. 3 is a detailed view of the CONTROL unit in FIG. 2 (b). In the figure, RQ is an access request, WD is write data, RD is read data, LP is a local pipeline, RMCU is another system MCU (MCU 1 in this case), LMCU is its own system MCU (in this case, MCU 0 ), PORT is a port, INQCT is an in counter, OUTQ CT is an out counter.

First, as shown in FIG. 2 (a), a part of MSU 0 from CPU 0, CPU, CHP 0, etc. (which will be described below for the sake of simplicity of explanation), which are access request sources, in MCU 0
When an access to save to ESU 0 is made, the access request RQ is temporarily set to PRE PORT, and is set to PORT 0 or PORT 1 after address translation. PORT 0 or PORT
The access request set to 1 goes through the priority circuit LMCU PRIORITY of the own system MCU and is set to a local pipeline LP (not shown).

The access request set in LP is checked by the control unit (not shown) whether the ESU is available or not, and the result is reported to CPU 0. When ESU is enabled, continue from CPU 0
A read request access is issued to the MSU.

As shown in FIG. 2 (b), the read request access to the MSU passes through the PRIORITY circuit, and the MSU read data R is generated at an appropriate timing after the access request RQ is generated to the MSU.
D is set in the register LMRDIR of its own system and then written in the buffer BUFFER via the buffer data selector BR SEL. At this time, the in-counter INQ CT (3rd
(See the figure) is added, and the buffer BUFFER is
It is determined that there is valid data in BUFFER by the difference between Q CT and OUT counter OUTQ CT. When there is valid data in BUFFER, data is sent to ESU via register BFRDR.
WD is transferred. At this time, the MCU sends a DATA VAL signal to the ESU as a valid display.

Then on access to reload data from ESU to MSU again
If the ESU is usable, data is sequentially transferred from the ESU together with the read data valid signal. As shown in FIG. 2 (b), the transfer data ESURD from the ESU passes through ESRDI, BDSEL and B
It is written to UFEER, and therefore the in-counter INQ CT is added to indicate that valid data exists in the BUFFER. ES
A write request access to the MSU is issued from the CPU that the U is reported to be available. Write request access is PRE
If there is valid data in BURRER when set from PORT to PORT 0 or PORT 1, the BUFFER data in the WD PORT0 WD or PORT1 WD register of the corresponding RORT is BFRDR and WDSEL.
Set via. After that, the relevant access passes through PRIORITY, a request RQ is issued to MSU, and writing is performed. Write request access is from PRE PORT to PORT 0 or PO
PRIO until valid data is set in BUFFER if valid data does not exist in BUFFER when set to RT 1
The passage of RITY is prohibited.

Next, of the access that saves data from MSU to ESU among the accesses across MCUs, for example, when CPU 0 requests the transfer of MSU 2 to ESU 0, the data read access to MSU 2 from CPU 0 is 0 or PORT 1 to RM
It is requested to MCU 1 as RMCU RQ through CU PRIORITY, and its access is sent to MSU 2 via LMSU PRIORITY of MCU 1.
LMRDIR, RMDES of MCU 1 at the appropriate timing when Q is issued
Set to RMRDIR of MCU 0 via EL, RMRDO, and BDSEL
Is written to BUFFER via. Subsequent processing Same as MSU → ESU data transfer in the same MCU.

When reloading from ESU 1 to MSU by access from CPU 0, the access request is set to PRE PORT of the Kikuoku controller MCU 0 to which the access request source is connected, and is set to PORT 0 or PORT 1 after address translation. It PORT0 or POR
The access request set in T1 is set in LP (not shown) via the LMCU PRIORITY and is also propagated to RP1 of the MCU1 via the interface line of the storage controller. In the MCU1, the ESU activation unit of FIG. 3 checks whether or not the access using the preceding ESU1 is suspended based on the information of RP1, and when there is no access using the preceding ESU1, the BUFFER indicates the access. The ESU1 is checked for availability and the result is reported to the MCU0 via the interface line between the storage controllers. As a result, ESU1 can be used and MCU 0 and MUC 1
After it is determined that the BUFFER is available, the read data from the ESU is sequentially written to the BUFFER in MCU 1. M
When valid data exists in BURRER of CU 1, another LMRD
Checks that there is no data transfer to MCU 0 via IR, RMDSEL, RMRDO, and transfers ESU data to MCU 0 via BFRDR, RMDSEL, RMRDO. At this time, MCU 1 sends a data valid signal to MCU 0. The MCU 0 recognizes the data transfer by the data valid signal and writes the data of RMRDIR to BUFFER through BDSEL. The subsequent steps are as described above.

〔The invention's effect〕

As described above, according to the present invention, in the extended storage access of the multiprocessor system, a large capacity RAM is used while commonly using the bus used by the access request source device to access the main storage device. Data transfer to and from the extended storage device can be performed at high speed and efficiently, while there is an effect that interference with the access request source device can be controlled to a minimum.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiprocessor system to which the present invention is applied, FIGS. 2 (a) and 2 (b) are detailed views of a main part of the storage control device of FIG. 1, and FIG. It is a detailed view of a part. (Explanation of symbols) ESU 0, ESU 1 ... extended storage device, MSU to MSU 3 ... main storage device, MCU 0, MCU 1 ... storage control device, CPU 0 to CPU 3, CHP 0, CHP 1 ... Access request source device.

Claims (1)

[Claims] 1. A storage control device comprising: a plurality of independently operable main storage devices; a plurality of access request source devices that access the main storage devices; and an extended storage device that temporarily saves unnecessary areas of the main storage devices. A multiprocessor system in which a plurality of storage control devices are connected to each other, and each access request source device accesses the main storage device via the storage control device. Access from the access request source device connected to the main storage device connected to another storage control device is performed via the interface line between the storage control devices, and each storage control device is connected to itself. A buffer for transferring data to and from the storage device is provided, and an access request from the access request source to the main storage device is made for data transfer between the main storage device and the extended storage device. Extended storage access control in a multiprocessor system that transfers data between the buffer and the main storage device based on the access request, and further transfers data between the extended storage device and the buffer according to the amount of data in the buffer. In the device, data transfer from the extended storage device using the extended storage device connected to the other storage control device from the access request source device connected to one storage control device of the plurality of storage control devices to the main storage device In the data transfer from the storage control device to which the extended storage device is connected to the other storage control device, the access request of the main storage read data bus of the interface line between the storage control devices that issued the access request to the extended storage device. Other connected to the storage controller to which the original is connected The storage control device to which the extended storage device is connected transfers the transfer data from the buffer to the storage control device while the main storage read data transfer by the data read request from the main storage device connected to the other storage control device is not used. Is set to the main memory read data bus of the interface line between them, and the data valid signal is sent out, and the storage control device to which the access request source is connected receives the data valid signal and sends it via the main memory read data bus from the other storage control device. Access buffer that sets data in the buffer, sets the buffer data in the write data bus corresponding to the access request source device according to the main memory write request issued by the access request source, and sends the access request to the extended storage device. The storage controller to which the device is connected reserves the buffer of another storage controller in advance. Comprising means for performing operations, said storage control unit is expanded storage access control apparatus characterized by accessing an extended storage device connected to the other storage controller.