JPH04313134A - Computer system - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency in a multiprocessor system by shortening the time when the DMA transfer request data are written in a shared memory and then actually used by a processor. CONSTITUTION:In a processor unit 1a that requests a DMA, a DMA number is set to a DMA request register 14a and a cache control circuit 12a writes the data equal to the data written in a shared memory 3 into a cache memory 11a when the data are transferred and written into the memory 3 from an I/O device 5. In a processor unit 1b where no DMA number is set to a DMA request register 14b, a cache control circuit 12b invalidates the data stored in a cache memory 11b provided in an address equal to that of the memory 3 which is updated with the DMA transfer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a cache memory is provided for each processor in a multiprocessor system.

0002

[Prior Art] Conventionally, in a multiprocessor system,
A shared memory is provided that is commonly used by each processor as a main memory. Each processor is provided with a cache memory, and stores part of the data stored in the shared memory in the cache memory. This allows each processor to access frequently used data at high speed, depending on the content of its respective data processing.

[0003] When data is transferred between an input/output device connected to the system and a shared memory using a DMA (direct memory access) method, each processor monitors the state of writing data to the shared memory. There is a need. This is to ensure consistency with the cache memory when data transferred from the input/output device is written to the shared memory.

Each processor invalidates cache memory data (hit data) at the same address as the shared memory address where the data was written. After this,
Each processor stores updated data from the shared memory in the cache memory as needed.

[0005]

[Problems to be Solved by the Invention] When data transferred from an input/output device using the DMA method is written to a shared memory, each processor needs to invalidate the hit data in the cache memory. By the way, each processor acquires the right to use the shared bus (system bus) after completing data transfer using the DMA method.
The write data will be read from the shared memory.

[0006] Therefore, after each processor outputs a DMA transfer request, it takes a considerable amount of time for the data written to the shared memory to be stored in the cache memory and used for various data processing. become. For this reason,
Each processor requires a large amount of time to actually use the data from the input/output device, resulting in a problem of reduced data processing efficiency.

An object of the present invention is to shorten the time it takes for a processor to actually use the data after DMA transfer requested data is written in a shared memory in a multiprocessor system, and as a result, the data processing speed is reduced. An object of the present invention is to provide a computer system that can improve efficiency.

[0008]

SUMMARY OF THE INVENTION The present invention is a system in which each processor unit has a processor and a cache memory, and has DMA control means for controlling data transfer between input/output means and shared memory means. Each processor unit has cache memory control means for writing the same data as the write data into the cache memory when the data requested for DMA transfer is transferred to the shared memory.

[0009]

According to the present invention, the DMA control means transfers write data from the input/output means to the shared memory means in response to a DMA request from the processor. When executing this data transfer, the processor that made the DMA request writes the same data as the transferred write data into the cache memory. This allows the processor to access and use the cache memory immediately after the data requested for DMA transfer is written to the shared memory.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a multiprocessor system according to the same embodiment. This system includes multiple processor units 1a, 1b, a shared memory 3
, the DMA control circuit 4 and the input/output (I/O) device 5 each share a common bus (data bus 2a and address bus 2b).
connected through.

Each processor unit 1a, 1b includes a processor (CPU) 10a, 10b, a cache memory 11a, 11b, a cache control circuit 12a, 12b,
It has data buffers 13a, 13b and DMA request registers 14a, 14b. Cache memory 11a
, 11b is a high-speed buffer memory that stores the same data required by the CPUs 10a and 10b in the shared memory 3 used as the main memory. Cache control circuits 12a and 12b are cache memory 11a.
, 11b.

[0013] The data buffers 13a and 13b are connected to each CP.
U10a and 10b are buffer memories that temporarily store data input and output through the data bus 2a. DM
The A request registers 14a, 14b are for each CPU 10a, 1
0b accesses the DMA control circuit 4 and the I/O device 5
This register stores a DMA request number (a number corresponding to the I/O number of the I/O device 5) for requesting data transfer between the shared memory 3 and the shared memory 3. Next, the operation of this embodiment will be explained.

When the CPU 10a accesses the shared memory 3, the cache control circuit 12a determines whether or not the address to be accessed is hit, and accesses the hit data from the cache memory 11a. CPU1
0a processes data accessed at high speed from the cache memory 11a and stores it in the data buffer 13a. The data stored in the data buffer 13a is transferred to, for example, another processor unit 1b or I/O device 5 via the data bus 2a. At this time, the address from the CPU 10a accompanying the data transfer is transferred to the address bus 2.
transferred through b. When the CPU 10b accesses the shared memory 3, the same operation as described above occurs.

Here, for example, the CPU 10a needs to read data from the I/O device 5, and makes a DMA request to the DMA control circuit 4 (step S1 in FIG. 2).
. The DMA control circuit 4 determines whether or not there is competition with another CPU 10b, and if there is competition, the other CPU 1
It is in a standby state until the DMA request of 0b is completed (step S2).

[0016] When the conflict is canceled (NO in step S2)
), the CPU 10a sends the DMA request register 14a to the DMA request register 14a.
A request number is set (step S3). The DMA control circuit 4 executes data transfer between the I/O device 5 having the requested I/O number and the shared memory 3 (step S4). That is, data read from the I/O device 5 is transferred to the shared memory 3 via the data bus 2a and written to the requested address (step S5).

During this DMA transfer, the cache control circuit 12a of the processor unit 1a that requested the DMA transfers the data written to the shared memory 3 to the cache memory 1.
1a is executed (step S7). D.M.A.
When the transfer is completed (YES in step S9), CPU1
0a initializes the DMA request register 14a (step S10).

On the other hand, in other processor units 1b that have not been set in the DMA request register 14b, the cache control circuit 12b controls the cache control circuit 12b when a hit occurs at the address of the shared memory 3 where update data (transfer data) is written. - Control is performed to invalidate the data in the memory 11b (step S8). That is, cache memory 11
If data at the address of the shared memory 3 before being updated is stored in b, that data is invalidated. Thereby, consistency between the cache memory 11b and the shared memory 3 can be ensured.

After invalidating the data, the cache control circuit 12b uses the shared memory 3 as required by the CPU 10b.
The updated data is read from the cache memory 11b and written to the cache memory 11b.

In this way, in the processor unit 1a that made the DMA request, when the data is transferred from the I/O device 5 to the shared memory 3 and written, the same data as the written data is written to the cache memory 11a. It will be done. In other words, when the recorded data in the shared memory 3 is updated by DMA transfer, the data in the cache memory 11a is also updated. Therefore, the CPU that requested the DMA
10a can access update data from the cache memory 11a at high speed without securing the right to use the common bus and accessing update data from the shared memory 3 after the DMA transfer.

Furthermore, in the processor unit 1b that does not request DMA, the shared memory 3 updated by DMA transfer is
Cache memory 11b at the same address as
data will be invalidated. Therefore, consistency between the shared memory 3 and the cache memory 11b can always be ensured.

[0022]

As detailed above, according to the present invention, firstly, in a multiprocessor system, when data requested for DMA transfer is written to the shared memory, it is also written to the cache memory. Therefore, the transferred data can be accessed immediately from the cache memory after the DMA transfer. Therefore, after the data requested for DMA transfer is written in the shared memory, the time required for the processor to actually use the data can be shortened, and as a result, data processing efficiency can be improved.

Second, since data in the cache memory of a unit that does not request DMA transfer is invalidated, consistency between the shared memory and the cache memory can always be ensured.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

1a, 1b...processor unit, 3...shared memory, 4
...DMA control circuit, 5...I/O device, 10a, 10b...
Processor, 11a, 11b...cache memory, 1
2a, 12b...cache control circuit, 14a, 14b...
DMA request register.

Claims (2)

[Claims] 1. A computer system in which a plurality of processor units each having a processor and a cache memory are connected through a bus, and an input/output means connected to the bus; shared memory means functioning as a common main memory; DMA control means for controlling data transfer between the input/output means and the shared memory means through the bus; cache memory control means for writing data identical to the write data into the cache memory of the processor unit that executed the DMA request among the processor units when the write data is transferred to the shared memory means; A computer system comprising: 2. A computer system in which a plurality of processor units each having a processor and a cache memory are connected through a bus; shared memory means functioning as a common main memory; DMA control means for controlling data transfer between the input/output means and the shared memory means through the bus; When the write data is transferred to the shared memory means, the same data as the write data is written in the cache memory of the processor unit that executed the DMA request among the processor units, and the other processor units A computer system comprising: cache memory control means for invalidating data at the same address as the address of the shared memory means to which the write data is written in the cache memory.