JPH0668738B2 - Light back control system of file controller - Google Patents

Description

DETAILED DESCRIPTION [Outline] Write-back control of a file control device having a cache memory and a cache control unit, preferentially writing write data from a higher level to the cache memory, and then writing back to the file storage device. In the system, the channel interface unit or the device interface unit is configured by a processor to provide a write-back processing function, and the write-back processing is performed instead when the cache control unit fails.

[Industrial application field]

According to the present invention, in a file control device having a cache memory connected to a file storage device, after writing write data from a higher level in the cache memory, the write data in the cache memory is written in the file storage device and cached. More specifically, the present invention relates to a write-back control method for matching the contents of a memory and a file storage device, and in particular, a write-back of a file control device capable of executing a write-back function even if a cache control unit that controls a cache memory fails. Regarding control method.

In response to the recent demand for faster computer systems, there is a demand for faster external storage system access times.

For this reason, a cache memory is provided in a file control device that controls a file storage device such as a magnetic disk device,
What is called a disk cache that stores a part of the contents of a file storage device in a cache memory is provided on the market.

Since such a cache memory is generally composed of an electronic memory such as a semiconductor memory, a high-order computer can perform high-speed access using the cache memory and can realize a shorter access time.

In a file storage system including such a cache memory, it is necessary that the data on the cache memory and the data on the file storage device match each other so that no contradiction occurs in the data.

[Conventional technology]

 FIG. 5 is an explanatory diagram of a conventional technique.

In the figure, 1 is a central processing unit (hereinafter referred to as CPU), 2 is a channel, 3 is a file control device, 4 is a cache memory, and 5 is a file storage device.

The file control device 3 is provided between the CPU 1, the channel 2 and the file storage device 5, and C via the channel 2 is provided.
The cache memory 4 and the file storage device 5 are accessed in response to an access request from the PU 1.

The file control device 3 is a cache interface unit 3 for performing interface control between the channel interface unit 30 for connection with the channel 2 and data transfer control, the control processor 31, and the cache memory 4.
2 and a device interface unit 33 for controlling the interface between the file storage device 5 and
The cache controller 4 and the cache memory 4 are collectively referred to as a file controller 3.

In such a file control device 3, in response to a read instruction from the CPU 1, the cache memory 4 is searched first, and if the requested data exists (this is called a hit), the data is retrieved from the cache memory 4. Take out,
If the data is transferred to the channel 2 via the channel interface unit 30 and the requested data does not exist in the cache memory 4 (this is called a miss), the file storage device 5
Data is taken out from and is transferred to channel 2 in the same manner.

On the other hand, in response to a write command from the CPU 1, write data is always stored in the cache memory 4.

In this case, in order to match the data of the file storage device 5 and the cache memory 4, the write-through method of writing the given write data to the cache memory 4 and at the same time to the file storage device 5, and the cache memory 4
There is a write-back method in which the write data written in the cache memory 4 is read out from the cache memory 4 and written back in the file storage device 5 after the writing is completed by writing to the cache memory 4 and the free time is utilized.

In the write-through method, the write data is written in both the cache memory 4 and the file storage device 5 to complete the writing, so that the data can be surely matched.

On the other hand, in the write-back method, since the writing is completed when the write data is written in the cache memory 4, C
High-speed write operation is possible from the viewpoint of PU1, and is superior to the write-through method when high speed is required.

[Problems to be solved by the invention]

However, in the write-back method, when a failure occurs in the control processor 31 that performs write-back processing, if there is data that has not been written back in the cache memory 4, the cache memory 4 and the file storage device 5 However, there is a serious problem that the data of and will not match, resulting in a decrease in reliability.

It is an object of the present invention to provide a write-back control method for a file controller that can prevent data inconsistency due to a failure in the write-back method.

[Means for solving problems]

 FIG. 1 is an explanatory view of the principle of the present invention.

In the figure, the same components as those shown in FIG. 5 are designated by the same symbols, 34 is a cache control unit, which performs read / write control and write back processing of the cache memory 4, and 35 is a resource. A management unit that manages resources of the entire file control device 3, and 36 is a bus, which includes a channel interface unit 30, a device interface unit 33, a cache memory 4, and a cache control unit 3.
4 and the resource management section 35 are connected to exchange data and control signals.

Reference numeral 30a denotes a processor, which is provided in the channel interface unit 30 and performs a write-back processing function in addition to channel interface control. 33a is a processor, which is provided in the device interface unit 33 and performs write-back in addition to device interface control. It performs a processing function.

Then, when the cache control unit 34 fails and the write-back process is disabled, the resource management unit 35 instructs the channel interface unit 30 to perform the write-back process, and writes in place of the failed cache control unit 34. Back processing is executed.

[Action]

In the present invention, the channel interface unit 30 or the device interface unit 33 is replaced by the processors 30a, 33.
In addition to the interface function which is the original function, a write back processing function is added.

Therefore, it is possible to perform write-back proxy by utilizing this, and it is possible to prevent the data inconsistency between the cache memory 4 and the file storage device 5.

When there are a plurality of device interface units 33, one device interface unit can be used as the write-back process and the other device interface unit can be used as the device interface control to similarly perform the write-back proxy.

〔Example〕

 (A) Description of Configuration of One Embodiment FIG. 2 is a configuration diagram of one embodiment of the present invention.

In the figure, the same parts as those shown in FIGS. 1 and 5 are indicated by the same symbols, 37 is a shared memory, and a part of this area is allocated as the cache memory 4. It is a thing.

In this example, the file controller 3 has two channel interface control units (hereinafter referred to as CHIC) 30
One device interface control unit (hereinafter referred to as DVIC) 33 is provided, and the CHIC 30 and the DVIC 33 are provided.
Includes a processor, and includes a channel or device interface control program and a write-back processing program as microprograms.

The interface control program is for exchanging data / commands with the channel 2 or the file storage device (hereinafter referred to as FSU) 5.

On the other hand, the cache control unit (hereinafter referred to as CC) 34 includes a processor, has a track number stored in the cache memory 4 and an address of the cache memory 4 in the table as management information, and reads the cache memory 4. / Perform write control.

A resource management unit (hereinafter referred to as RM) 35 includes a processor, a flag indicating whether each unit of the file control device 3 is operating / not operating, a cache memory (hereinafter referred to as SS) 4
The flag indicating the completion / non-completion of write-back, the address of unprocessed write-back data is stored, and each unit is controlled and the failure of CC34 is detected.

Therefore, CHIC30, DVIC33, CC34, RM
35 includes a processor, the RM 35 performs exclusive control on a processing request from the CPU 1, and in the normal case, CHI.
The C30 and DVIC33 are brought online to perform channel or device interface control.

(B) Description of Operation of One Embodiment First, the operation in a normal state will be described.

The data transfer request from the CPU 1 is transmitted to the CHIC 30 via the channel 2.

(i) When the request includes a data read command, the CHIC 30 requests the RM 35 to determine whether SS4 can be used. R
If CC34 is inactive due to the flag, M35
The CC 34 checks from the management information in the table whether the requested track number of the CHIC 30 is within SS4.

CC if requested data exists in SS4
The data of SS4 is sent to the CHIC 30 according to the instruction of 34, and the data is transmitted from the CHIC 30 to the CIC via the channel 2.
It is sent to PU1.

On the other hand, when the requested data does not exist in SS4, the RM 35 receives the judgment result of CC 34 and releases the free DV.
Examine the presence of IC33, instruct DVIC33,
The requested data is read from the FSU 5 by the C33 and sent to the CHIC 30. Similarly, the data is sent from the CHIC 30 to the CPU 1 via the channel 2.

(ii) When the CHIC 30 includes a data write command in the above-mentioned data transfer request, the CHIC 30 requests the RM 35 to determine whether SS4 can be used. The RM 35 permits the use of the CC 34 if the CC 34 is not operating, and the write data given from the CPU 1 is sent from the CHIC 30 to the CC 34 in the SS4.
When the writing is completed, the writing completion is returned to the CPU 1.

The RM 35 instructs the CC 34 to perform write-back processing on the written write data at an appropriate time such as a vacant time, and the CC 34 gives the write-back unprocessed data of SS4 to the DVIC 33, and writes it back to the FSU 5. Write back control.

In the file control device which performs such a normal operation, when the CC 34 becomes unusable due to a failure, C
A read / write operation that does not use the cache memory (SS) 4 is executed by connecting and disconnecting C34.

At this time, before the failure of CC34 is written in SS4, F
If data that has not been written back to SU5 remains in cache memory (SS) 4, the data in SS4 and FSU5 do not match, and the cache memory contact / separation operation cannot be executed.

Therefore, the recovery process called the write-back proxy is executed in the following procedure.

FIG. 3 is a write back proxy control flow chart of one embodiment of the present invention, and FIG. 4 is an operation timing chart thereof.

When the RM 35 detects a failure in the CC 34, it stops the data transfer using the cache memory (SS) 4,
Set the operation prohibition flag of CC34.

The RM 35 checks the presence / absence of unprocessed writeback data in the SS4 from the writeback completion / unfinished flag, and if the data writeback is all completed, the recovery process ends.

On the contrary, if the data write-back is not completed,
The RM 35 checks the operation flags of the CHIC 30 and DVIC 33.

If all CHICs 30 and DVICs 33 are operating, the completion of these operations is awaited.

On the other hand, when it is determined that the CHIC 30 and DVIC 33 are not operating, that is, there is a non-operating processor, one is selected as the non-operating processor and the processor is set offline.

For example, if the CHIC 30 is not operating, the processor is taken offline and the interface processing is stopped.

Then the RM35 takes this offline CHIC
30 (or DVIC 33) is instructed to perform the write-back process substitution, and the address of the incomplete write-back data is given.

Therefore, CHIC3 is instructed to perform the write-back process.
The 0 (or DVIC33) processor can execute the write-back processing program.

The processor instructed to perform the write-back processing is S
The write-back unprocessed data is read from S4 and given to the online DVIC 33 capable of interface processing,
Write back to FSU5.

When the CHIC 30 (or DVIC 33) processor instructed to perform the write-back process completes the write-back process, the RM 35 is notified of the completion.

As a result, the RM 35 brings the processor of the CHIC 30 (or DVIC 33) that has performed the write-back processing on-line, returns it to the interface processing, and ends the recovery processing.

After that, since the operation prohibition flag of CC34 is set in the step, CC34 and SS4 are separated, and therefore, the access from the CPU1 is all performed to the FSU5.

(C) Description of Other Embodiments In the above embodiment, the write back completion / incompletion flag,
Although the RM 35 has an unprocessed write back address, it may be provided in the shared memory 37.

Further, the CHIC 30 and DVIC 33 are not limited to two and may be plural, and it is not necessary to configure all CHIC 30 and DVIC 33 by the processor.

Although the present invention has been described with reference to the embodiments, the present invention can be variously modified according to the gist of the present invention, and these modifications are not excluded from the present invention.

〔The invention's effect〕

As described above, according to the present invention, in the file controller having the cache memory control function of the write-back method, even when the failure of the cache controller occurs, the mismatch between the data in the cache memory and the data in the file storage device can be prevented. There is an effect that can be done.

Therefore, it contributes to the improvement of the data reliability of the write-back method, which is excellent in high speed but inferior in data reliability.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 is a write back proxy control flow chart of an embodiment of the present invention, and FIG. 4 is an operation in FIG. The timing diagram, FIG. 5, is an explanatory diagram of the prior art. In the figure, 3 ... File control device, 4 ... Cache memory, 5 ... File storage device, 30 ... Channel interface unit, 33 ... Device interface unit, 34 ... Cache control unit, 35 ... Resource management unit .

Claims (1)

[Claims] 1. A channel interface unit (30), a device interface unit (33), a cache memory (4), a cache control unit (34) and a resource management unit (3).
5), write data from a higher order is written in the cache memory (4) by the cache control unit (34), and then write data written in the cache memory (4) is written in the device interface unit. In the write-back control system of the file controller for writing back to the file storage device (5) via (33), at least one of the channel interface unit (30) and the device interface unit (33) is constituted by a processor and write-back is performed. When the cache control unit (34) is provided with a processing function and the write-back processing function is provided under the instruction of the resource management unit (35), the channel interface unit (30) or the device interface unit ( 33) by substituting write-back processing on behalf of the cache memory (4) The write-back control method of the file controller, wherein the data which has not been written back is written back to the file storage device (5).